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1

I/O Buffer Modeling Class2 lectures

Prerequisite Reading – Chapter 7

IBIS spec will be used as

reference

Additional Acknowledgement to Arpad Muranyi, Intel Corporation



2

Additional Information

URLsIBIS home page:http://www.eigroup.org/ibis/ibis.htm

IBIS 3.2 spec:http://www.vhdl.org/pub/ibis/ver3.2/

IBIS-X: http://www.eda.org/pub/ibis/futures/

ToolsGolden Parser:

http://www.eda.org/pub/ibis/ibischk3 Visual IBIS editor, SPICE-to-IBIS tool on IBISweb site. We will use this free tool.http://www.mentor.com/hyperlynx/visibis.cfm

http://www.eigroup.org/ibis/ibis.htm

http://www.vhdl.org/pub/ibis/ver3.2/

http://www.eda.org/pub/ibis/futures/

http://www.eda.org/pub/ibis/ibischk3

http://www.mentor.com/hyperlynx/visibis.cfm


http://www.eda.org/pub/ibis/ibischk3

http://www.eda.org/pub/ibis/futures/

http://www.vhdl.org/pub/ibis/ver3.2/

http://www.eigroup.org/ibis/ibis.htm



3

Key Topics

What is a model?

Importance of accurate models Types of buffer models

IBIS and the portions of an IBIS model

How model data is generated

How to calculate VOL and VOH from a model

Package modeling in IBIS

IBIS HSPICE example

Bergeron diagrams



4

Theories, Modeling, and Reality

“I take the positivist viewpoint that a physical theory is

just a mathematical model and that it is meaningless toask whether it corresponds to reality. All that one canask is that its predictions should be in agreement withobservation. “ 1

1 Steven W. Hawking, September 30 1994, Public Lecture

on “Time and Space” Electrical models can be derived in two ways

From physical structures and propertiesFrom observed behavior

It is irrelevant whether the electrical modelscorrespond to physical reality. It only needs to predict behavior.

Hence all models are behavioral



5

What is a Model?

Electrical representation of a physical device

For example, a transmission line can be modeled as:

A package can be modeled as a combination of transmissionlines and lumped elements.

An input or output buffer can be modeled in various ways aswell.

? ?



6

Importance of Accurate Models

T-lines, package, connectors, vias, return paths, etc.

can all be modeled to extreme detail, but if theinput (stimulus) is not accurate, it‟s wasted.

Garbage in, garbage out.

It is extremely important for engineers tounderstand the origins of model data, be familiarwith modeling types and limitations, and double-check models, whether they create them or they

receive them from someone else! Also, know how your tool uses model data!



7

How do we model I/O buffers?

Linear

Models

Description

M o r e d e t a i l

Behavioral

Models

Linear or non-linear

I-V and V-t data

Transistor

Circuit /

Netlist

Simulation

Speed

All buffer details including

driving transistors, pre-driver

circuitry, receiver diff. amp,

etc.

Intellectual

Property“Sweep-ability”

RS

Slowest

Fast

Fast Very

Somewhat

limited

Very Little

Little

Lots

RHigh

RLow



8

Basic C-MOS Buffer Model

Pad Capacitance

Output / Driver Input / Receiver

ESD Diodes

+

Inherent Diodes in Transistors

Pull-up

Device

Pull-down

Device



9Review Lattice Diagram Analysis

V(source) V(load)

Vlaunch

source r

load r

Vlaunch r load

Vlaunch

0

Vlaunch(1+ r load )

Vlaunch(1+ r load + r load r source )

Time

0

2N ps

4N ps

Vlaunch r load r source

Vlaunch r 2

load r source

Vlaunch r 2 load r

2 source

Vlaunch(1+ r load + r 2 load r source+ r 2 load r 2 source

Time

N ps

3N ps

5N ps

Vs

Rs

Zo V(source) V(load)

TD = N ps 0

Vs

Rt

A signal can bedetermined by justknowing Vlaunch,

rload, and rsource plusdelay



10

Refining Buffer Assumptions

The original assumption was that Vlaunch, rload

and rsource are constant in time and linear. Most buffers are not linear.

In other words, there is a current dependentvoltage that changes with the time varyingvoltage.We call these “I-V” curve elements instead ofresistors, capacitors, or inductors

Vintial Vs ZL

ZL Z0 rload

ZL Z0ZL Z0

rsourceZS Z0ZS Z0

and and

ZL Zload V I( )ZS Zsource V I( )

thenthen

Vintial VsZload V I( )

Zload V I( ) Z0 rload

Zload V I( ) Z0

Zload V I( ) Z0 rsource

Zsource V I( ) Z0

Zsource V I( ) Z0



11

Beginning of Behavioral Buffer Modeling

This was the basis fora buffer specificationthat was created inthe early 90‟s calledIBIS

Consider that Vs is Vs(t) and V is V(t), so Vintial, rload, and

rsource are Vinitial(t), rload(t), and rsource(t). Also, thepropagation functions can be described in a similar manner.Hence the voltage and current response and for all nodesin the network can be determined by replacing the buffer

with the appropriate “I-V” impedance functions and don‟trequire the actual transistor models for the buffer.



12

IBIS and Other Model Types IBIS = I/O Buffer Information Specification

The beginnings of IBIS occurred at Intel duringPentium Pro days. Engineers wanted a way to givebuffer information to customers, and decided on I-Vcurves. The initial IBIS spec was created shortlythereafter. IBIS went through many iterations,eventually adding V-t curves (rev 2.1) and otherfeatures like staged devices (rev 3.0). The currentrevision is 3.2.

Other I-V/V-t model types include:Various simulator vendors have their own internal models.

However most will convert IBIS to their internal format.

We often use controlled switched resistors (V-t curves ofsorts) in SPICE.

Colloquial Terminology ~ V-t = V/T = V(t);I-V = I/V = I(V)



13

What is in an IBIS file?

First IBIS is a standard for

describing the analogbehavior of the buffers ofdigital devices using plainASCII text formatted data

IBIS files are really not

models, they just contain thedata that will be used. Casuallythey may be referred to as amodels but are reallyspecifications.

Simulation tools interpret thisbehavioral specification toimplement their own models andalgorithms

Keyareasofspec



14

Key Portions of an IBIS Model

Die Pad Capacitance

Output / Driver Input / Receiver

ESD Diodes

+

Inherent Diodes in Transistors

Pull-down

Device

I(V)

V(t)

I(V)

V(t)I(V)

I(V) I(V)

I(V)

Pull-up

DeviceVcc

Vss maybe 0V

Vcc

Vss maybe 0V

Pa

ck age

Pa

ck age



15

MOS I-V Curves Impedance of a buffer is dynamic during transitions - between fully open

and fully driving (RON).

Example – let‟s take a look at a high-to-low transition below.

In the next few slides we will learn how we can model this dynamicV-I characteristic.

VOUT (t=0) = VCC

VGS (t=0) = 0

VCC

Triode

(Ohmic)

Saturation

t=2 t=0, t=1

(no current

below Vt)

t=3

t=4

t=5

ID

time

VGS

0

VT

1 2 3 4 5

+

VGS

-

Gate

Source

Drain +

VDS =

VOUT

-

VCC

Drain

Source

Gate

ID

Assume pulled up to Vcc at t=0

Vcc

Vss



16

Generating pull down I-V Data

Output / Driver

Pull-down

Device

off

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

Pull-up

Device

on

Driving

LOW

+I

Sweep V

–Vcc to 2Vcc

Pull-down I-V

Measurement or Simulation SetupI

V

Current ispositive aboveVss perdefinition if I

flows

(N-channel

curve)



17

Generating Ground Clamp I-V Data

Tristate+I

Sweep V

–Vcc to 2Vcc

Ground Diode I-V

Measurement or Simulation Setup

I

V

Output / Driver

Pull-down

Device

off

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

Pull-up

Device

on

Current isnegative belowVss per

definition if Iflows



18

Generating pull up I-V Data

Driving

HIGH

+I

Sweep V

–Vcc to 2Vcc

Pull-up I-V

Measurement or Simulation SetupI V

Vcc

Output / Driver

Pull-down

Device

off

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

Pull-up

Device

on

Current isnegative belowVcc per definitionif I flows.

It is desirable tomake the curvereferenced toVcc. Will explainlater

(P-channel

curve)



19

Generating Power Clamp I-V Data

Output / Driver

Pull-down

Device

off

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

Pull-up

Device

on

Current ispositive aboveVcc perdefinition if I

flows

Tristate+I

Sweep V

–Vcc to 2Vcc

Pull up diode I-V

Measurement or Simulation Setup I

V

Power

Clamp

It is desirable tomake the curvereferenced to Vcc.Will explain next



20

Double Counting Resolution Sometimes the clamp current is not zero in

the range of operation. Before use in IBIS the clamp current needs

to be subtracted. Below is an example for the ground clamp and

pull down data

I

V

Power

ClampI

VccVcc Vcc

I

VccVcc

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

I(V)

V(t)

I(V)

V(t)I(V)

I(V)

Pull up

measurement

Pull up

curve



21

I-V Curves in IBIS

IBIS uses Vcc-referenced I-V curves for all devices

hooked to the power rail (pull-up and high-side diode). This effectively shifts and flips the I-V curve.

Major reason is so same model can be used regardlessof power connection (independent of Vcc).

For example, a 5-V and 3.3-V part can use the same model.

I

V

I

V

Power

Clamp

Power

Clamp

I V

Vcc

I V

Vcc

Pull-upPull-up

Measured Curve IBIS Curve

Driving

HIGH +I

Sweep V –Vcc to 2Vcc

Vcc



22

Simple model of High/Low drive

The high and low switches are ideally

complementaryThey switch in opposite senses simultaneously

Real devices have slightly different switchingcharacteristics.

I(V)

V(t)

I(V)

V(t)

I-V

I-V

Controls V(t)for High Curve

Controls V(t)for Low Curve



23

How to Generate the V-t Data

Driver

Vcc

Pull-down V-t


RLOAD

(typically 50 ohms)

Driver

Pull-up V-t


RLOAD

(typically 50 ohms)

V

t

VOH

+

V

t

VOHVCC VCC

V

t

VCC

+

V

t

VOL

VCC

VOL

4 V-t curves are required2 for each switch for high and low switching

Accuracy is improved if Rload is within 20% of the usage modelload



24

Why Four V-t Curves? It is important for the V-t curves to be time-correlated.

The four V-t curves describe the relative switchingtimes of the pull-up and pull-down devices.

VOH

VCC

VOL

All V-t curve measurements

or simulations are started

at time zero.

NMOS is

completely OFF

NMOS begins

turning OFF PMOS begins

turning ON

PMOS is

completely OFF

NMOS is

completely ON

PMOS is

completely ON

PMOS begins

turning OFF

NMOS begins

turning ON



25

More on IBIS transition time

Two ways to synchronize switch

Build delay into curvesUse version 3.1 Scheduled drivers

Make sure the total transition time to

settling is shorter that half the period.

Start of bit time



26

PVT Corners

PVT = Process, Voltage, Temperature

Models in the past have historically been built at the“corners.” All buffer characteristics are considereddependent parameters with respect to PVT.

Fast Corner = Fast process, high voltage, low temp.Slow Corner = Slow process, low voltage, high temp.

These can be entered into an IBIS model in the “min” and“max” columns.

Fast/strong in the max columnSlow/weak in the min column

In recent generations we have found that just providing fastand slow corners does not adequately cover all effects. Inthese cases other model types can be given (e.g., “maxringback” model).

Compensated buffers explode the combination of requiredbuffer corners.

They use extra circuits to counteract (compensate) PVT effectsThis makes PVT and buffer characteristics independentparameters.



27

“Envelope” or “Spec” Models

Historically, we have repeatedly predicted buffer

strength and edge rates incorrectly.Buffer strengths are often weaker in silicon.

Edge rates are often slower in silicon.

One approach that can be used is to create

“envelope” or “spec” models. For example: I

V

Envelope.

All measured curves should

fall within these specs.

V

t

Key point!!!:

These spec curves can be

given to I/O designers to

describe required buffer

behavior.

Weak

Strong



28

Issues with spec curve models

These are legal according to the spec.

Sometimes more qualification isrequired.

I

V

Envelope.

All measured curves should

fall within these specs.

V

t

Weak

Strong

Instantaneouslya short

Instantaneously

an openNon-monotonic

29



29

Example: Create CMOS Model

Given:

Vcc = 2.0 VMeasurement threshold = 1 V; VIL = 0.8 V; VIH = 1.2 VNMOS RON = 10 ohmsPMOS RON = 10 ohmsAll edge rates are ramps of 2 V/ns

Capacitance at the die pad of the buffer = 2.5 pFClamps are 1 ohms and start 0.6V above and below railsPMOS starts turning on 100 ps after NMOS starts turningoff (rising edge)NMOS starts turning on 100 ps after PMOS starts turning

off (falling edge) Will use Mentor Graphic Visual IBIS editor in

examplehttp://www.mentor.com/hyperlynx/visibis.cfm

30





30

Example: Header information

31



31

Package definition and pin allocation

mysimple_buffer

2pF

12mohms2nH

signal001

32



32

Model statement Notice the name “special_IO” is assign to our single pin before. Many pins and models can specified for single component

mysimple_buffersignal001

2pF

12mohms2nH

2.5p

33



33

I-V curves

Construct in this

example with a spreadsheet

Break session to IBISEdit to view I/V curves

Assignment: Use thisexample and change thepull and pull down curvesto 15 ohms. Check withVisual IBIS. Correct VTwaveforms.

34



34

The 4 V-t waveforms w/ spec 100ps delay

35



35

Match V-t and I-Curves

The intersection of the load line of the

fixture (specified in the waveformsection) and a corresponding I-V curvedetermines the Voh and Voh thatshould to be used in the respective V-tsection

I

Vdd

Pull down

Vdd Vdd

Vdd Vol

V-t

More on

load lines

later

Fixture load

line

R_fixture

36



36

End and Ramp

The ramp is specified but the simulatortool can determine whether to use theramp or the V-t data

The End statement is require The IBIS 3.1 and 2.1 are spec are actually

readable IBIS code and can be view with anIBIS editor.

37



37

GTL+ on die termination

Recall that a GTL buffer contains pull-down

transistors only No switched PMOS Many of Intel‟s processors and chipsets have

started to include termination devices inside theI/O buffer.

This eliminates the stub on the PWB to connect tothe termination resistance

Vcc

On- or off-die

resistor for pull-up

and termination

38



38

On-die Termination

One way to include on-die termination is to use

superposition and add the termination currents tothe diode currents in the clamp sections.

The clamps are always active in an IBIS model,regardless of whether the buffer is driving or

receiving. Since the termination is always active,also, this scheme works well.

I V

Vcc

On-die

Pull-up

Resistor

I

V

Power

Clamp

Vcc+

I

V

Power Clamp + On-die term.

(Put full curve into power clamp

section of IBIS model.)

Vcc

39

P k d l B



39

Package Modeling in IBIS

Three ways to model packages in IBIS:

Lumped R, L, C values in IBIS filePackage models

EBD (Electrical Board Description)

Package models and EBDs follow this convention:

[Len=l R=r L=l C=c] Examples:

Lumped resistor: Len=0 R=50 L=0 C=0

Capacitor package: Len=0 R=[ESR] L=[ESL] C=1uF

Package trace: Len=1.234 R=0 L=10E-9 C=2E-12

40



40

Example: VOL Calculation – Resistor Load Line

The I-V for the resistor load is below

Vcc = 2V

50 ohmsRLoad

I

V

Pull-downI-V curve

Load line

Slope = -1/RLOAD

Vcc

Vcc

RLOAD

VOL

50 ohm load line

Zero Current

ZeroVoltage

41

E l V C l l i b ff



Example: VOL Calculation - buffer

Now create the NMOS I-V curve for load line

analysis below:

~10ohms

I

V

Pull-downI-V curve

Vcc

Vcc

RLOAD

VOL

~10

I-V

42



Example: VOL Calculation

Using the intersection of the NMOS I-V curve and

load line, calculate VOL

: The Vol should correspond the Vol in the V-twaveforms

~10ohms

Vcc = 2V

50 ohms

50 ohms

I

V

Pull-downI-V curve

Load line

Slope = -1/RLOAD

Vcc

Vcc

RLOAD

VOL

Sanity check and solution:

Vcc = 2V

50 ohms

10 ohms

VOL = 0.33 V

50 ohm load line

~10

I-V

Zero Current

Zero

Voltage

43

E l C l l V



Example: Calculate VOH

calculate VOH from the intersection of PMOS I-V

curve and the resistor load line: The Voh should correspond to the Voh in the V-T

waveforms

~10ohms

Vcc = 2V

65 ohms

30 ohms

I

VVOH

VCC

Example: VOH = 1.5 V

Needs to agree with V-T data

~10

I-V

30 ohm load line terminatedto ground this time)

44



Using IBIS Models in HSPICE

Use the IBIS file presented earlier (10 ohm

up down resistor. Compare to

Using prior HSPICE example and MYBUFsubciruit library and switch case with alters.

New net list name: testckt_ibis.sp

0-2V.33ns r/f fulltransition time

10

45



Recall HSPICE Block Diagram

Printed WiringBoard

Buffers

p a

c k a g e

p a

c k a g e

Receiver

D a t a

g e n e r a t o r

46

C t th lib i f MYBUF



Create three libraries for MYBUF

„driver‟ – source/resistor model

„driver_ibis‟ – 10 ohm CMOS IBIS modelusing ramp data

„driver_ibis_two‟ - 10 ohm CMOS IBIS model2 V-t curves for rising and falling edges. (4

total) Good example to show how to use libraries.

In some cases we start with a behavioral modelmove to a transistor model to fine tune the

buffer design and solutions space.This modularity enables this migration path withminimal impact to the system model.

47

Th th lt d t 0 t 1 t 2



The three alters produces .tr0, .tr1, .tr2

Before the end statement insert the

alter statementsAdjust the pulse source to .333 ns

48

R L b



Resistor Source Library

Use delay to synchronize cases

We will force IBIS to start on the 50%

point in the bit drive waveform

49

HSPICE IBIS l



HSPICE IBIS example

This is a simpleexample. Many more

controls are possible Buffer=2 tells hspice

to use an outputbuffer model

Ramp_fwf and

ramp_rwf = 0 meansuse the ramp Ramp_fwf and

ramp_rwf = 2 meansuse the 2 V-t curvesfor each edge

The edges are scaledby 1/10 also to matchthe resistor/source

What does NINT do?



51

Cl l k t i i



Closer look at rising wave

Ramp isslightly

distorted

52

Cl l k t f lli d



Closer look at falling edge

Rampproducesunexpectedresults

53

Additi l IBIS M d li I f ti



Additional IBIS Modeling Information

IBIS files can be tuned to produce

desired performanceSimulator may vary on how the IBIS

files are used. Especially when the used

far away from the specified loads.

54

Bergeron Diagrams Intro



Bergeron Diagrams – Intro. A Bergeron diagram is another way of analyzing a transmission

line. It is useful to analyze:

Reflections from non-linear drivers or loadsUsage is in industry is low – Can do same with equations andsimulators.

First example – analyze a low-to-high transition: Process

1.

Draw all I-V curves of transmitter and receiver2. Transmission lines are load lines of 1/Zo or -1/Zo depending on

direction of wave.3. Start at initial condition. For this case, it is 0V, 0A and move on

the transmission line slope to intersection of load.4. Determine intersection V and I.

5. Create equation for transmission line with -1/Zo slope at theintersection6. Bounce back and forth using the parallel transmission line load

curves and the receiver load which is a 0v horizontal line for thiscase and repeat until stable.

7. For this case, voltage on the load line is for Tx and a 0v is for Tx



56

Determine Initial Voltage



Determine Initial Voltage

at TxSolve for V

V

Zo

V

R

Vs

R

V Vs

R ZoZo

The intersection is where source resistor load line and

transmission line forward wav e is

Initial wave looks like the

voltage divider we e xpect

Zo

Zo R Vs 0.833

0 0.4 0.8 1.2 1.6 20

0.024

0.048

0.072

0.096

0.12

V

Zo

V

R

Vs

R

V

First Forward Wave Transmission Line Load Curv eI V

Zo

Source Resistor Load Line ( M ore o n f(V) later)I f V( )orI V

R

Vs

R

V 0 .1 2 Zo 50R 10Vs 1let

Bergeron Analysis



58

Find n xt lt t Tx in



Find next voltage at Tx again

Now the wave follows the 1/Zo I=mV+b and we solve for b again from abo

b 2

Vs

R Zo and I

V

Zo 2

Vs

R ZoThis line intersects the Tx load line

I V

R

Vs

R so

V

R

Vs

R

V

Zo2

Vs

R Zo

at TxV Vs

3 R Zo

R Zo( )2

Zo I Vs Zo R

R Zo( )2

0 0.4 0.8 1.2 1.6 20.1

0.08

0.06

0.04

0.02

0

0.02

0.04

0.06

0.08

V

Zo

V

R

Vs

R

V

Zo 2

Vs

R Zo

V

Zo2

Vs

R Zo

V

Vs 3 R Zo

R Zo( )2

Zo 1.111

59

Find voltage at Rx again



Find voltage at Rx again

The re flected wave follows a 1/-Zo line. Again the task is to find b. But since w

a V and I above th is is easy

I VZo

b b 4 Vs R

R Zo( )2

Then I VZo

4 Vs R

R Zo( )2

when I=0 V 4 Vs R

R Zo( )2

Zo I 4 Vs R Zo 1

R Zo( )2

at Rx

0 0.4 0.8 1.2 1.6 20.1

0.08

0.06

0.04

0.02

0

0.02

0.04

0.06

0.08

V

Zo

V

R

Vs

R

V

Zo 2

Vs

R Zo

V

Zo2

Vs

R Zo

V

Zo 4 Vs

R

R Zo( )2

V

4 Vs R

R Zo( )2

Zo 0.556

And so on....

60

The non linear case



The non-linear caseBergeron Analysis For Non-Linear I/V

let Vs 1 R 20 Zo 10 V 0 .01 2

IfctV( )

V

2

52

R

Vs

R

Source I-V curve)

I V

Zo First Forward Wave Transmission Line Load Curve

0 0.4 0.8 1.2 1.6 20

0.024

0.048

0.072

0.096

0.12

V

Zo

Ifct V( )

V

GivenI0

V0

ZoI0

V0

2

5

2

R

Vs

R

61

Use MathCad Solve blocks at Tx



Use MathCad Solve blocks at Tx

I1

V1

Find I0 V0( )

2 4.854844553088357314810-2

.48548445530883573148

need to choose correct solution, look at gr

to pickI1

V1

0.049

0.485

at Tx

Given ne xt line is

Given

I1 V1

Zo b

b1 Find b( ) 9.709689106176714629610-2

b1 0.097

62

First Step at the Rx



First Step at the Rxat the axis I2 0

Given

I2

V2

Zo b1 V2 Find V2( ) .97096891061767146296

0 0.4 0.8 1.2 1.6 20

0.024

0.048

0.072

0.096

0.12

V

Zo

Ifct V( )

V

Zo b1

V

V2 0. 97 1at Rx

Reflected line I3 0

Given

I2 V2

Zo b2 b2 Find b2( ) 9.709689106176714629610

-2

I3 V3

Zo b2

63

Assignment:



Assignment:

0 0.4 0.8 1.2 1.6 20

0.024

0.048

0.072

0.096

0.12

.12

0

V

Zo

Ifct V( )

V

Zo b1

V

Zo b2

20 V

Solve for next voltageand current at Rx

64Example: Under-damped Case with Diode



I

V

Vcc

Example Under damped Case w th D ode

Multiple I/V curves can be overlaid to estimate

performanceIn this case an ideal diode‟s I-V characteristics gives a feelfor what to expect

20 ohms

Vcc = 2V

60 ohms

Pull-upI-V curve

DiodeI-V curve

1/Z0

t=0 TD

1V

2TD

2V

3TD 4TD 5TD 6TD

-1/Z0

65

Linear vs Non-linear



Linear vs. Non-linear

The accuracy of a linear approximation can be

determined with a Bergeron diagram:

1/Zo

I

NMOS curvePMOS curve

Voltages from the

reflections are close to

linear approximation

1/Zo

Voltages from the

reflections are NOT close

to linear approximationI

V

V

66

Summary: We now understand



Summary: We now understand

What is a model?

Importance of accurate models Types of buffer models

IBIS and the portions of an IBIS model

How model data is generated

How to calculate VOL and VOH from a model

On-die termination

Package modeling in IBIS

Bergeron diagrams