T.Pullaiah1
1
2
3 Professor &Principal, Sri Devi women
Abstract: Network-On-Chip (NOC) structuremakes a fitting substitution for system on chipdesigns incorporating large number of processingcores. In network the main source of powerdissipation is in the network on chip links. Thedynamic power dissipation in links is majorcontributor to the power consumption in NOC. Thiseffort investing sates the reduction of transitionactivity using gray coding schemes. Our advancedscheme does not require any change of the routersand link architecture. The future scheme uses thebinary to gray conversion at the transmitter and grayto binary conversion at the receiver. Aninvestigational result has shown the effectiveness ofthe proposed schemes, with respect of powerdissipation and area overhead in the NetworkInterface (NI) as compared with data encoding.
Keywords-Binary to gray conversion, Dataencoding, Interconnection on chip, Low power,Network-on-chip (NOC), Power analysis, Gray tobinary conversion.
I.
The Network on chip is an emerging approach for
the implementation of on chip communicationarchitecture. The system on chip designsincorporating large no. of processing cores andmodular structure of Network on chip makes afitting replacement for system on chip. Networkon chip is intended to solve the shortcomings ofthese, by implementing a communication networkof switches, micro routers and resources. Systemon chips are not containing IP cores only andtraditional methods for communication such asbus are not suitable solution for future Systemon chips. The Network-on Chip has emerged asunderlying
2 Dr. B. L .Malleswari3
ing, Hyderabad.
infrastructure for communication betweenIntellectual Property cores. Network on chip issolution for communication architecture of futureSystem on chips that are composed of switchesand IP cores where communicate among eachother through switches. Between IP cores datamove in the form of packet. As the technologyshrinks the power ratio between link and routerincrease making link more power hungry thanrouters. network on chip communication givesflexibility in the topology, in support to that theflow control, Advance routing algorithms, selfswitching techniques guarantying the quality ofservice. Network on chip is an approach todesign the communication subsystem betweenintellectual property cores in a system on chip.The communication strategy in system on chipuses dedicated buses between communicatingresources.
This will not give any flexibility since the needsof the communication, in each case, have to bethought of every time a design is made. Anotherpossibility is the use of common buses, whichhave the problem that it does not scale verywell, as the number of resources grows.
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, Dr. Manjunatha Chary
Associate Professor, Krishna Murthy Institute of Technology and EngineerProfessor & Head, GITAM University, Hyderabad.
s engineering college, Hyderabad.
The advances in fabrication technologyallow designers to implement a whole system on asingle chip, but the inherent design complexity ofsuch systems makes it hard to fully explore thetechnology potential. Thus, the design of Systems-on-Chip (SoCs) is usually based on the reuse ofpredesigned and pre- verified intellectual propertycore that are interconnected through specialcommunication resources that must handle verytight performance and area constraints. In additionto those application-related constraints, deepsubmicron effects pose physical design challengesfor long wires and global on-chip communication.A possible approach to overcome those challengesis to change from a fully synchronousdesign paradigm to a globally asynchronous, locallysynchronous (GALS) design paradigm. A networkon- Chip (NoC) is an infrastructure essentiallycomposed of routers interconnected bycommunication channels. It is suitable to supportthe GALS paradigm, since it provides asynchronouscommunication, scalability, reusability andreliability.
II.
The accessibility of chips are growingevery years. In the next several years, theavailability of cores with 1000 cores is foreseen[3].Since the focus of this paper is on reducing thepower dissipated by the links, here we brieflyreview some of the works in the area and link powerreduction. Also these include some technique.There are, use of shielding [4], [5],
increasing line-to-line spacing [6], [7], and repeaterinsertion [8]. Thus the above all the techniqueshaving large area overhead. Another one method isthe data encoding technique it mainly fo cus onreducing the link power reduction. The dataencoding technique is classified into twocategories. In the first category is mainlyconcentrate on minimizing the power due to self-switching activity of each bus lines and avoid thepower dissipation due to coupling switching activity.In this category, bus invert [BI] [9] and INC -XOR[10] have been proposed. When the random patternsare transmitted via these lines. On the other hand,gray code [11], T0 [12], working -zone encoding[13], and T0-XOR [14] have been proposed for thecase of correlated data patterns.
In this first category of encoding is notsuitable for applied in deep sub -micron metertechnology nodes where the coupling capacitance is a
main part of the total interconnects capacitance. Thiscauses the power due to the coupling switchingactivity to become a large portion of the linkpower reduction.
In the second category concentrate onreducing power dissipated through the reduction ofthe coupling switching [7], [14] -[15]. The techniqueproposed in[16], proposed a method on powereffective Bus Invert. In [15] they presented a methodbased on Odd/Even Bus -Invert techniques. If thenumber of switching transitions is half of the linewidth means the odd inversion is performed. In [9],the number of transitions from 0 to 1 for two datapackets is counted.
The number of 1 s in the data packet islarger than the half of the links means the inversionwill be performed and the number of 1 s is reduced to0 transitions when the packets are transfer throughthe links. In [17], the technique is used to reducingthe coupling switching. From this method, theencoder counts the Type I transitions with theweighting coefficient of one and the Type IItransitions with the weighting coefficient of two. Ifthe number of 1 s is larger than half of the linksmeans the inversion will be performed and itreducing the power consumption on the links. Thetechnique proposed in [1] using the data encodingtechnique.
This technique illustrate if the bits areencoded before they are injected into the networkwith the goal of minimizing the self-switching andthe coupling switching in the links. These two are themain reason for the link power dissipation. Here theyare classified the encoding technique into threescheme based on the four Types. In scheme 1 usingthe odd inversion and scheme 2 using the both oddinversion and full inversion and scheme 3 using theboth odd, full and even inversion. Based on the odd,full and even inversion the power dissipation isreduced o n the Network on chip (NOC) links. In thispaper we present gray encoding technique, whichfocused on reducing the errors during the transitionfrom transmitter to receiver and reducing the powerdissipation in the links.
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Development of technology allowsdesigners to use an Evolution system on chips. Butcomplexity of such systems creates a difficult toinheritance and using their properties to growth andcompleting them. So designing of systems on chipwhich is based on using of their previous properties,by correlation of resources should manage togetherin a common confine, introduces some challengesfor physical designing and way of changing systemphysical architecture. A network on chips (NOC)consists of interior communication resources whichhave relation by channels. Rectifying switchingactivity in networks and also reduction of datachanging in these networks were considered. Fordecreasing them, encoding or decoding can be usedin this algorithm.
The basic idea of the proposed approach isencoding the flits before they are injected into thenetwork with the goal of minimizing the self-switching activity and the coupling switchingactivity in the links traversed by the flits. In fact,self- switching activity and coupling switchingactivity are responsible for link power dissipation.In this paper, we refer to the end-to-end scheme.This end-to-end encoding technique takes advantageof the pipeline nature of the wormhole switchingtechnique. Note that since the same sequence offlits passes through all the links of the routing path,the encoding decision taken at the NI may providethe same power saving for all the links.
In this section, we present the proposedencoding scheme whose goal is to reduce powerdissipation by minimizing the coupling transitionactivities on the links of the interconnectionnetwork. The datas could be classified into 4 typesbased on the bit transition. The data which havezero bit transition that is type 1 and one bittransition in the sense that is type 2 and two bittransition in the sense that is type 3 and more than 2bit transition in the sense that is type 4. In thisproject for reduce the bit transition we are doingencoding scheme. The type 4 is encoded into type1 and transmitted at last it is decoded and getthe(type 4) original signal. And type 3 isencoded in to type 2 and its
transmitted and get the original signal (type 3). There
is no change on type 2 and type 1 because of thereason bit transition value is low.
The encoder and the decoder were designedin Verilog HDL described at the RTL level,synthesized with synopsys design compiler andmapped.Some of encodings reduce expenditureonly when the number of bosses are high or some ofencodings have high level of efficiency when thenumber of data transferring are many, some ofmethods require knowledge of static parameters andinterior traffic, but we use a method that it needs noone of above, in fact we use a common method.
Base of this method is encodingsperformed on Bus networks. In these methods,method of encoding by decreasing average numberof signal transferring has suggested strongly. Insome of these methods some parameters of interiortraffic is required, but in this research has suggestedstrongly. In some of these methods some parameters
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III.
IV.
of interior traffic is required, but in this research wesimulate a method on networks.
Which doesn't require such information.Usually in encoding methods based on possibility,there's no need to know about network traffic, theyact according to statistic flow. Intelligent bit isencoded according has suggested strongly. In someof these methods some parameters of interior trafficis required, but in this research to it's past and realvalue and acts based on approximate statisticinformation.
The main goal of the proposed encodingscheme is to reduce the power dissipation byminimizing the coupling transition activities on thelinks of the interconnection network. In [17], theyare classified four types of coupling transitions. AType I occurs when one of the line is switches andre maining one is unchanged. A Type II occurswhen one of the lines switches from low to high andanother one is switches from high to low. A Type IIIoccurs both the lines switches simultaneously. AType IV occurs when both the lines are remainsunchanged. The coupling switching activity(Tc) is defined as a
Tc = K1T1 + K2T2 + K3T3 + K4T4 eq. (1Where Ti is the average number of Type I
transition and Ki is the corresponding weight.
A.The gray code is also knows as reflected
binary code. It is a binary numeral system, where twosuccessive values differ in only one bit. The reflectedbinary code was originally designed to preventfalse output from electromagnetic switches. It ismainly used for error correction application in digitalcommunications.
B.The problem with binary codes is that, with
real switches. The switches will change statesexactly in synchronously. In binary code, the twosuccessive values differ in one or more bits. if theoutput pass through a sequential system then thesequential system may store a false value. Thegray code solves the above problem by changingonly one bit at a time.
Table 1: Binary to Gray converter
C.In scheme 1, our main goal is to reducing
the number of Type 1 transitions and Type 2transitions. Type 1 transitions is converted into TypeIII and Type IV transitions and Type II transitions isconverted into Type I transitions. This schemecompares the two data s based on to reducing thelink power reduction by doing odd inversion or noinversion operation.
Table 2: Effect of Odd and Even inversion onchange of Transition Types
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Fig.1.Scheme1.(a)Block diagram. (b) Architecturefor encoder blockTy > Tx eq. (2)Ty > 0.5 (w-1) eq. (3)
The general block diagram in Fig. 1(a) issame for scheme 1, scheme 2 and scheme 3. The w-1 bit is given to the one input of the binary to grayconversion block. This block converts the originalbinary input into gray output. The output of the graycode is given as input of encoder block and anotherinput of the encoder block is the previously encodedoutput. The encoder block compares these twoinputs and performing the any one of the inversionbased on the transition types. The block E is varyfor all the three schemes.
Comparing the current data and previousencoded data to decide which inversion isperformed for link power reduction. Here the TYblock this takes two adjacent bits from the giveninputs. From these two input bits the TY blockchecks what type of transitions occurs, whethermore number of type 1 and type 2 transitions isoccurring means it set the output state to 1,otherwise it set the output to 0.
The odd inversion is performed for thesetype of transitions.Then the next block is theMajority code it checks the state, if the number ofone s is greater than zeros or not and it implementedusing a simple circuit. The last stage using the XORcircuits, these circuit is used to perform theinversion on odd bits. The decoding is performed bysimply inverts the encoder circuit when theinverting bit is high.
D.
In scheme II, our main goal is to reducingthe number of Type II transitions. Type II transitionsare converted into Type IV transitions. This schemecompares the two data s based on to reducing the linkpower reduction by doing full inversion or oddinversion or no inversion operation.
T2 > T4** eq. (4)
Full and odd inversion based this advancedencoding architecture consist of w-1 link width andone bit for inversion bit which indicate if the bittravel through the link is inverted or not. W bits linkwidth is considered when there is no encoding isapplied for the input bits. Here the TY block fromscheme 1 is added in scheme 2. This takes twoadjacent bits from the given inputs. From these twoinput bits the TY block checks what type oftransitions occurs.
We have T2 and T4**blocks whichdetermines if any of the transition types T2 andT4**occur based on the link power reduction. Thenumber of ones blocks in the next stage. The outputof the TY, T2 and T4** send through the number ofone s blocks. The output of the ones block is log 2w.The first ones block is used to determine the numberof transitions based on odd inversion.
The second ones block determines thenumber of transitions based on the full inversion andthe then another one ones block is used to determinethe number of transitions based on the full inversion.These inversions are performed based on the linkpower reduction. Based on these ones block theModule A takes the decision of which inversionshould be performed for the link power reduction. For
.None of the output is set to if there is noinversion is takes place. The module A isimplemented using full adder and comparator circuit.
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The block diagram of the decoder isshown in Fig.3. The w-1 bits input is applied in thedecoder circuit and another input of the decoder isprevious decoded output. The decoder blockcompares the two input data s and inversionoperation is performed and w-1 bits output isproduced. The remaining one bit is used toindicate the inversion is performed or not. Thenthe decoder output is given
to the gray to binary block. This block co nverts thegray code into original binary input. In decodercircuit diagram (Fig.4.) consist of TY block andMajority vector and Xor circuits. Base d on theencoder action the TY block is determined thetransitions. Based on the transitions types themajority blocks checks the validity of the inequalitygiven by(2). The output of the majority voter isgiven to the Xor circuit. Half inversion, fullinversion and no inversion is performed based onthe logic gates.
E.
In scheme III, we are adding the eveninversion into scheme II. Because the odd inversionconverts Type I transitions into Type II transitions.From table II, T 1**/T1*** are converted into TypeIV/Type III transitions by the flits is even inverted.The link power reduction in even inversion is largerthan the Odd inversion.
The encoding architecture (Fig.5) inscheme III is same of encoder architecture inscheme I and II . Here we adding the Te block tothe scheme II. This is based on even invertcondition, Full invert condition and Odd invertcondition. It consist of w-1 link width input and thew bit is used for the inversion bit. The full, half andeven Inversion is performed means the inversion bit
.The TY, Te andT4** block determines the transition types T2, Teand T4**. The transition types are send to thenumber of ones block. The Te block is determined ifany of the detected transition of types T 2, T1**and T1**. The ones block determines the numberof ones in the corresponding transmissions of TY,T2, Te and T4**. These number of ones is given tothe Module C block. This block check if odd, even,full or no invert action corresponding to the outputs
10 or respectively, should beperformed. The decoder architecture of scheme IIand scheme III are same.
Fig.4. Decoder architecture scheme II
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V. Results and Discussion
Fig.6. shows the simulation result ofscheme I (reducing Type I and Type II transitions)using gray encoding technique. The output of thescheme I reducing the number of Type I and TypeII transitions by using the odd invert condition.Fig.7. shows the simulation result of scheme II(convert Type II transitions into Type IV ) usinggray encoding techniques. In scheme II the numberof type II transition is converted into Type IVtransitions by using the odd and full inversion
condition.
Fig.6. Simulation for scheme I using gray encoding
Fig.7. Simulation for scheme II using gray encoding
Fig.8. shows the simulation result ofscheme III(Type I (T1***) converted into Type II)using the gray encoding. The output of the schemeIII reducing the number of Type I (T 1***) intoType II transitions by using odd, full and eveninversion.
Fig.8. Simulation for scheme III using grayencoding
VI.
In this work, the gray encoding techniqueis implemented for reducing the transition activity inthe NOC. This gray encoding scheme aimed atreducing the power dissipated by the links of anNOC. In fact links are responsible fora significant fraction of the overall power dissipatedby the communication system. The proposed
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encoding schemes are agnostic with respect to theunderlying NOC architecture in the sense that ourapplication does not require any modificationneither in the linksnor in the links. The proposedarchitecture is coded using VERILOG language andis simulated and synthesized using cadencesoftware. Overall, the application scheme allowssavings up to 42% of power dissipation and withless than 5% area overhead in the NI compared tothe data encoding scheme.
In the future, the Network On Chip(NOC) implementation using different types ofrouter technique will be analyzed. Comparison onmany encoding techniques such as gray encodingtechniques will be analyzed in which the area,delay, power and the performance of the NOC willbe investigated and use for high speedapplications.
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Mr. T. Pullaiah, Associate Professor, Departmentof ECE , Krishna Murthy Institute Technology andEngineering ,Hyderabad, TS. B.E (ECE) fromSRKR Engineering College, Bhimavaram, AndhraUniversity, AP ,completed in 1996, M.Tech(DSCE) from JNTU Anantapur,JNTUA,completed in 2007. Presently persuingPh.D from JNTUH Hyderabad on Datacompression Techniques He has 17 years ofexpereince.
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Dr. K. Manjunathachari, Professor & Head ofECE, Dept. of ECE, School of Technology,GITAM University, Hyderabad. He completed hisB.E (ECE) from Gulburga University, Gulbarga,and M. Tech (DSCE), JNT University, Hyderabadin 1996. He was awarded Ph D from JNTUniversity, Kakinada in 2010 in Image processing.He has 21 years of experience.
Dr. B. L. Malleswari, Professor & Principal of SriDevi Women s Engineering College, Hyderabad.She completed B.E (ECE) from SRKREngineering College, Bhimavaram, AndhraUniversity, AP in 1988 and M.S. Electronics&control Systems DLPD from BITS PILANI in1993. She completed her Ph D from JNTUUniversity, Hyderabad, in 2008. Her areas ofinterest are spatial technology for Navigation &modeling GPS. She has 28 years of experience.
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