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Electronics Laboratory II
EECS 3440
Lab Manual
January 2002
rev. 2
editor
Roger King, prof. EECS
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Foreword
This lab is a continuation of the lab experience included with the course Electronics I.
As such, it would be repetitious to include the sections describing the equipment, documenting
procedures, or reviewing SPICE. For the same reason, a comprehensive set of data sheets is not
included in this lab manual. (The PN2222A data sheet is included because of its frequent use.)
It is assumed that the student has retained a copy of the lab manual from the Electronics I
(EECS 3400) course.
The main new topics covered by this lab are frequency response and feedback in analog
electronic systems. These are fundamental for any practical electronics, and in addition, each of
these has a counterpart in the digital signal processing world. An understanding of the behavior
of the analog system is the best preparation for an understanding of the correspondingdigital-domain behavior. As with Electronics I, this lab will also emphasize the use of SPICE
along with hands-on experimentation to gain an intuitive understanding of the electronics
involved. The student is encouraged in each experiment to simulate the lab using SPICE, to
hand work a simplified analysis, and to compare these with the observed experimental behavior.
This lab is continually being redeveloped. Please give the instructor your feedback
concerning the lab experiments and procedures so that the future manuals can be as error-free as
possible.
Prof. Roger King, EECS
July 1998
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Table of Contents
51Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47Experiment 13 Analog/Digital Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43Experiment 12 Wien Bridge Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39Experiment 11 Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35Experiment 10 Negative Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
Experiment 9 Complementary-Symmetry
Push-Pull Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27Experiment 8 Differential Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Experiment 7 BJT High-Frequency
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
Experiment 6 Bypass and Coupling Capacitor
Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Experiment 5 Small-Signal CC and CB
mplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
Experiment 4 JFET Common-Source
mplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
Experiment 3 SPICE Simulation of a JFET
Common-Source Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5Experiment 2 741 Op-Amp Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Experiment 1 SPICE Modeling the 741
Op-Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Experiment 1
SPICE Modeling the 741 Op-Amp
Introduction
The purpose of this experiment is to gain experience with ac and transient SPICE
simulation procedures, and to learn about the slew rate and bandwidth behaviors of a typicalgeneral-purpose op-amp. A simple model of the internal structure of the 741 op-amp will be
used.
Equipment Needed
vSPICE model for a 741
general-purpose op-amp
vPC running a current version of
PSpice
Procedure
Use PSpice to run an analysis of the circuit of Fig. 1. A model for the 741 op-amp isgiven in Fig. 2. (The model in Fig. 2 is also available from the instructor on disk.) The actual
circuit requires two 15-V power supplies for the op-amp; the model in Fig. 2 works without
having to explicity show these power supplies. Most general purpose op-amps have two internal
stages of gain: the first one is modeled in Fig. 2 as the voltage-controlled current source
Gstage1, and the second one is modeled as the voltage-controlled voltage source Estage2.
1. Make the input source Vin a pulse voltage source (VPULSE) in series with a transient
sine source (VSIN). Set the ac component of VPULSE to 1 V, and its pulse component
to transition from -1 V to +1 V as a square wave with a period of 400 s (200s at -1 V,
and 200 sat +1 V). Set up VSIN for an offset voltage of 0, an amplitude of 50 mV, and
a frequency of 40 kHz. The input voltage to the inverting amplifier will then be a 1-V acsignal during the ac analysis (a steady-state phasor analysis), and it will be a 50-mV
40-kHz sine wave added to a 1-V 2.5-kHz square wave during the transient simulation.
2. Run an ac sweep from 0.1 Hz to 10 MHz, and a transient simulation for 500 s.
1
Fig. 1 Inverting amplifier using a 741 op-amp.
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3. Use PROBE to view the results of the ac sweep. The input ac voltage Vin will have a
constant magnitude of 1 V (0 dB); display the dB magnitude of the output voltage Vout.
Determine the high-frequency cutoff of the inverting amplifier by finding the frequency
at which the output is reduced to 3 dB less than its low-frequency value.
4. Determine why the gain of the inverting amplifier is not constant up to a very highfrequency. Use PROBE to plot the gain of the op-amp itselfby adding the plot
DB(Vout/-Vid) to the previous plot. Note that -Vid is the input voltage to the op-amp,
not the input voltage to the circuit. Print this composite plot of the inverting circuit gain
together with the op-amp gain for a frequency range of 0.1 Hz to 10 MHz.
5. Use PROBE to view the results of the transient run. Plot the output voltage Vout
together with -10 times the input voltage Vin. Ideally, these two traces should coincide.
However, there will be some notable discrepancies. Print this composite plot.
6. The output voltage will show evidence of slew rate limitingat the times that the square
wave transitions. During this time, the Vout rises or falls with a well-defined slope, andthe small sinusoidal component of signal disappears. To find out why, add an additional
Y-axis to the plot and add a trace of the output current leaving the first stage, I(Gstage1).
The vertical scale of this new Y-axis should be -15 A to +15 A, and there should be
evidence that the current output of stage 1 is clipping. Print this composite plot.
Report
There is no formal report for this lab. Simply record your findings and comments and
submit them in a homework format. In the following, be careful to distinguish the op-amp by
itselffrom the complete amplifier circuit of Fig. 1. Please answer the following questions:
1. What is the voltage gain (in dB) of the circuit of Fig. 1?VoutVin
2. The high-frequency cutoff fHis defined as the frequency at which the gain is down to
3 dB less than its low-frequency value. What is the value of fHfor this amplifier?
3. What is the voltage gain of the op-amp itself (in dB) at very low frequencies?VoutVid
Describe the variation of the op-amp gain with respect to frequency. What is the value of
fHfor the op-amp by itself?
4. Describe the behavior of this inverting amplifier when it is producing a 10-Vsquare-wave output voltage, especially with regard to the regions where Vout is in
transition. Why does the sine waveform disappear from the output waveform during the
transition times?
SPICE Modeling the 741 Op-Amp
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Table 1Device Parameters for the Inverting Amplifier SPICE Model
Dbreak D(
IS=1E-14
CJO=0.1pF
RS=0.1)
TABLE=
(-50mV,-13V)
(+50mV,+13V)
TABLE=
(-75mV,-15uA)
(+75mV,+15uA)
DC=0
AC=0
VOFF=0
VAMPL=50mV
FREQ=40kHz
DC=0
AC=1V
V1=-1V
V2=+1V
TD=200us
TR=0
TF=0
PW=200us
PER=400us
D1 & D2Generic diodes
(use Dbreak model)
Estage2Voltage amplifier
(VCVS) with
saturation
Gstage1Transconductance
amplifier (VCCS)
with saturation
VSINInput source for
transient sine wave
VPULSEInput source for ac
steady state +
transient square
wave
SPICE Modeling the 741 Op-Amp
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Fig. 2 Inverting amplifier with 741 op-amp model.
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SPICE Modeling the 741 Op-Amp
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Experiment 2
741 Op-Amp Circuits
Introduction
The purpose of this experiment is to gain experience with the '741 op-amp in severaltypical applications, and to discover some of the basic limitations of all op-amps. The observed
behavior of the inverting amplifier will be compared with the simulated behavior from
Experiment 1.
Pre-Lab
It is expected that Experiment 1, "SPICE Modeling the '741 Op-Amp," has already been
performed.
Equipment Needed
vPower supplies, function
generator, oscilloscope
vLM741/MC741/SN741 op-amp
(prefix indicates manufacturer)
Procedure
1. Connect the circuit of Fig. 1. Use a 100-mV peak 1-kHz sine wave input voltage to
measure the system voltage gain . (The expected result is -10.) To reduce theAv =vovi
high-frequency noise on the scope channel handling the 100-mV signal, turn on its
bandwidth limit, found on the channel input menu.
2. Measure the high-frequency cutoff (fH) of Fig. 1 using a 100-mV sine wave input and
monitoring the output voltage. Starting at 1 kHz, increase the frequency of until thev ioutput has decreased to 70.7% of its 1-kHz value. Record this -3 dB frequency as fH.v o(The expected value of fHis about 90 kHz.)
3. Collect two output voltage waveforms from Fig. 1 and display them simultaneously using
the memory capability of the DSO. Focus on the rising edge of the square wave
response. Display and record:
a) The response to a 50-mV peak 1-kHz square wave. Measure the slope of the rising
edge of the response using a horizontal scale of 0.5 s/div, and a vertical scale of0.2 V/div.
b) The response to a 500-mV peak 1-kHz square wave. Measure the slope of the rising
edge of the response using a horizontal scale of 5 s/div, and a vertical scale of 2 V/div.
4. Measure the slew rate (SR) capability of the '741 op-amp from the recorded response of
(b) above. (The expected value of SR is about 0.5 V/s.) Try increasing the amplitude
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of the input square wave. Can the output voltage attain a rate-of-change any greater than
your measured slew rate?
5. Connect Fig. 2. Measure the voltage gain of Fig. 2 using a low amplitude 1-kHz sine
wave. (The expected result is +11.)
6. Connect Fig. 3 and display the input and output voltage waveforms together, using a
0.5-V peak 1-kHz square wave for . Does the output appear to satisfy the followingv itransfer function?
vo = 1RiCf
0
tvi(t) dt+ vo(0)
7. Record this square wave input with its triangle wave response. Record the input/response
pair for a 1-kHz sine wave.
Report
1. Compare the 1-kHz voltage gains measured for Figs. 1 and 2 with those predicted by
ideal op-amp equations.
2. Compare the high-frequency cutoff measured for Fig. 1 with that predicted by the SPICE
simulation in Experiment 1. Use the SPICE model for the '741 op-amp to explain why
the circuit gain decreases at frequencies above fH.
3. Compare the slew rate measured for Fig. 1 with that predicted by the SPICE simulation
in Experiment 1. Does increasing the input voltage amplitude beyond 1 V increase the
slew rate observed at the output? Why?
4. Do the integrator responses observed in steps 6 and 7 agree with the equation given for
an ideal op-amp? Compare the shapes and amplitudes of the predicted and observed
responses to square wave and sine wave inputs.
741 Op-Amp Circuits
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741 Op-Amp Circuits
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Fig. 2 Non-inverting amplifier.
Fig. 3 Integrator.
Fig. 1 Inverting amplifier, 8-pin dual-in-line plastic package (top view).
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741 Op-Amp Circuits
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Experiment 3
SPICE Simulation of a JFET Common-Source Amplifier
Introduction
The purpose of this experiment is to gain practical experience with the mechanics of the
SPICE simulations for bias point and ac analysis. The circuit used is a JFET common-source
amplifier.
Pre-Lab
There is no pre-lab for this experiment.
Equipment Needed
vCurrent version of PSpice
Procedure
Turn on the PC and open the current version of PSpice. Enter the circuit of Fig. 1 using
the library model for the 2N5457 JFET. The signal source Vin should be an ac source, set to an
amplitude of 1 V, and with its dc component set to 0 V.
1. Set up the simulation for a detailed bias point solution, a dc sweep, and an ac sweep. The
bias point solution will consist of a detailed listing of the operating-point solution in the
output file, along with calculated incremental model parameters for the JFET. Set the dc
sweep to step the dc value of source Vinfrom -5 V to +5 V in 0.1-V steps. Set the ac
sweep to step the frequency of the ac content of Vinfrom 1 Hz to 100 kHz in 101 steps
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Fig. 1 JFET common-source amplifier.
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per decade.
2. After running the simulation, examine the output file to find the bias point solution. The
JFET drain-source voltage (VDS) must be more than 2 V, and the drain current (ID) must
be more than 0.1 mA. If the bias point does notrepresent a reasonable operating point
for an amplifier, there is no point in proceeding further - something has gone wrong inthe entry of the schematic, or the design of the circuit. Note: Later versions of SPICE
allow you to enable direct display of the bias point solution on the schematic diagram.
Record IDand VDS.
3. Use probe to display the dc sweep results. Plot the output voltage Vo vs.the input
voltage Vin. Use the add trace menu to add a plot of the derivative of Vo [the syntax is
D(V(Vo))]. Record these traces.
4. Use probe to display the ac sweep results. Plot the dB equivalent of the output voltage
Vo vs.frequency. (Vin should be 0 dB at all frequencies.) Record this trace.
Report
No formal report is required for this experiment. Simply summarize the results you have
obtained in a homework format. Briefly answer the following questions:
1. Discuss the location of the optimum Q-point for this amplifier using the plot of Vo vs.
Vin obtained from the dc sweep. Use the plot of the derivative of Vo to estimate the gain
at this Q-point. At what values of Vo (upper and lower) will the amplifier saturate?
2. Discuss the voltage gain of the amplifier as measured at various frequencies. Why does
the voltage gain vary with frequency?
3. For what range of frequencies does the voltage gain read from the ac sweep agree with
the incremental voltage gain read from the dc sweep? Why?
Notes on SPICE
SPICE computes the bias point analysis by setting all ac and transient components of all
sources to zero, and considering only the dc components of these sources. The dc sweep is
computed by stepping the dc component of the source specified in the dc sweep setup statement.
During dc analyses, capacitors are open circuits; and inductors are short circuits.
When SPICE does an ac sweep, it first uses the dc source values to compute the dc bias
point solution. It then computes incrementalmodels for all devices in the circuit based upon the
bias point. After this, SPICE applies an ac steady-state analysis to the incremental equivalent
circuit over the frequency range given in the setup. The ac amplitude of the source Vin can be
set to any convenient valuewithout causing amplifier saturation because the incremental model
is always a linear model.
SPICE Simulation of a JFET Common-Source Amplifier
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Experiment 4
JFET Common-Source Amplifier
Introduction
The purpose of this experiment is to investigate the performance of a JFETcommon-source amplifier.
Equipment Needed
vFor alternate VPand IDSS, you
may substitute 2N5458/59
v2N5457 n-channel JFETvNormal laboratory equipment
Pre-Lab
Estimated typical values of the JFET parameters are: VP = -2.5 V and IDSS = 3 mA.
Obtain a 2N5457 data sheet and find out what the allowable ranges of these parameters are.Read the text file of the 2N5457 SPICE model currently used in this department and determine
what values the model assumes for these parameters.
Procedure
1. Obtain the FET drain characteristics using the curve tracer. Measure the pinchoff voltage
VPand the zero-bias drain current IDSS. Make sure these lie within the ranges promised
on the 2N5457 data sheet. Record the measured values of these two parameters, but you
do not need to record the drain characteristics.
2. Connect the circuit of Fig. 1 without C1 and measure its quiescent operating point (IDQand VGSQ).
3. Set the function generator for a 5-kHz sine wave with zero dc offset. Increase the FG
voltage level until the output voltage is on the verge of clipping-type distortion.VoRecord the output waveform, showing evidence of the voltage levels at which clipping
will occur.
4. Reduce the signal level to assure an undistorted output. Measure and record the voltage
gain at 5 kHz. Place C1 into the circuit and record its effect on the voltageAv =VoVi
gain.
5. With C1 in the circuit, measure and record the amplitude and phase of the output voltage
(relative to the input voltage) at the following frequencies: 5 kHz, 500 Hz, 50 Hz.
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Report
1. Use the measured values of VPand IDSSto predict the Q-point (IDQand VGSQ). Compare
these values with the experimentally-measured values. Compare these values with the
prediction of a SPICE bias point solution using the 2N5457 model.
2. Use the measured values of VPand IDSSto estimate the transconductance (gm). Calculate
the midband voltage gain (the 5-kHz gain) with and without C1, and compare with the
experimentally-measured values. Also, compare the measured 5-kHz gain with the result
of a SPICE ac analysis.
3. Estimate the maximum possible output voltage before the onset of severe distortion.
Consider clipping due to the drain current going to zero, and distortion due to the JFET
entering its ohmic region of operation. Compare these estimates with your observed data.
4. Comment on the observed frequency response data. What happens to the signal as its
frequency is lowered below midband? Why? Compare these experimental results withthe results of a SPICE ac frequency sweep.
Background
Refer to your electronics text for background on modeling the JFET. For the purpose of
this experiment, it is OK to ignore channel-length modulation in modeling the JFET. Be aware
that various electronics books may present the following equations using different symbols.
iD
= IDSS
1 vGS
VP
2
and
gm =iDvGS Q point
=
2IDSSVP
1 VGSVP
=2VP
IDSS $ID
where
IDSS= zero-gate-voltage drain current, and
VP= pinchoff voltage.
The equations above are valid onlyin the constant-current (saturation, or pinch-off) region.
JFET Common-Source Amplifier
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JFET Common-Source Amplifier
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Fig. 1 JFET common-source amplifier.
Fig. 2 2N5457 case and pin-outs.
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JFET Common-Source Amplifier
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Experiment 5
Small-Signal CC and CB Amplifiers
Introduction
The purpose of this experiment is the measurement of the small-signal voltage gain, inputresistance, and output resistance of a common-collector (emitter follower) and a common-base
amplifier. These two circuits are then compared to each other.
Equipment Needed
vPN2222A npn transistorvNormal laboratory equipment
Procedure
Connect the circuit of Fig. 1 and measure its quiescent operating point (ICQand VCEQ).
Connect a 5-kHz sine wave signal source to the input terminals, and a 100-load resistor to the
output. Measure the following small-signal amplifier parameters using a signal level low enough
to avoid clipping, yet high enough to be measurable.
1. Measure the voltage gain .Av = VoVi
2. Measure the input resistance .Ri
3. Measure the output resistance .Ro
Connect the circuit of Fig. 2 and measure its quiescent operating point (ICQand VCEQ).Connect a 5-kHz sine wave signal source to the input terminals, and a 10-kload resistor to the
output. Measure the same small-signal amplifier parameters as previously. Remember to keep
the signal level small enough to avoid any visible distortion of the sinusoidal waveforms.
1. Measure the voltage gain .Av = VoVi
2. Measure the input resistance .Ri
3. Measure the output resistance .Ro
Use the curve tracer to measure the incremental current gain (ac= hfe) of your transistor
in the neighborhood of IC = 1 mA, VCE = 10 V.
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Report
1. Using reasonable approximations, predict the Q-point of Figs. 1 and 2, assuming that
dc = 150. Compare this with the experimentally measured Q-point.
2. Using the values of ac(hfe) and Q-point which were measured experimentally, predict the
following: , , , , and for Figs. 1 and 2.Av Ri Ri
Ro Ro
3. Compare these calculated values with the experimentally-determined values. Compare
the relative values of , , and for Figs. 1 and 2. Based on simplified formulas,Av Ri Rogive the most important factor(s) which determine , , and for Figs. 1 and 2.Av Ri Ro
Small-Signal CC and CB Amplifiers
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Small-Signal CC and CB Amplifiers
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Fig. 2. Common-base amplifier.
Fig. 1 Common-collector (emitter follower) amplifier.
Fig. 3 PN2222A package
and pin-out.
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Appendix: The Experimental Determination of Voltage Gains and Incremental Resistances
1. Voltage gain is measured with a specified load resistor in place by monitoring andVi Vowith a two-channel scope. The smallest measurable level is used; the measurement is
only valid if no appreciable distortion occurs in either or .Vi Vo
2. Input resistance can be measured by monitoring while driving the amplifier from aRi
Vo
source having a known source resistance (RS). Then, using a variable resistor in series
with the source, the source resistance is increased until drops to one-half its previousVovalue. We have:
3. (first measurement), and (1)Vo1 = AvVsRi
Ri+Rs
(second measurement) (2)Vo2 = AvVsRi
Ri+Rs+Rpot
4. Therefore:
(3)Vo1Vo2
= 12 = Ri
+Rs
Ri+Rs+Rpot
(4)Ri
= RpotRs
5. The input resistance is calculated from the measured value of the variable resistorRi
( ) and the value of the source resistance ( ). For the FG in the electronics lab,Rpot Rs. This measurement is only valid for small (undistorted) signals. is easilyRs = 50 Ri
calculated from .Ri
6. Output resistance is measured by monitoring while driving the amplifier with aRo
Vosignal source having the specified source resistance ; is first measured, and then aRs Vovariable resistor is paralleled with the output terminals and adjusted so that is one-halfVoits previous value. The resistance of the potentiometer is then equal to the output
resistance . This measurement is only valid for small signals. is easily calculatedRo
Ro
from .Ro
Small-Signal CC and CB Amplifiers
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Experiment 6
Bypass and Coupling Capacitor Effects
Introduction
The purpose of this experiment is the measurement of the low-frequency response of anac-coupled amplifier.
Equipment Needed
vSwitchable 0-dB/40-dB 50-
attenuator
vPN2222A npn transistorvNormal laboratory equipment
Pre-Lab
Calculate the expected locations of the poles and zeros contributed by each capacitor in
Fig. 1 (they each act independently). Calculate the midband gain, and sketch a Bode plot of theexpected magnitude of the voltage gain from 1 Hz to 10 kHz.
Procedure
Gain will be measured over a wide range of values in this experiment: The amplitude of
the input signal may need to be changed in order to maintain a measurable output level, but at all
times keep the levels low enough to avoid appreciable distortion, yet high enough to be
measurable. You will need to use a switchable 0-dB/40-dB 50-attenuator at the FG output to
do this. Turn on the bandwidth limiters in both channels of the scope to reduce any
high-frequency noise present in low-level signals.
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Fig. 1 Common-emitter amplifier with blocking and bypass capacitors.
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1. Connect the circuit of Fig. 1 and measure its operating point (ICand VCE). Note that the
function generator (FG) must be connected to provide a dc path for the base current.
Make sure that the operating point is reasonable for operation as an amplifier.
2. Set the FG to produce a 7-mV rms 10-kHz sine wave at Vi and measure the midband
gain at 10 kHz. (Expected value is about +40 dB.) Make sure that both scope channelsare dc-coupled throughout this procedure. An ac-coupled scope channel is itself a
high-pass filter.
3. Measure the gain magnitude (in dB) over the frequency range of 10 Hz to 10 kHz. Mark
the data points on your predicted frequency response plot. If there is a deviation of more
than 6 dB, you should investigate the reason for the discrepancy. Use the 2-channel
scope to measure the peak-to-peak values of Viand Vofor the purpose of measuring gain.
Details Lower the frequency by steps in a 10-4-2-1 sequence (e.g., 1 kHz - 400 Hz -
200 Hz - 100 Hz), taking gain magnitude measurements at each step. You may need toincrease the input signal level at lower frequencies to maintain a measurable output
signal. Take data from 10 kHz down to 100 Hz. Continue going down in frequency
towards 10 Hz as far as meaningful data can be obtained. Use "averaging1" (found in the
scope Display menu) to reduce the amount of noise on small signals.
4. Divide the midband gain measured in part 1 by 1.414 (this is equivalent to subtracting
3 dB from its decibel value). Use the FG to experimentally measure the frequency at
which the amplifier's gain is 3 dB below its midband value. This is called the
"low-frequency cutoff."
Report
1. Bode plot the pre-lab calculated frequency response on 4-cycle semi-log paper. Use dB
notation, and use a frequency range of 1 Hz to 10 kHz.
2. Mark the experimental data points on this graph. Do they agree well with the predicted
values?
3. Identify the midband gain from the experimental data, and from the calculated response.How do they compare?
4. Identify the low-frequency cutoff (fL) from the experimental data, and from the calculated
response. How do they compare?
Bypass and Coupling Capacitor Effects
20
1 "Averaging" is the process of storing repeated acquisitions of the waveform, each one based on the trigger
event, and point-by-point averaging these stored waveforms to produce the display. Averaging only works if there
is a stable trigger event.
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Bode Plots
The actual gain vs.frequency plot of an ac-coupled amplifier is a smooth curve.
However, Bode pointed out that if semi-log paper is used, a series of straight-line asymptotic
approximations to the gain curve will be close enough for many engineering purposes. The gain
magnitude in dB is placed on the linear scale; the frequency is placed on the log scale. Fig. 2below shows sample Bode plots of the contribution of the emitter bypass C1 acting alone (upper
figure), and the collector blocking capacitor C2 acting alone (lower figure).
Bypass and Coupling Capacitor Effects
21
Fig. 2 Bode plot of frequency response of C1 alone (upper figure); and C2 alone (lower figure)
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Bypass and Coupling Capacitor Effects
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Experiment 7
BJT High-Frequency Performance
Introduction
The purpose of this experiment is the investigation of the high-frequency performance ofa BJT common-emitter amplifier. The transistor junction capacitances Cand Cwill be
estimated from typical data sheet information.
Equipment Needed
vPN2222A npn transistorvNormal laboratory equipment
Pre-Lab
Study the appendix to this lab which shows how to estimate the transistor junction
capacitances on the basis of the limited information typically given on a data sheet.
Procedure
The circuit of Fig. 1 may not maintain a stable dc operating point; therefore, you should
verify at several stages during the experiment that the operating point is still 5 mA/5 V (I C/VCE).
The collector current is controlled by adjusting VBB, and the collector-emitter voltage is then set
by adjusting VCC. Be sure to remove the dc voltmeter or milliameter from the circuit when
making the actual gain measurements. Gain will be measured from midband (5 kHz) to beyond
the high-frequency cutoff fH(1 MHz).
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Fig. 1 Common-emitter amplifier.
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1. Connect Fig. 1 using a 1 K load resistor (RL). Set the dc operating point and remove all
dc meters from the circuit. Measure the midband gain factor at 5 kHz using a smallVoVi
signal. Measure the transistor base-emitter resistance at 5 kHz by measuring the ac
signal at each end of R1.
2. Take gain measurements from 5 kHz to 1 MHz. The objective is to accurately determine
the high-frequency cutoff (fH). Take enough data points to be sure of the value of the
midband gain, and the frequency at which the gain is reduced to 70.7% of its midband
value. (Expected midband gain and hf cutoff are about -100 and 400 kHz.)
3. Change the load resistor (RL) to 560 . Readjust the dc operating point to maintain
5 mA/5 V. Measure the midband gain and the high-frequency cutoff again. (The
expected values are now 56% and 179% of the previous measurements, respectively.)
Report
1. Obtain a copy of the transistor data sheet for type 2N2222A or PN2222A, and put it in an
appendix to your report. Use the data sheet to estimate values for Cand C.
2. Calculate the midband gain and high-frequency cutoff for each of the two values of load
resistance used. Compare these results with the experimental data.
3. Use SPICE to simulate the frequency response of the experimental circuit. Compare the
midband gain and high-frequency cutoff predicted by SPICE with your calculated and
observed data. After running your simulation successfully, open the *.OUT file and read
the values for Cand Cthat were produced by SPICE. Compare these with your
estimated values.
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Appendix A - Estimating Cand CFrom a Data Sheet
The capacitance associated with a pn junction has two components: the transition
capacitance, which is a nonlinear function of the junction voltage; and the diffusion capacitance,
which is directly proportional to the junction forward current.
In the active mode, the collector-base junction is reverse-biased, and therefore it has only
transition capacitance, whose value is determined by the dc collector-base voltage. This
capacitance is denoted Cbc, C, Cobor "output capacitance" on most data sheets. A complete
data sheet will typically contain a graph of C vs.collector-base reverse voltage. An abbreviated
data sheet will at least give a single value for C. Note that the transition capacitance increases
with decreasing reverse-bias, reaching its maximum value at zero bias.
In the active mode, the emitter-base capacitance is composed of both transition and
diffusion components. The transition component is generally small and independent of operating
point (VBEis almost constant at 0.7 V); the diffusion component is generally large and directly
proportional to emitter current. The foregoing is true when the transistor is used at normalcurrent densities: In a large transistor used at low current, C will not be zero; it will approach a
lower limit equal to its transition capacitance. The transition component of C can be estimated
from the data sheet as the zero-voltage limiting value of the reverse-biased emitter-base
capacitance. The diffusion component of C is directly proportional to IE, and is never directly
given on the data sheet.
The short-circuit unity-current-gain frequency (denoted fTand frequently called the
current gain-bandwidth product, or GBW) is normally found on the data sheet. It can be shown
that this is related to the junction capacitances by:
2fT = gmC + C
If the proposed operating point current (IE) is within one decade of the operating point used in
making the data sheet measurement, it may be assumed that fTdoes not change and the
computation of Cis straightforward. If the proposed IEis small, model C by the following:
C = X0 + X1 $ IE
X0is the zero-bias limiting value of the transition capacitance, and X1is readily calculated from
the given GBW data together with the operating point used to measure it. This equation is then
used to estimate C at the proposed operating point.
As an example, capacitances are estimated from the data sheet for a National
Semiconductor PN2222A. A graph labeled "Emitter Transition and Output Capacitance vs.
Reverse Bias Voltages" directly states that Cis typically 4.5 pF at VCB= 4.3 V. From the same
graph, X0= 21 pF. Under the small-signal characteristics, it is stated that fTis at least 300 MHz
at IC= 20 mA. From this data, X1= 20 pF/mA. Therefore, Cis expected to be 121 pF at 5 mA.
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An alternative calculation, which simply assumes that fTis the same at 5 mA as at 20 mA,
produces C= 102 pF. Either is justifiable given the precision of the available data.
Appendix B - SPICE Simulation of the CE Amplifier
The CE amplifier of Fig. 1 can be easily entered into SPICE and simulated using a
2N2222A transistor model. The problem that will immediately arise is that the dc operating
point in the simulation will not be the same as that in the lab. The gain and bandwidth results are
strongly operating-point dependent, and therefore will not match the lab results at all. The newer
versions of PSpice allow the direct display of the calculated operating point on the schematic:
Enable this option and verify that the correct operating point has been achieved before looking at
the frequency response data in probe.
With the direct display of the bias point solution, it is not difficult to iteratively adjust
VBBto obtain IC= 5 mA, and then adjust VCCto obtain VCE= 5 V. This process is speeded if all
other analyses except for bias point are disabled during this iterative procedure.
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Experiment 8
Differential Amplifiers
Introduction
The purpose of this experiment is to investigate several key features of the balanceddifferential pair and the wide band (asymmetrical) differential pair.
Equipment Needed
vScope probe having known input
capacitance
vtwo PN2222A npn transistorsvNormal laboratory equipment
Pre-Lab
Assuming that the transistors will have a dc current gain ( or hFE) equal to 100, predict
the Q-points of Figs. 1 and 2. Estimate the differential gain (Ad) and the common-mode gain(Acm) for Fig. 1. In each case, the output is taken at Q2's collector.
Procedure
1. Connect the circuit of Fig. 1 and verify that a reasonable Q-point is obtained. Remember
that the amplifier is not properly biased unless a dc current path is provided from each
transistor base to the ground. Substitute transistors until the collector currents of Q1 and
Q2 match to within 10 A of each other. Use the curve tracer to measure the ac current
gain (Oor hfe) in the vicinity of the Q-point for each transistor.
2. Use the signal connections shown in solid lines in Fig. 1 to measure the differential-mode
gain ( ) of the symmetric differential pair. Note that the output is takenAd = Vo
Vs
single-endedly (from one collector only). This is a midband, small-signal measurement;
use 400 Hz and a signal level low enough that there is no appreciable distortion in the
output sine wave. Use an attenuator as needed to reduce the output of the function
generator (FG). (The expected value is about 85.)
3. Measure the high-frequency cutoff fHof the symmetrical differential amplifier of Fig. 1.
Note that the input capacitance of the scope probe1is a part of the high-frequency model
of the circuit. (The expected value is about 27 kHz.)
4. Use the signal connections shown in broken lines in Fig. 1 to measure the common-mode
gain ( ) of the symmetric differential pair. Use 400 Hz and a low signal levelAcm = Vo
Vcm
so that there is no appreciable distortion in the input or output waveforms. (The expected
value is about -0.3.)
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1 For the HP 10071A probe, the input capacitance is 16 pF.
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5. Connect the asymmetric differential pair of Fig. 2 and verify that a reasonable Q-point is
obtained. (VCBfor Q2 should be between 10 and 18 V.)
6. Measure the gain ( ) and the high-frequency cutoff of the asymmetricAd = Vo
Vs
differential pair of Fig. 2. Note that the input capacitance of the scope probe is also an
important part of the high-frequency model of this circuit. (The expected values areabout 85 and 80 kHz, respectively.)
Report
1. From the transistor data sheet, estimate the values of collector-base and emitter-base
capacitance at the Q-point. Hint: at the current level used here, Cwill be dominated by
its transition component.
2. Calculate the theoretical values of Ad, Acmand fHfor Figs. 1 and 2, and compare with the
experimental results. (For Fig. 1, use Miller's Theorem and model the symmetricaldifferential amplifier as equivalent to a common-emitter stage.)
3. Use SPICE (with a 2N2222A model) to simulate this circuit, and compare these results
with the experimental and calculated results.
4. Compare the gains and cutoff frequencies of Figs. 1 and 2. Compute a gain-bandwidth
product for each.
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Differential Amplifiers
29
Fig. 1 Symmetrical differential pair. The load capacitance is the scope probe capacitance.
Fig. 2 Asymmetrical differential pair. The load capacitance is the scope probe capacitance.
Fig. 3 PN2222Apackage and pin-out.
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Experiment 9
Complementary-Symmetry Push-Pull Amplifier
Introduction
The purpose of this experiment is to observe the operation of a class-Bcomplementary-symmetry amplifier and the use of negative feedback to improve its behavior.
Equipment Needed
vLoad resistor (about 12 ,5 W)vComplementary-symmetry
output stage circuit board
vNormal laboratory equipment
Procedure
Connect the circuit of Fig. 1 using a complementary-symmetry output stage circuit board.Fig. 3 gives a top view (component side) of this circuit board to identify the correct connection
points. Note that both Figs. 1 and 2 show only a simplified equivalent of the circuit board
schematic: The details of the circuit board are shown in Fig. 3. In making connections, bring
all ground leads separately back to the "COM" binding post on the circuit board (including the
function generator and scope ground leads). This is known as a "star" grounding arrangement.
1. Use the function generator (FG) to apply a 10-V peak 100-Hz triangle wave as shown in
Fig. 1. Connect the two scope channels as indicated. Display and record the input
(Chan. 1) and output (Chan. 2) waveforms. Note carefully the defect in the output
waveform around its zero crossings. This is known as "crossover" distortion.
2. Display and record an X-Y plot of output vs.input on the scope. (Look on the horizontal
"Main/Delayed" menu.) Be sure that both channels are set for zero offset and 2 V/div
before switching to the X-Y mode. This is the transfer function of the basic
complementary-symmetry output stage.
3. Obtain a type '741 op-amp and connect Fig. 2, placing the op-amp on a proto-board. It is
best to run separate jumper wires from each op-amp terminal to the corresponding
terminals on the output stage circuit board. Make all power supply connections (+15 V,
-15 V and COM) to the circuit board, not to the proto-board. Set the FG for 10 V peak at
100 Hz as before.
4. Display and record the input from the FG (Chan. 1) and the output (Chan. 2) waveforms.
Note the suppression of the crossover distortion by the negative feedback.
5. Display and record an X-Y plot of output vs.input as before. Use identical vertical
settings of 2 V/div and zero offset on both channels.
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6. Investigate how the negative feedback functions to suppress the crossover distortion.
Move the scope channel 1 to the two transistor bases (B1 and B2) on the circuit board.
Switch the scope back to voltage vs.time. Display and record the input and output of the
complementary-symmetry stage itself. Note the inverse crossover distortion at the input
to the complementary-symmetry stage.
7. Maintain these two waveforms on the scope while increasing the FG frequency to
10 kHz. Note the decreasing ability of the feedback to cancel the crossover distortion at
high frequency. Record these waveforms.
Report
1. Explain the cause of the crossover distortion observed in steps 1 and 2. (Most electronics
texts have a good discussion of this problem in a chapter on "power amplifiers" or
"output stages.")
2. Analyze the circuit in Fig. 2 based upon the assumption of an idealop-amp. (Assumethat the voltages on pins 2 and 3 of the '741 must be exactly equal because of its infinite
gain.) How does this suppress the distortion? Use the waveforms gathered in steps 4 and
5 to support your discussion.
3. Why is the distortion reduction in step 7 (at 10 kHz) not so good as it was at 100 Hz?
Explain this in terms of a specific imperfection in all practical op-amps, as opposed to an
ideal op-amp.
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Complementary-Symmetry Push-Pull Amplifier
33
Fig. 1 Simplified diagram of the complementary-symmetry output stage.
Fig. 2 Complementary-symmetry amplifier with negative feedback.
Fig. 3 Pictorial top view and detailed schematic of the complementary-symmetry output stage.
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Complementary-Symmetry Push-Pull Amplifier
34
Fig. 4 '741 pinout, top view.
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Experiment 10
Negative Feedback
Introduction
The purpose of this experiment is to investigate the effects of shunt-shunt negativefeedback on the gain, input resistance and output resistance of a transresistance amplifier.
Equipment Needed
vPN2222A npn transistorvNormal laboratory equipment
Procedure
Connect the circuit of Fig. 1. Verify that the Q-point is approximately 1 mA. All ac
measurements will be at midband (5 kHz) and small signal (no appreciable distortion).
1. Measure the closed-loop voltage gain .Av = Vo
Vs
2. Measure the input resistance indicated on Fig. 1, . This may be done by measuringRif
the ac voltages VSand VSJusing the scope. Verify that these two voltages are in-phase.
Compute the current in RS, and then find . (The expected value is aboutRif
= VSJIRS
60 .)
3. Measure the output resistance indicated on Fig. 1, . Fig. 2 shows how to do this:Rof
Remove the function generator (FG), but keep its source resistance RSin place as
indicated. Connect the FG at the output terminal with a 100-K series resistor (R5). Set
the FG for a 10-V peak 5-kHz sine wave output and measure voltages V1and V2.
Compute the current in R5, and then find . (The expected value is aboutRof
= V1IR5
370 .)
4. Connect the circuit of Fig. 3. This is the amplifier with the feedback removed, but the
loading effects of the feedback resistor Rfretained. Verify that the Q-point is the same as
previously, approximately 1 mA.
5. Measure the voltage gain , input resistance , and output resistance usingAv = Vo
Vs Ri Ro
the same techniques as previously. (The expected values are -150, 3.2 Kand, 5 K
respectively.)
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Report
1. Use feedback theory to calculate the gain , input resistance , and outputAv = Vo
Vs Ri
resistance for Fig. 1. Be sure to note that the gain factor is notthe one directlyRo A vstabilized by the feedback or given by the equation .
A
1+A
2. Use SPICE simulation to predict the gain and input/output resistances of Fig. 1.
3. Compare the results predicted by SPICE and by calculation to your experimental data.
Background - Measuring Input/Output Resistances in a Feedback System
There are two general cautions to observe in analyzing a feedback system: The quantity
which you are computing may not be the same as the one actually stabilized by the feedback; and
everything (all gains and resistances) pertaining to the feedback amplifier is affected by the loopgain. The first caution applies to this lab in that the voltage gain of Fig. 1 is notdirectly
stabilized by the feedback. Fig. 1 is a transresistance amplifier: Its current-to-voltage
conversion factor is stabilized by the feedback. The best way to calculate the voltage gain of
Fig. 1 is to compute the transresistance first, and then convert it into the voltage gain.
The second caution affects the resistance measuring procedure used in this lab. The
"ohmmeter" applied to the circuit must not alter the loop gain of the amplifier. (This caution
must also be remembered in devising a SPICE-based procedure for determining the input and
output resistances as well.) When measuring the input resistance , the source resistance RSRiprovides a convenient way of measuring the input current; however, changing the value of RS
from that given will alter the measured value of because it would alter the loop gain. TheRifunction generator (FG) is connected in series with a 1-Kresistor which is considered the
source resistance. It is reasonably accurate to neglect the internal 50 resistance of the FG.
Similarly, the measuring apparatus in Fig. 2 (the FG with R5) alters the loop gain, and
thus produces an erroneous value of . In this case, R5 is chosen to be much greater than theRo
open loopvalue of the output resistance so that it will only change the open loop gain by a small
amount and produce a reasonably accurate measurement.
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Negative Feedback
37
Fig. 1 Amplifier with shunt-shunt feedback.
Fig. 2 Measuring the output resistance.
Fig. 3 Amplifier with feedback removed, but loading effects retained.
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Experiment 11
Voltage Regulators
Introduction
The purpose of this experiment is to investigate the performance characteristics of twosimple voltage regulators.
Equipment Needed
vResistor decade box
v1N754 6.8-V Zener diode
(alternates: 1N4736 or 1N5235)
vMJE 371 pnp power transistorvNormal laboratory equipment
Pre-Lab
Complete the design of the Zener diode shunt regulator in Fig. 1 (determine the largest
5% standard value which can be used for R1). It must operate satisfactorily over a load current
range of 0 to 10 mA using a supply voltage of 12 V. The output voltage is expected to have a
nominal value of 6.8 V.
Procedure
The 12-V supply in the following procedure is a laboratory supply capable of 200 mA of
output current. Be sure to set its current limiter for at least this amount.
1. Set up the circuit of Fig. 1 using the standard value that you calculated for R1 in the
pre-lab. Use a resistor decade box as the "load resistor" RLOAD. Insert a milliammeter as
shown to monitor the load current. Measure the load voltage at light-load (ILOAD= 1 mA),
and at full-load (ILOAD= 10 mA).
2. Measure the output voltage/current pairs with various values of load resistance. Use
output currents ranging from zero to well beyond the point where the regulator "drops out
of regulation." Collect enough data to sketch a map of the regulator performance on the
VLOADvs.ILOADplane (put VLOADon the vertical axis, and ILOADon the horizontal). The
expected result is that the regulator will maintain the output voltage almost-constant with
regard to load current up to the "dropout current:" the output voltage will then fall
rapidly with further increase in load current.
3. Set up the circuit of Fig. 2 and adjust it for an output voltage of 5.0 V at no-load.
Measure the output voltage and current with load resistors of 500 and 50 .
4. Operate the voltage regulator for several minutes with a 50-load and feel Q2. (Is it
getting warm?)
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Report
1. Include and discuss your design calculations for the Zener diode voltage regulator of
Fig. 1.
2. Describe the range of output current over which Fig. 1 operates satisfactorily. Why doesit "drop out of regulation?"
3. Find the experimentally-measured dynamic output resistance of each regulator in the
following manner:
ROUT = VLOAD
ILOAD=
VLOAD,1 VLOAD,2
ILOAD,1 ILOAD,2
4. Use PSpice to estimate the output resistance of Figs. 1 and 2. Use ac simulation and
measure the resistance at midband (about 1 kHz). Include a 680-load resistor in Fig. 1,
and a 50 load resistor in Fig. 2. Model Z1 using a 1N750-series Zener diode, but editthe breakdown voltage parameter to: (BV=6.8V). Model Q2 with a transistor having its
SPICE parameters set to: (IS=1E-14 BF=100 VAF=50V). Compare the SPICE results
with the experimentally-measured output resistances.
5. Use PSpice to determine the range of output current over which Fig. 2 operates
satisfactorily. Put a dc current source in place of the load resistor, and use a dc sweep to
plot the load voltage vs.the load current. (Truncate any data beyond the point at which
the load voltage is reduced to zero.) What is the maximum useful load current according
to this simulation? Calculate the power dissipation in Q2, and its junction temperature
for this amount of load current.
Background - Zener Shunt Regulator
The Zener diode shunt regulator is treated in detail by most electronics texts. For the
purposes of the pre lab design, it is sufficient to treat the diode as an ideal 6.8-V Zener. The
design problem is to pick R1 such that some amount of reverse current will flow in the Zener
diode under all normal load conditions. Here, worst case is at maximum load current. A
calculation at maximum load current produces the maximum feasible value for R1, which then
must be rounded downwardto the nearest available standard value. The student version of
PSpice includes a 1N750-series Zener diode model - if it is not the one you need, modify thelibrary model to include "BV = 6.8." (This sets the reverse breakdown voltage of the diode.)
Background - Series-Pass Voltage Regulator
The voltage regulator in Fig. 2 is an application of series-shunt negative feedback.
Resistors R5 and R4, together with Z1, form an adjustable "input voltage" to a voltage amplifier
programmed for a gain of +1. The load is the external circuitry to which the voltage regulator is
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Voltage Regulators
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Fig. 1 Zener diode shunt regulator. Calculate the maximum
standard value which can be used for R1.
Fig. 2 Adjustable voltage regulator.
Fig. 3 Transistor package outlines.
MJE 371
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feeding power. (Nowadays, almost all electronic circuitry is fed from a voltage-regulated power
supply.) Note that the +12-V supply is the energy source which runs the whole system; it is not
usually a regulated source. One of the key specifications of a voltage regulator is its dynamic
output resistance, which indicates its ability to maintain a constant output voltage even as the
load current varies. This can be predicted theoretically by the same methods used to calculate
the output resistance of any shunt-sensing feedback amplifier.
Transistor Q2 is called a "series-pass transistor." This is because the main load current is
carried by Q2; the collector-emitter voltage drop on Q2 is equal to the difference between the
supply voltage (+12 V) and the load voltage. In general, Q2 dissipates a lot of heat, and thus
gets hot. The junction temperature of Q2 may be estimated by using a simplified heat-flow
model which makes the temperature drop between two locations directly proportional to the
amount of heat flowing from one to the other. (Note the analogy to Ohm's law.) For the
MJE 371, which is in a TO 225 package, mounted in free air, the "thermal resistance" between
the junction and the ambient air is approximately 83 C/W. The maximum safe junction
temperature for the long-term survival of this semiconductor is rated by the manufacturer at
150 C. The heat dissipated in the junction is calculated by (watts).PDISS = VCE $ ICTherefore, assuming a laboratory ambient temperature of 25 C, the junction temperature is
estimated by: . The junction temperature of Q2 defines theTJ = PDISS $ (83C/W) + 25Cmaximum load current that this regulator can safely deliver.
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Experiment 12
Wien Bridge Oscillator
Introduction
The Wien bridge oscillator will be used to demonstrate the effects of positive feedback,
and the Barkhausen criterion for oscillation. Negative feedback is also used to stabilize the
transfer characteristics of the amplifier used by this oscillator.
Equipment Needed
PN2907A pnp transistor
(alternate: 2N4403)
PN2222A npn transistor
(alternate: 2N4401)
Normal laboratory equipment
Pre Lab
Read the appropriate section(s) of your electronics text dealing with the "Barkhausen
criterion" or "quasi-linear sinusoidal" oscillators.
Procedure
1. Construct the amplifier of Fig. 1. Measure its voltage gain at 1 kHz. VerifyVoutVin
that the amplifier is non-inverting, and that trim pot R4 adjusts its voltage gain from
something less than +3 to something more than +3. Use the 100-K series resistor
together with the function generator (FG) to measure the amplifier input resistance
Rin. (The expected value is about 180 K.)
2. Add the frequency-selective feedback network to the amplifier as shown in Fig. 2.
Use the capacitor value given for C on Fig. 2, unless otherwise instructed. Initially,
wire the circuit as indicated by the "TEST" position of the switch. Set the FG for a
sine wave at the frequency and monitor Voutand the FG signal using thefo =1
2RC
two-channel scope. Monitor the phase shift. (Hint: A phase measurement is
available on the DSO "Measure Time" menu.) Vary the FG frequency about untilfoyou find the frequency at which the phase is zero.
3. Remove the FG, and wire Fig. 2 as indicated by the "OSCILLATE" position of the
switch. Adjust trim pot R4 until the circuit breaks into oscillation. Adjust R4 to
produce the minimumamplifier gain which maintains oscillation. Study the effectsof a slight decrease or increase of the amplifier gain about the borderline value
which just barely sustains oscillation. Measure the frequency of oscillation.
4. Do not change the setting on R4. Remove the frequency-selective feedback network,
and measure the amplifier gain as done previously in Fig. 1.VoutVin
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Report
1. Review the Barkhausen criterion for oscillation.
2. Derive the transfer function of Fig. 3, the frequency-selective feedbackVo(s)
Vi(s)
network. Calculate the magnitude and the phase of this function at the frequency
.o =1
2RC
3. Calculate the amplifier gain required for oscillation at . Compare this with yourolaboratory observations.
4. Run a series of several PSpice simulations of the complete oscillator circuit. Use a
transient simulation, and parametrically step the total resistance RE= R3+R4 from
1.2 Kto 1.6 Kin 100-steps. Set the simulation run time at 50 ms with a
maximum step size of 0.1 ms. Do not omit the initial transient solution. Observe the
start-up process for the oscillator, and comment on it in your report.
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Wien Bridge Oscillator
45
Fig.1 Voltage amplifier with series-shunt feedback.
Fig. 2 Completed oscillator circuit using amplifier from above.
Fig. 3 Frequency-selective feedback network.
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Wien Bridge Oscillator
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Experiment 13
Analog/Digital Conversion
Introduction
Most digital signal processing systems are interfaced to the analog world through
analog-to-digital converters (A/D) and digital-to-analog converters (D/A). The purpose of this
experiment is to observe how the conversion process modifies the signal. A circuit board having
separate sample-and-hold (S/H), A/D and D/A sections is provided for this experiment. It allows
easy access to the signals at each stage of these conversion processes.
Equipment Needed
Analog/digital conversion
circuit board
Function generator Digital Scope with event
averaging capability
Pre Lab
Read the appropriate section(s) of your electronics text dealing with A/D and D/A
conversion, as well as S/H circuits.
Procedure
1. Connect the analog/digital conversion circuit board as shown in Fig. 1. Be sure to
observe correct polarity in connecting the +/- 15-V power supplies. The function
generator and oscilloscope ground leads should be connected to "analog ground."
The power supply common lead is connected to "digital ground." Set the FG for a dc
output1voltage of 0 V. Connect the scope channel 1 to the analog input (to the A/D
converter), and channel 2 to the analog output (from the D/A converter).
2. Vary the dc voltage at the analog input slowly from 0 V to 5 V. The eight LEDs
indicate the digital value of the converted analog input voltage. The 8-bit byte
should vary from 00hto FFh. Determine what happens when the analog input
voltage goes below zero, or above 5 V. Using an increment of 1 mV in the analog
voltage, carefully determine the voltage change (to the nearest 1 mV) required to
produce a 1-bit change in the digital output. This is the "quantization step size."
3. Use a dc voltmeter connected between "analog ground" and "VREF" to measure the
internal reference voltage of the A/D and D/A converters. The result should be 5 V,
plus or minus 5%. Divide VREFby (28-1) and compare with the quantization step
size measured in step 2. These two results should be equal.
47
1 To obtain dc output from the HP 33120A, press and hold the buttons for twowaveforms, such
as sine and triangle, simultaneously for several seconds.
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4. Set the FG for a 100-mVpp 50-Hz triangle wave with a 100-mV dc offset2. Connect
channel 1 of the scope to show this analog input waveform, and connect channel 2 to
show the output voltage of the S/H stage, labeled "S/H OUT." Trigger from channel
1. You will need to use event averaging to obtain a low-noise display at 50 mV/div.
Record this display which documents the relationship between the low-frequency
input signal and a sampled version of it.
5. Keep the same setup as the previous step, except move channel 2 to the "analog
output." This output shows the result of digitizing the sampled signal, and then
converting it back to analog form. Record this display which documents the
relationship between the low-frequency input signal and a sampled and quantized
version of it. Use this display to measure the quantization step size.
6. Measure the frequency of the sampling-and-conversion clock signal labeled
"CONV. CLK." This is the sampling frequency.
7. Set the FG for a 5-Vpp 500-Hz sine wave with a 2.5-V dc offset. View the inputsignal on channel 1, and the sampled signal (S/H OUT) on channel 2. Be sure to
trigger the scope from channel 1. View the results both with and without event
averaging (8 averages is fine). The normally-acquired waveforms should clearly
show the effects of the sampling process on the signal. Record two sets off
waveforms, one event-averaged and the other without event averaging.
8. With the event averaging turned off, slowly change the frequency of the sine wave
by +/- 10 Hz using 1-Hz increments. Your scope display should be showing signal
components at 500 Hz, and signal components at the sampling frequency (7 kHz).
These two frequencies could be commensurate (having an integer-ratio relationship),
or incommensurate. As you change the signal frequency slightly, observe whathappens when the two frequencies involved become commensurate. Record your
written comments.
9. Set the scope time base for 1 ms/div, and change the triggering source to channel 2
with HF reject on. Channel 2 is still connected to the analog output. Increase the
frequency of the sine wave input from 0.5 kHz to 22 kHz, going in 0.1 kHz steps.
Observe what happens as you pass through the frequencies fS, 2 fS, and 3 fS. Record
your written comments.
Report
1. Discuss the meaning of "quantization step size." Give its numerical value for this
A/D converter as measured in steps 2 and 3. Label your waveforms recorded in step
Analog/Digital Conversion
48
2 Remember that the actual output voltage amplitude will not agree with the programmed value
unless the output termination is set to "High Z."
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5 to show where the quantization step size can be measured from these results.
2.
3.
Analog/Digital Conversion
49
Fig. 1 Top view of analog/digital conversion experiment circuit board. Observe polarity when
connecting the +/- 15-V power supplies.
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Analog/Digital Conversion
50
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Data Sheets
The following data sheets are included with this lab manual:
Operational Amplifier: GBW=1 MHz, SR=0.5 V/s, Voff
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52
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NPN General Purpose Amplifier
This device is for use as a medium power amplifier andswitch requiring collector currents up to 500 mA. Sourcedfrom Process 19.
Absolute Maximum Ratings* TA= 25C unless otherwise noted
*These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.
NOTES:1)These ratings are based on a maximum junction temperature of 150 degrees C.2)These are steady state limits. The factory should be consulted on applications involving pulsed or low duty cycle operations.
Symbol Parameter Value Units
VCEO Collector-Emitter Voltage 40 V
VCBO Collector-Base Voltage 75 V
VEBO Emitter-Base Voltage 6.0 V
IC Collector Current - Continuous 1.0 A
TJ, Tstg Operating and Storage Junction Temperature Range -55 to +150 C
1998 Fairchild Semiconductor Corporation
Thermal Characteristics TA= 25C unless otherwise noted
Symbol Characteristic Max Units
PN2222A *MMBT2222A **PZT2222A
PD Total Device Dissipation
Derate above 25C
6255.0
3502.8
1,0008.0
mW
mW/C
RJC Thermal Resistance, Junction to Case 83.3 C/W
RJAThermal Resistance, Junction to Ambient 200 357 125
C/W
*Device mounted on FR-4 PCB 1.6" X 1.6" X 0.06."
**Device mounted on FR-4 PCB 36 mm X 18 mm X 1.5 mm; mounting pad for the collector lead min. 6 cm 2.
PN2222A
CB
E
TO-92
MMBT2222A
C
B
E
SOT-23Mark: 1P
PZT2222A
BC
C
SOT-223
E
PN2222A
/M
MBT2222A
/PZT2222A
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Electrical Characteristics TA= 25C unless otherwise noted
Symbol Parameter Test Conditions Min Max Units
OFF CHARACTERISTICS
ON CHARACTERISTICS
SMALL SIGNAL CHARACTERISTICS
fT Current Gain - Bandwidth Product IC= 20 mA, VCE= 20 V, f= 100 MHz 300 MHz
Cobo Output Capacitance VCB= 10 V, IE= 0, f = 100 kHz 8.0 pF
Cibo Input Capacitance VEB= 0.5 V, IC= 0, f = 100 kHz 25 pFrbCC Collector Base Time Constant IC= 20 mA, VCB= 20 V, f= 31.8 MHz 150 pS
NF Noise Figure IC= 100 A, VCE = 10 V,
RS= 1.0 k, f = 1.0 kHz
4.0 dB
Re(hie) Real Part of Common-EmitterHigh Frequency Input Impedance
IC= 20 mA, VCE= 20 V,f = 300 MHz
60
SWITCHING CHARACTERISTICS
*Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%
Spice Model
V(BR)CEO Collector-Emitter Breakdown Voltage* IC= 10 mA, IB = 0 40 V
V(BR)CBO Collector-Base Breakdown Voltage IC= 10 A, IE = 0 75 V
V(BR)EBO Emitter-Base Breakdown Voltage IE= 10 A, IC = 0 6.0 V
ICEX Collector Cutoff Current VCE = 60 V, VEB(OFF) = 3.0 V 10 nA
ICBO Collector Cutoff Current VCB= 60 V, IE = 0VCB = 60 V, IE = 0, TA= 150C
0.0110
A
A
IEBO Emitter Cutoff Current VEB= 3.0 V, IC = 0 10 nA
IBL Base Cutoff Current VCE= 60 V, VEB(OFF) = 3.0 V 20 nA
hFE DC Current Gain IC= 0.1 mA, VCE= 10 V
IC= 1.0 mA, VCE= 10 VIC= 10 mA, VCE= 10 V
IC= 10 mA, VCE= 10 V, TA= -55CIC= 150 mA, VCE= 10 V*IC= 150 mA, VCE= 1.0 V*IC= 500 mA, VCE= 10 V*
35
507535
1005040
300
VCE(sat) Collector-Emitter SaturationVoltage*
IC= 150 mA, IB= 15 mAIC= 500 mA, IB= 50 mA
0.31.0
VV
VBE(sat) Base-Emitter Saturation Voltage* IC= 150 mA, IB= 15 mAIC= 500 mA, IB= 50 mA
0.6 1.22.0
VV
td Delay Time VCC= 30 V, VBE(OFF)= 0.5 V, 10 ns
tr Rise Time IC= 150 mA, IB1= 15 mA 25 ns
ts Storage Time VCC= 30 V, IC= 150 mA, 225 ns
tf Fall Time IB1= IB2= 15 mA 60 ns
NPN (Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=255.9 Ne=1.307 Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0Ikr=0 Rc=1 Cjc=7.306p Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p Itf=.6Vtf=1.7 Xtf=3 Rb=10)
NPN General Purpose Amplifier(continued)
PN2222A
/M
MBT2222A
/PZT2222A
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Typical Characteristics
Typical Pulsed Current Gain
vs Collector Current
0.1 0.3 1 3 10 30 100 3000
100
200
300
400
500
I - COLLECTOR CURRENT (mA)h
-TYPICALPULSEDC
URRENT
GAIN
C
FE
125 C
25 C
- 40 C
V = 5VCE
Collector-Emitter Saturation
Voltage vs Collector Current
1 10 100 500
0.1
0.2
0.3
0.4
I - COLLECTOR CURRENT (mA)V
-COLLECTOR-EMITTERVOLTAGE(V)
CE
SAT
25 C
C
= 10
125 C
- 40 C
Base-Emitter Saturation
Voltage vs Collector Current
1 10 100 500
0.4
0.6
0.8
1
I - COLLECTOR CURRENT (mA)
V
-BASE-EMITTERVOLTAGE(V)
BE
SA
T
C
= 10
25 C
125 C
- 40 C
Base-Emitter ON Voltage vs
Collector Current
0.1 1 10 250.2
0.4
0.6
0.8
1
I - COLLECTOR CURRENT (mA)V
-BASE-EMITTERONVOLTAGE(V)
BE(ON)
C
V = 5VCE
25 C
125 C
- 40 C
Collector-Cutoff Current
vs Ambient Temperature
25 50 75 100 125 150
0.1
1
10
100
500
T - AMBIENT TEMPERATURE ( C)
I
-COLLEC
TORCURRENT(nA)
A
V = 40VCB
CBO
Emitter Transition and Output
Capacitance vs Reverse Bias Voltage
0.1 1 10 100
4
8
12
16
20
REVERSE BIAS VOLTAGE (V)
CAPAC
ITANCE(pF)
f = 1 MHz
C ob
C
te
NPN General Purpose Amplifier(continued)
PN2222A
/M
MBT2222A
/PZT2222A
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Typical Characteristics (continued)
Power Dissipation vs
Ambient Temperature
0 25 50 75 100 125 1500
0.25
0.5
0.75
1
TEMPERATURE ( C)
P
-POWERDISSIPATION(W)
D
o
SOT-223TO-92
SOT-23
Turn On and Turn Off Times
vs Collector Current
10 100 10000
80
160
240
320
400
I - COLLECTOR CURRENT (mA)
TIME(nS)
I = I =
t on
t off
B1
C
B2
I c
10
V = 25 Vcc
Switching Times
vs Collector Current
10 100 10000
80
160
240
320
400
I - COLLECTOR CURRENT (mA)
TIME
(nS)
I = I =
t r
t s
B1
C
B2
I c
10
V = 25 Vcc
t f
t d
PN2222A
/M
MBT2222A
/PZT2222A
NPN General Purpose Amplifier(continued)
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Typical Common Emitter Characteristics (f = 1.0kHz)
Common Emitter Characteristics
0 10 20 30 40 50 600
2
4
6
8
I - COLLECTOR CURRENT (mA)CHAR.RELATIVETOVALUESATI=10mA
V = 10 VCE
C
C T = 25 CAo
hoe
h re
h fe
h ie
Common Emitter Characteristics
0 20 40 60 80 1000
0.4
0.8
1.2
1.6
2
2.4
T - AMBIENT TEMPERATURE ( C)
CHAR.RELATIVETOVALUESATT
=25C
V = 10 VCE
A
A I = 10 mAC
hoe
hre
hfe
hie
o
o
Common Emitter Characteristics
0 5 10 15 20 25 30 350.75
0.8
0.85
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
V - COLLECTOR VOLTAGE (V)
CHAR.RELATIVETOVALUESATV
=10V
CE
CE
T = 25 CAo
hoe
h re
h fe
h ie
I = 10 mAC
NPN General Purpose Amplifier(continued)
PN2222A
/M
MBT2222A
/PZT2222A
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Test Circuits
30 V
1.0 K
16 V
0
200ns
200ns
500
200
50
37
- 1.5 V
1.0 K
6.0 V
0
30 V
FIGURE 2: Saturated Turn-Off Switching Time
FIGURE 1: Saturated Turn-On Switching Time
1k
PN2222A
/M
MBT2222A
/PZT2222A
NPN General Purpose Amplifier(continued)
NOTE: BVEBO
= 5.0 V
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TO-92 Tape and Reel Data
March 2001, Rev. B12001 Fairchild Semiconductor Corporation
TO-92 PackagingConfiguration: Figure 1.0
AMMO PACK OPTIONSee Fig 3.0 for 2 Ammo
Pack Options
2000 units perEO70 box for
std option
FSCINT Label
530mm x 130mm x
83mm
Intermediate box
10,000 units maximumper
intermediate boxfor std option
FSCINT Label
114mm x 102mm x 51mmImmediate Box
Anti-static
Bubble Sheets
(TO-92) BULK PACKING INFORMATION
EOLCODE
DESCRIPTIONLEADCLIP
DIMENSIONQUANTITY
J18Z TO-18 OPTION STD NO LEAD CLIP 2.0 K / BOX
J05Z TO-5 O PTION STD NO LEAD CLIP 1.5 K / BOX
NO EOLCODE
TO-92 STANDARDSTRAIGHT FOR: PKG 92,
NO LEADCLIP 2.0 K / BOX
BULK OPTIONSee Bulk PackingInformation table
375mm x 267mm x 375mm
Intermediate Box
FSCINT
Label
CustomizedLabel
333mm x 231mm x 183mmIntermediate Box
FSCINTLabel
CustomizedLabel
TO-92 TNR/AMMO PACKING INFROMATION
Packing Style Quantity EOL code
Reel A 2,000 D26Z
E 2,000 D27Z
Ammo M 2,000 D74Z
P 2,000 D75Z
Unit weight = 0.22 gmReel weight with components = 1.04 kgAmmo weight with components = 1.02 kgMax quantity per intermediate box = 10,000 units
F63TNRLabel
5 Ammo boxes perIntermediate Box
Customized
Label
327mm x 158mm x 135mm
Immediate Box
LOT: CBVK741B019
NSID: PN2222N
D/C1: D9842 SPEC REV: B2
SPEC:
QTY: 10000
QA REV:
FAIRCHILD SEMICONDUCTOR CORPORATION HTB:B
(FSCINT)
F63TNRLabel
CustomizedLabel
5 Reels perIntermediate Box
TAPE and REEL OPTIONSee Fig 2.0 for various
Reeling Styles
LOT: CBVK741B019
FSID: PN222N
D/C1: D9842 QTY1: SPEC REV:
SPEC:
QTY: 2000
D/C2: QTY2: CPN:N/F: F (F63TNR)3
F63TNR Label sample
FSCINT Label sample
C
5 EO70 boxes per
intermediate Box
ustomizedLabel
94 (NON PROELECTRON
SERIES), 96
L34Z TO-92 STANDARDSTRAIGHT FOR: PKG 94
NO LEADCLIP 2.0 K / BOX
(PROELECTRON SERIES
BCXXX, BFXXX, BSRXXX),
97, 98
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TO-92 Tape and Reel Data, continued
September 1999, Rev. B
TO-92 Reeling StyleConfiguration: Figure 2.0
Style A, D26Z, D70Z (s/h)
Machine Option A (H)
Style E, D27Z, D71Z (s/h)
Machine Option E (J)
FIRST WIRE OFF IS EMITTERADHESIVE TAPE IS ON THE TOP SIDEFLAT OF TRANSISTOR IS ON BOTTOM
ORDER STYLE
D75Z (P)
FIRST WIRE OFF IS COLLECTORADHESIVE TAPE IS ON THE TOP SIDEFLAT OF TRANSISTOR IS ON TOP
ORDER STYLE
D74Z (M)
TO-92 Radial Ammo PackagingConfiguration: Figure 3.0
FIRST WIRE OFF IS EMITTER (ON PKG. 92)ADHESIVE TAPE IS ON BOTTOM SIDEFLAT OF TRANSISTOR IS ON BOTTOM
FIRST WIRE OFF IS COLLECTOR (ON PKG. 92)ADHESIVE TAPE IS ON BOTTOM SIDEFLAT OF TRANSISTOR IS ON TOP
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ITEM DESCRIPTION
Base of Package to Lead Bend
Component Height
Lead Clinch Height
Component Base Height
Component Alignment ( side/side )
Component Alignment ( front/back )
Component Pitch
Feed Hole Pitch
Hole Center to First Lead
Hole Center to Component Center
Lead Spread
Lead Thickness
Cut Lead Length
Taped Lead Length
Taped Lead Thickness
Carrier Tape Thickness
Carrier Tape Width
Hold - down Tape Width
Hold - down Tape position
Feed Hole Position
Sprocket Hole Diameter
Lead Spring Out
SYMBOL
b
Ha
HO
H1
Pd
Hd
P
PO
P1
P2
F1/F2
d
L
L1
t
t1
W
WO
W1
W2
DO
S
DIMENSION
0.098 (max)
0.928 (+/- 0.025)
0.630 (+/- 0.020)
0.748 (+/- 0.020)
0.040 (max)
0.031 (max)
0.500 (+/- 0.020)
0.500 (+/- 0.008)
0.150 (+0.009, -0.010)
0.247 (+/- 0.007)
0.104 (+/- 0 .010)
0.018 (+0.002, -0.003)
0.429 (max)
0.209 (+0.051, -0.052)
0.032 (+/- 0.006)
0.021 (+/- 0.006)
0.708 (+0.020, -0.019)
0.236 (+/- 0.012)
0.035 (max)
0.360 (+/- 0.025)
0.157 (+0.008, -0.007)
0.004 (max)
Note : All dimensions are in inches.
ITEM DESCRIPTION SYSMBOL MINIMUM MAXIMUM
Reel Diameter D1 13.975 14.025
Arbor Hole Diameter (Standard) D2 1.160 1.200
(Small Hole) D2 0.650 0.700
Core Diameter D3 3.100 3.300
Hub Recess Inner Diameter D4 2.700 3.100
Hub Recess Depth W1 0.370 0.570
Flange to Flange Inner Width W2 1.630 1.690
Hub to Hub Center Width W3 2.090
Note: All dimensions are inches
TO-92 Tape and Reel TapingDimension Configuration: Figure 4.0
Ha
H1 HO
PO
P2
P1 F1
DO
P Pd
b
d
L1
LS
WOW2
W
t
t1
Hd
W1
TO-92 Reel
Configuration: Figure 5.0
User Direction of Feed
SENSITIVEDEVICES
ELECTROSTATIC
D1
D3
Customized Label
W2
W1
W3
F63TNR Label
D4
D2
TO-92 Tape and Reel Data, continued
July 1999, Rev. A
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TO-92 (FS PKG Code 92, 94, 96)
TO-92 Package Dimensions
January 2000, Rev. B
1:1Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.1977
2000 Fairchild Semiconductor International
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SOT-23 PackagingConfiguration: Figure 1.0
ComponentsLeader Tape500mm minimum or
125 empty pockets
Trailer Tape300mm minimum or
75 empty pockets
SOT-23 Tape Leader and TrailerConfiguration: Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
PackagingOption
SOT-23 PackagingInformation
Standard(no flow code)
D87Z
Packagingtype
Reel Size
TNR
7" Dia
TNR
13"
Qty per Reel /Tube/Bag 3,000 10,000
Box Dimension (mm) 187x107x183 343x343x64
Max qty per Box 24,000 30,000
Weight per unit (gm) 0.0082 0.0082
Weight per Reel (kg) 0.1175 0.4006
Human readable
Label
Human Readable Label
Human Readable Label sample
343mm x 342mm x 64mmIntermediate box for L87Z Option
187mm x 107mm x 183mmIntermediate Box for Standard Option
SOT-23 Unit Orientation
3P 3P 3P 3P
Human ReadableLabel
Customized Label
EmbossedCarrier Tape
Antistatic Cover Tape
Packaging Description:
SOT-23made from a dissipative (carbon filled) polyca rbonateresin. The cover tape is a multilayer fil m (H eat A ctivatedAdhesive in nature) primarily composedof polyester film,adhesive l ayer, sealant, and anti-static sprayed agent.These reeled parts in standard option are shipped with3,000 units per 7" or 177cm diameter reel. The reels aredark blue in color a nd is made of polystyreneplastic (anti-static coated). Other option comes in 10,000 units per 13"or 330cm diameter reel. This and some other options aredescribed in the Packaging Information table.
These full r eels areindiv idually l abeled and placed insidea standard intermediate made of recyclable corrugatedbrown paper with a Fairchild logo printing. One pizza boxcontains eight reels maximum. And these intermediateboxes are placed inside a labeled shipping box whichcomesi n diff erent sizes depending on the number of partsshipped.
parts are shipped in tape. The carrier tape is
SOT-23 Tape and Reel Data
September 1999, Rev. C2000 Fairchild Semiconductor International
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Dimensions are in millimeter
Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc
SOT-23
(8mm)
3.15
+/-0.10
2.77
+/-0.10
8.0
+/-0.3
1.55
+/-0.05
1.125
+/-0.125
1.75
+/-0.10
6.25
min
3.50
+/-0.05
4.0
+/-0.1
4.0
+/-0.1
1.30
+/-0.10
0.228
+/-0.013
5.2
+/-0.3
0.06
+/-0.02
Dimensions are in inches and millimeters
Tape SizeReel
OptionDim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
8mm 7" Dia7.00177.8
0.0591.5
512 +0.020/-0.00813 +0.5/-0.2
0.79520.2
2.16555
0.331 +0.059/-0.0008.4 +1.5/0
0.56714.4
0.311 0.4297.9 10.9
8mm 13" Dia13.00330
0.0591.5
512 +0.020/-0.00813 +0.5/-0.2
0.79520.2
4.00100
0.331 +0.059/-0.0008.4 +1.5/0
0.56714.4
0.311 0.4297.9 10.9
See detail AA
Dim A
max
13" Diameter Option
7" Diameter Option
Dim AMax
See detail AA
W3
W2 max Measured at Hub
W1 Measured at Hub
Dim N
Dim Dmin
Dim C
B Min
DETAIL AA
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum component rotation
0.5mmmaximum
0.5mmmaximum
Sketch C (Top View)
Component lateral movement
Typicalcomponentcavitycenter line
20 deg maximum
Typicalcomponentcenter line
B0
A0
Sketch B (Top View)
Component Rotation
Sketch A (Side or Front Sectional View)
Component Rotation
User Direction of Feed
SOT-23 Embossed Carrier TapeConfiguration: Figure 3.0
SOT-23 Reel Configuration: Figure 4.0
P1 A0
D1
F W
E1
E2
Tc
Wc
K0
T
B0
D0P0 P2
SOT-23 Tape and Reel Data, continued
September 1999, Rev. C
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SOT-23 (FS PKG Code 49)
SOT-23 Package Dimensions
September 1998, Rev. A1
1:1Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0082
2000 Fairchild Semiconductor International
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SOT-223 PackagingConfiguration: Figure 1.0
ComponentsLeader Tape500mm minimum or62 empty pockets
Trailer Tape300mm minimum or38 empty pockets
SOT-223 Tape Leader and TrailerConfiguration: Figure 2.0
Cover Tape
Carrier Tape
Note/Comments
Packaging Option
SOT-223 Packaging Information
Standard(no flow code)
D84Z
Packaging type
Reel Size
TNR
13" Dia
TNR
7" Dia
Qty per Reel/Tube/Bag 2,500 500
Box Dimension (mm) 343x64x343 184x187x47
Max qty per Box 5,000 1,000
Weight per unit (gm) 0.1246 0.1246
Weight per Reel (kg) 0.7250 0.1532
SOT-223 Unit Orientation
F852
014F852
014F852
014F852
014
F63TNR Label343mm x 342mm x 64mm
Intermediate box for Standard
184mm x 184mm x 47mm
Pizza Box for D84Z Option
F63TNR Label
LOT: CBVK741B019
FSID: PN2222A
D/C1: D9842 QTY1: SPEC REV:
SPEC:
QTY: 3000
D/C2: QTY2: CPN:N/F: F (F63TNR)3
F63TNR Label sample
F63TNR Label
Antistatic Cover Tape
Customized Label
Static DissipativeEmbossed Carrier Tape
Packaging Description:SOT-223 parts are shipped in tape. The carrier tape ismade from a dissipative (carbon filled) polycarbonateresin. The cover tape is a multilayer film (Heat ActivatedAdhesive in nature) primarily composed of polyester film,adhesive layer, sealant, and anti-static sprayed agent.These reeled parts in standard option are shipped with2,500 units per 13" or 330cm diameter reel. The reels aredark blue in color and is made of polystyrene plastic (anti-static coated). Other option comes in 500 units per 7" or177cm diameter reel. This and some other options arefurther described in the Packaging Information table.
These full reels are individually barcode labeled andplaced inside a standard intermediate box (illustrated infigure 1.0) made of recyclable corrugated brown paper.One b