Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP
B.V. All other product or service names are the property of their respective owners. © 2019 NXP B.V.
Sr. Principal Engineer
NXP Digital Networking BL
Geoff Waters
Layerscape in Automotive — Multicore Arm Processors for Telematics, Gateway and AD Sensor Fusion
June 2019 | Session #AMF-AUT-T3662
COMPANY PUBLIC 1COMPANY PUBLIC 1
• NXP Multicore Processor Families
• Digital Networking Layerscape Products
• Service Oriented Gateway
• ADAS/BlueBox
• Summary
Agenda
COMPANY PUBLIC 2
NXP Automotive Microprocessors & MicrocontrollersBL DN
(Digital Networking)
High Performance
Networking & Computing
• Highest networking & compute
performance SoCs in NXP
• Experts in Linux, networking
protocols, network security,
virtualization
• #1 SoC Architecture in Mil/AeroProducts
QorIQ
Layerscape
ADAS(Advanced Driver Assistance
Systems)
Radar, LIDAR
Vision
Sensor Fusion
• #1 in Radar with strong IP
and system knowledge
• High performance low power
accelerators
• Scalable high performance
roadmap for central
processing
Products
S32R - Radar
S32V - Vision
VDS(Vehicle Dynamics & Safety)
C&S(Connectivity & Security)
GatewayChassis & Safety
Powertrain & Hybrid/EV
• Long term Innovator in
Chassis and Powertrain
Control.
• Significant Growth in Safety
as Autonomous Control
Drives Robust Fault Tolerant
Systems
• #1 in Vehicle Networking with
leading networking and security
IP
• #1 in Automotive HW Security
with Strong IP and broad
portfolio
• End to end portfolio of
networking devices
(MCU/MPU, TX/RX)
Products Products
MPC564xB/C
MPX574xG
S32
MPC56xx
MPC57xx
S32S/P/H
GPIS(General Purpose & Integrated
Solutions)
Body Electronics
Edge Nodes
• 500+ customers
• Broadest portfolio of
integrated MCU+HV mixed-
signal solutions
• Complete Tools & Software
enablement
Products
S08/S12/PPC ARM
KEA – S32K
S12 MagniV – S32M
BL AMP
BL Micros
Multimedia Processing
• HMI, Multimedia, Compute,
Image Processing Leader
• GPUs with 1 to 16 Vec4 shaders, 8
to 256 GFLOPS
• With ML Framework
• Power efficiency, battery operation
Products
i.MX
COMPANY PUBLIC 3
DN Processors in Mission Critical Applications
Fuel Management, Main Flight Control, Secondary Flight Control, Aircraft Engine
Management, Cockpit Display
Rocket navigation, Artillery Control Computer, IFF
IFF, UAV Flight Computer, Defense Airborne Computer, Weapon
Navigation System, Ground Control System
Robotics Controllers, Motion Controllers, Multi-Axis Motor Controllers, Safety PLCs
Traction Control, Railway Signaling Controller, Railway Communications, Brake
Controller
Power Distribution Relays, Smart Grid Communications
Aerospace Military and Defense
Factory Automation Railway Power Grid
COMPANY PUBLIC 4
Layerscape Longevity
NXP Application Processors
• 10 and 15 year supply longevity options
• Formal program with products listed at
www.nxp.com/productlongevity
Industrial & Automotive applications require
product longevity
• Long product lifecycles
• Special product certification required
Digital Networking is still selling the (Motorola) 68302, a processor which was introduced in 1989. Many other products are
still shipping after >20 years.
Any Layerscape product selected for a production vehicle will be guaranteed 10yrs supply, regardless of official start date of
10-15 year guarantee in longevity program.
COMPANY PUBLIC 5
LS1012A• Cortex-A53
• 800MHz
• 2Gbps Packet
• 1Gbps Crypto
• 1-2W
• Lowest power
64-bit ARM
LS1021A• Cortex-A7
• 2 cores
• 1GHz
• 2Gbps Pkt
• 1Gbps Crypto
• 2W
LS1043A• Cortex-A53
• 2-4 cores
• 10Gbps Pkt
• 5Gbps Crypto
• 4-8W
• 1st 64-bit ARM
processor
LS1084A• Cortex-A53
• 4-8 cores
• 1.5GHz
• DPAA2
• 20Gbps Pkt
• 10Gbps Crypto
• 15-20W
• 1st 8x A53 ARM
Next gen
programmable
offload
LS1046A• Cortex-A72
• 4 cores
• DPAA1
• 10Gbps Pkt
• 10Gbps Crypto
• 8-15W
• 1st Value Tier A72
ARM
LS2084A• Cortex-A72
• 4-8 cores
• DPAA2
• 40G Pkt
• 20G Crypto
• 20-35W
• 1st 8x A72 ARM
Next gen
programmable
offload
LX2160A• Cortex-A72
• 16 cores
• 100Gbps Pkt
• 100Gbps Crypto
• 40W
• 1st 16nm product
LS1028A• Cortex-A72
• 2 cores
• 5Gbps Pkt
• 5Gbps Crypto
• 4-9W
• 1st with TSN switch
• Integrated GPU
Sampling
Auto Qual Plan*
* Additional products can be auto
qualified with business justification
Layerscape Portfolio
Pin Compatible
Production
COMPANY PUBLIC 6
Comparative NXP ARM Processing Capacity
0
50
100
150
200
250
KD
MIP
S
2x64b DDR
64b DDR
32b DDR
16b DDR
COMPANY PUBLIC 7
Comparative NXP ARM Packet Processing Capacity & High
Speed IO
0
20
40
60
80
100
120
140
Gb
ps
Ethernet MAC
(capable, not aggregate)
PCIe USB
Product 10G 2.5G 1G ControllersMax
lanes2.0 3.0
i.MX 8DualMax 0 0 1 2x 3.0 1 2 1
i.MX 8Quad 0 0 2 2x 3.0 1 2 1
LS1012A 0 2 2 1x 2.0 2 1 1
LS1043A 1 2 5 3x 2.0 4 0 3
LS1046A 2 2 5 3x 3.0 8 0 3
LS1084A 2 0 8 3x 2.0 8 0 3
LS2084A 8 8 8 3x 3.0 16 0 2
LX2160A 10 10 16 6x 3.0 24 0 2
Refer to product specific documents for exact features and performance
COMPANY PUBLIC 8
NXP Auto’s View of Domains and Functions
Bo
dy &
Com
fort
Driver
Experie
nce
Con
ne
ctivity
Dri
ve
r
Rep
lace
me
nt
Po
we
rtra
in &
Ve
hic
le
Dyn
am
ics
SENSE THINK ACT
V2X
Broadcast Radio
Cellular
NFC
Smart Car Access
Radar
Camera
Lidar
Motion & Pressure
Speed
Ultrasonic
Smart Light
Access, Door Ctrl
eCockpit
Amplifiers
Powertrain &
Vehicle DynamicsEngine
Transmission
Brake
Battery Cell Management
Steering
Airbag
Suspension
Infotainment
Fusion
WiFi, BT, GNSS,
TPMS
Powertrain
Domain Controller
Connectivity
Domain Controller
Body
Domain Controller 4
5
1
2
3
Layerscape
COMPANY PUBLIC 9
Central Gateway
Actuator
Actuator
Actuator
Actuator
Actuator
Actuator
Actuator
Actuator
Domain
Controller
Sensor
Sensor
Sensor
Sensor
S32V(Vision)
Switch
Sensor
Sensor
Sensor
Sensor
3rd party(LIDAR)
SwitchDSRC
V2X
Actuator
Actuator
Actuator
Actuator
Domain
Controller
Domain
Controller
Sensor
Sensor
Sensor
Sensor
S32R(RADAR)
Switch
Infotainment/
eCockpit
Telematics
Control Unit /
Wireless
Gateway
Cellular
Modem
Wi-Fi /
BT
Central Fusion
C-V2X
GPS
LS1043A
Apps Processing + Ethernet
Networking
MPC5748G
Auto MCU, AutoSAR, CAN
Switch
LS2/LX2
High DMIPS (Planner)
S32x
ASIL-D MIPS (Safety)
3rd Party
High TOPS (Perception)
Conceptual Vehicle Architecture
COMPANY PUBLIC 11
MPC-LS VNP Reference Design Board Preview
VNP Reference Design Board (RDB) provides value to customers with a more representative reference
design schematics & layout for automotive MPC-LS solutions.
. • Single 6-layer board ~ 6.1 x 6.4 x <2.0 inches
• 90% of the BOM is available in Automotive Grade
COMPANY PUBLIC 12
MPC-LS-VNP-RDB System Solution
LIN FlexRay SPI FlexCAN
JTAGSJA1105SEL
Ethernet SwitchEthernet
RMII
SPI
MPC5748G
SDHCPCIe
LS1043A
M.2 M-Key
Connector
eMMC
8GBEEPROM
NAND
Flash
Ethernet 6USB 3.0
2
Dual Stacked
USB Connector
GPIO
DDR3L
2GB + ECC
GPIO
LIN
JTAG
Header
30 pin ConnectorFlexRay
Connectors
Console
Connector
10BASE-T
100BASE-TX
1000BASE-T
Connector
100BASE-T1
Connector
USB 3.0
1Ethernet 5 Ethernet 4
JTAG
Header
JTAG
Ethernet 2
SPI to
CAN
Dual Stacked RJ45
Connector
RJ45
Connector
IFC
DDR
UART
QSPINOR
Flash
100BASE-T1
Connector
PF8200
PMIC
Power
Console
Connector
I2CEEPROM
USB to Serial
UART
TJA1048
CAN PHYs
TJA1024
LIN PHY
TJA1048
CAN PHYsTJA1081
FlexRay PHYs
TJA1102
ENET PHY (MII)
ENET PHY
RGMII
ENET PHY
RGMII
ENET PHY
RGMII
ENET PHY
1, 2.5, 10G
USB to Serial
UART
I2C
NVMe SSD
(optional)
Port 1Port 3Port 2Port 4
Port 0
SPI
COMPANY PUBLIC 13
MPC5748G Gateway Microcontroller
Multicore architecture
• Power Architecture cores
• 2x e200z4 @ 160MHz, with
floating point unit
• 1x e200z2 @ 80MHz
Triple ported flash and
multiple RAM for low memory
latency
Safe Assure Functional
Safety Program
• Designed for ISO 26262
ASIL B systems
Media Local Bus Supports MOST for infotainment
domain networking
USB 2.0 (OTG and host
module) supports interfacing to
both wireless modems and
infotainment domain
2 x Ethernet modules and
Ethernet Switch support 10/100
Mb/s for diagnostics, backbone and
AVB applications
Low-Power Unit (LPU) provides CAN, LIN, SPI, ADC
functionality in a new low power
state
Broad Communications Multiple CAN, LIN, I²C, I²S for
integrated BCM & Gateway
applications
Robust security Hardware Security Module
(HSM) option supports both SHE
and EVITA low/medium
security specifications
MPC5748G
Cores 3
Flash 6 MB
RAM 768 KB
Eth/FR/ML
/SD/USB
2/1/1/1/2
COMPANY PUBLIC 14
QorIQ Layerscape LS1043ACE (Grade 3)
Performance
• ARM A53 x 4 @ up to 1.6GHz (LS1023A: 2 cores)
− 19.5K DMIPS
− SpecInt2k6 – 5.95, Rate -15
− Neon SIMD in all CPUs
• 1x36b (including ECC) DDR3L/4 up to 1.6GT/s
− 6.4GB/s memory BW
• High Speed IO
− Multiple PCIe Gen2 controllers
− Multiple Ethernet MACs (up to 10G)
Auto Quality• AEC Q100 Grade 3 (105 Tj max)
• 15 years product longevity
• ZD-like approach to reduce risk of DPPM
or Life failures
• Expected Operating Life fail rate <10 FIT
• Mission Profile: 10 years, 90C Tj-effective
Security
• 5Gbps Crypto Acceleration
• IPsec, SSL
• Trust Architecture
− Secure Boot
− Secure Debug
− Secure Storage
− Tamper Detection
− HW Enforced Partitioning
− ARM Trust Zone
Functional Safety
• Target ASIL-B*
• ECC protected memories
• Fault localization, containment and recovery
• Soft lockstep with determinism
• Excellent support for virtualization,
containerization
Process & Package
• 28HPM, ~5-9W Thermal Max @ 105C
• 23x23mm, Lidded FCBGA, .8mm pitch
(780 pins)
32-bit
DDR3L/4
Memory Controller
Interconnect
SA
TA
3
Gen2 P
EX
Gen2 P
EX
Gen2 P
EX
Queue Manager
Buffer ManagerSEC – 5G
Secure Boot
Trust Zone
Power Mgt
SD/eMMC
2x DUART, 6x
LPUART
4x I2C
SPI, GPIO, JTAG
3x USB3.0 + PHYSERDES 4 lanes @ up to 10GHz
Frame Manager
1MB Banked L2
ARM
A53
ARM
A53
ARM
A53
ARM
A53
Parse, Classify,Distribute, Autorespond
10/1G
1G 1G
Flash Ctl, QSPI
uQE
SMMU
2.5/1G
1G2.5/1G
1G
Major Milestone Schedule
Engineering Samples Rev
1.1
Completed / October
4, 2016
Networking/Telecom
Qualification
Completed / January
25, 2017
AECQ100 grade 3 Qual on
Rev 1.1
Complete / Sept 12,
2017
PPAP Completion
June 2018
Updated PPAP (for
new lidded package)
Jan 2019
COMPANY PUBLIC 16
QorIQ Layerscape LS1043ABE (Grade 2)
Performance
• ARM A53 x 4 @ up to 1.4GHz (LS1023A: 2
cores)
− 17K DMIPS
− SpecInt2k6 – 5.2, Rate -13.1
− Neon SIMD in all CPUs
• 1x36b (including ECC) DDR3L/4 up to 1.6GT/s
− 6.4GB/s memory BW
• High Speed IO
− Multiple PCIe Gen2 controllers
− Multiple Ethernet MACs (up to 2.5G)
Auto Quality• AEC Q100 Grade 2 (125 Tj
max)
• 15 years product longevity
• ZD-like approach to reduce risk
of DPPM or Life failures
• Expected Operating Life fail
rate <10 FIT
• Mission Profile: 10 years, 90C
Tj-effective
Security
• 5Gbps Crypto Acceleration
• IPsec, SSL
• Trust Architecture
− Secure Boot
− Secure Debug
− Secure Storage
− Tamper Detection
− HW Enforced Partitioning
− ARM Trust Zone
Functional Safety
• Target ASIL-B*
• ECC protected memories
• Fault localization,
containment and recovery
• Soft lockstep with
determinism
• Excellent support for
virtualization,
containerization
Process & Package• 28HPM, up to 11W
Thermal Max @ 125C
• 23x23mm, Lidded
FCBGA, .8mm pitch
(780 pins)
32-bit
DDR3L/4
Memory Controller
Interconnect
SA
TA
3
Gen2 P
EX
Gen2 P
EX
Gen2 P
EX
Queue Manager
Buffer ManagerSEC – 5G
Secure Boot
Trust Zone
Power Mgt
SD/eMMC
2x DUART, 6x
LPUART
4x I2C
SPI, GPIO, JTAG
3x USB3.0 + PHYSERDES 4 lanes @ up to 5GHz
Frame Manager
1MB Banked L2
ARM
A53
ARM
A53
ARM
A53
ARM
A53
Parse, Classify,Distribute, Autorespond
10/1G
1G 1G
Flash Ctl, QSPI
uQE
SMMU
2.5/1G
1G2.5/1G
1G
Major Milestone Schedule
Engineering Samples Completed / May 2018
AECQ100 grade 2 Qual Completed / Oct, 2018
Grade 2 PPAP Completion Jan 2019
COMPANY PUBLIC 18
LS1043 SERDES Options
• Rows with green right edge are
supported on grade 2 version
• Rows with black right edge are
only supported on grade 3
version
Grade 3 Grade 2
Serdes 1
0 1 2 3
SERDES Prot A B C D
0000 unused unused unused unused
1555 XFI PCIe 1 PCIe 2 PCIe 3
2555 SGMII 2.5G PCIe 1 PCIe 2 PCIe 3
4555 QSGMII PCIe 1 PCIe 2 PCIe 3
4558 QSGMII PCIe 1 PCIe 2 SATA
1355 XFI SGMII 1G PCIe 2 PCIe 3
2355 SGMII 2.5G SGMII 1G PCIe 2 PCIe 3
3335 SGMII 1G SGMII 1G SGMII 1G PCIe 3
3355 SGMII 1G SGMII 1G PCIe 2 PCIe 3
3358 SGMII 1G SGMII 1G PCIe 2 SATA
3558 SGMII 1G PCIe 1 PCIe 2 SATA
3555 SGMII 1G PCIe 1 PCIe 2 PCIe 3
7000 PCIe 1
9998 PCIe 1 PCIe 2 PCIe 3 SATA
6058 PCIe 1 PCIe 2 SATA
1455 XFI QSGMII PCIe 2 PCIe 3
2455 SGMII 2.5G QSGMII PCIe 2 PCIe 3
2255 SGMII 2.5G SGMII 2.5G PCIe 2 PCIe 3
3333 SGMII 1G SGMII 1G SGMII 1G SGMII 1G
1460 XFI QSGMII PCIe 3
2460 SGMII 2.5G QSGMII PCIe 3
3460 SGMII 1G QSGMII PCIe 3
3455 SGMII 1G QSGMII PCIe 2 PCIe 3
9960 PCIe 1 PCIe 2 PCIe 3
2233 SGMII 2.5G SGMII 2.5G SGMII 1G SGMII 1G
2533 SGMII 2.5G PCIe 1 SGMII 1G SGMII 1G
LS1043 SERDES (4 lanes)
COMPANY PUBLIC 19
Gateway/Vehicle Server Scalability
Eth
ern
et
PC
Ie
Auto
IFs
S32x
Apps Proc
MPC or S32
2x 2
.5G
4x 1
G
LS1043A
Auto
IFs
MPC or S32
Auto
IFs
2x 1
0G
1x 2
.5G
3x P
CIe
4x 1
G
LS1046A
1x 1
0G
MPC or S32
1x 2
.5G
4x 1
G T
SN
LS1028
Auto
IFs
3x P
CIe
2x P
CIe
Pin
compatible
COMPANY PUBLIC 21
ADAS System Functional Building Blocks
ASIL-D Island
General Purpose
Compute Island
Infrastructure,
Communication,
Security Island
Parallel Processing
SIMD/MIMD/AI
Accelleration Island
Vision Processing Island
Redundant ASIL-B
Island
COMPANY PUBLIC 22
Layerscape
S32x
ASIL-D Island
General Purpose
Compute Island
Infrastructure,
Communication,
Security Island
Parallel Processing
SIMD/MIMD/AI
Accelleration Island
Vision Processing Island
Redundant ASIL-B
Island
Mapping of NXP Products to ADAS Functional Partitioning
SOP 2022
COMPANY PUBLIC 23
S32V
Layerscape
S32x
ASIL-D Island
General Purpose
Compute Island
Infrastructure,
Communication,
Security Island
Parallel Processing
SIMD/MIMD/AI
Accelleration Island
Vision Processing Island
Redundant ASIL-B
Island
Mapping of NXP Products to ADAS Functional Partitioning
SOP 2023
COMPANY PUBLIC 24
High Level Architecture
• Flexible architecture allowing various 3rd party accelerator based on customer needs
• Open SW standard based on proven embedded ARM architecture
• Expedite time to market
LX2160A
S32x
LX2160A
ISP
Optional Depending
On Accelerator
Optional Safety Channel
Safety Companion
Vision Perception
Fusion & Planning3rd party
Accelerator
Big Data Compute Safe Computing
COMPANY PUBLIC 26
BlueBox 2.0 Inside
• LS2084A in the middle
• Two DIMM sockets
• S32V234 and camera i/f at
top/left
• S32R275 at top right
• Automotive SSD
• IVN subsystem hidden under
SSD
COMPANY PUBLIC 27
BlueBox 2.0 – NXP Software & Partners
Helios
COMMUNICATION
UART, ENET, CAN
PCIe, I2C, DSPI
GRAPHICS
DCU,
FRAMEBUFFER,
GPU, VIU,
ENCODERS
SECURITY
CRYPTO
SECUREBOOT
SOCTIMERS, PINMUX
GPIO, CLOCKS
INTERRUPTS, WDG
MIDDLEWARE
ROS Kinetic and v2.0 Middleware SDK
TOOLS
ICC
ROOTFS (Ubuntu rootfs)
BOOTLOADERS
UBOOT
UEFI
Neusoft Vision
Perception SW
Neusoft MIPI
Driver for the
S32V
Lane
centering
Adaptive
cruise
Traffic
jam
assist
Intelligent
lane
change
RobinOS
Motion
Planning
Object
Detection
Valet Parking
Deep Learning
NN
Full System HW+SW Set-up
Sensor Fusion + Camera Node
BLUEBOX 2.0 (LS2084A, S32V, S32R)
Apollo
NXP
NXP
Neusoft
Elektrobit
Polysync
Baidu
AutonomouStuff
Berkley
COMPANY PUBLIC 28
BlueBox 3.0 High Level Concept
Flexibility:• Camera configuration
• NN type, performanceSafety:• HW ASIL-D companion SoC
• Safety checker
• Safety channel
LX2160A
S32x
LX2160A
(Optional)
ISP
Safety Checker
Perception/Model
Fuse & PlanPartner
Accelerator
Flexibility & Safety:• Rule Base Algorithm
Safety Channel
COMPANY PUBLIC 29
ADAS Planner Scalability
S32x S32x
8x 1
0G
8x 1
/2.5
G
4x P
CIe
LS2084A
8x 1
0G
8x 1
/2.5
G
6x P
CIe
LX2160
Eth
ern
et
PC
Ie
Au
to IF
s
Eth
ern
et
PC
Ie
Au
to IF
s
Pin
compatible
1
S32x
8x 1
0G
8x 1
/2.5
G
4x P
CIe
LS2044A
Eth
ern
et
PC
Ie
Au
to IF
s
S32x
8x 1
0G
8x 1
/2.5
G
6x P
CIe
LX2080
Eth
ern
et
PC
Ie
Au
to IF
s
S32x
8x 1
0G
8x 1
/2.5
G
6x P
CIe
LX2120
Eth
ern
et
PC
Ie
Au
to IF
s
Pin
compatible
2
COMPANY PUBLIC 30
LS2/LX2 Scalability
A72 Cores Frequency KDMIPS SpecInt
LS2044 4 1.8GHz 43 SpecInt2k6 13.1, Rate 37.5
LS2084 8 1.8GHz 86 SpecInt2k6 13.1, Rate 75.1
LX2080 8 1.8GHz 86 SpecInt2k6 14.4, Rate 64.3
2.0GHz 95 SpecInt2k6 16.0, Rate 71.5
2.2GHz 105 SpecInt2k6 17.6, Rate 78.7
LX2120 12 1.8GHz 129 SpecInt2k6 14.4, Rate 96.5
2.0GHz 143 SpecInt2k6 16.0, Rate 107
2.2GHz 157 SpecInt2k6 17.6, Rate 118
LX2160 16 1.8GHz 172 SpecInt2k6 14.4, Rate 129
2.0GHz 191 SpecInt2k6 16.0, Rate 143
2.2GHz 210 SpecInt2k6 17.6, Rate 157
COMPANY PUBLIC 31
Layerscape LS2084A
Performance (Grade 3)• ARM A72 x 8 @ 1.8 GHz
− 86K DMIPS
− SpecInt2k6 – 13.1, Rate -75.1
− Neon SIMD in all CPUs
• 2x72b (w/ECC) DDR4 @ 1.8GT/s
− 28.8GB/s memory BW
• High Speed IO
• Multiple PCIe Gen3 controllers
• Multiple Ethernet MACs (up to 10G)
Auto Quality• AEC Q100 Grade 3 (105C Tj)
• 15 years product longevity
• ZD-like approach to reduce risk of DPPM or Life failures
• Expected Operating Life fail rate <10 FIT
• Mission Profile: 10 years, 90C Tj-effective
Security• 20Gbps Crypto Acceleration
• MACSEC, IPsec, SSL
• Trust Architecture
− Secure Boot
− Secure Debug
− Secure Storage
− Tamper Detection
− HW Enforced Partitioning
− ARM Trust Zone
Functional Safety• Target ASIL-B*
• ECC protected memories
• Fault localization, containment and recovery
• Soft lockstep with determinism
• Excellent support for virtualization, containerization
Process & Package
• 28HPM, ~40W Thermal Max @ 105C
• 37.5 x 37.5 mm, lidded FCBGA, 1mm pitch, 1292 pins
72-b
it D
DR
4
Me
mo
ry
Co
ntr
olle
r
1 M
B
Pla
tfo
rm
Ca
ch
e
1MB Banked L2
ARM
A72
ARM
A72
Interconnect
72-b
it D
DR
4
Me
mo
ry
Co
ntr
olle
r
SA
TA
3S
AT
A3
x8
Ge
n3
PE
X
x4
Ge
n3
PE
X
x4
Ge
n3
PE
X
x8
Ge
n3
PE
XQueue Manager
Buffer Manager
SEC – 20G
DCE – 20G
Secure Boot
Trust Zone
Power Mgt
SD/eMMC
2x DUART
4x I2C
SPI, GPIO, JTAG
2x USB3.0 + PHY
SERDES 16 lanes @ up to 10GHz
Wire Rate IO Processor
2MB Packet Buffer
8x1/10 + 8x1 Ethernet MACs
L2 Switching
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
PME – 10G
Major Milestone Schedule
Samples (Production Rev) Dec 2017
Networking/Telecom Qualification March 2018
AECQ100 grade 3 Qual on production rev Nov 2018
PPAP Completion Aug 2019
COMPANY PUBLIC 32
Layerscape LX2160ASamples (Rev1): Now
Samples (Rev2): April 2020 (fully tested)
Telecom Production: May 2020
Auto Grade 3 & PPAP: Oct 2020
Performance• ARM A72 x 16 @ 2.2 GHz
− ~201K DMIPS
− SpecInt2k6 – 17.6, Rate -157
− Neon SIMD in all CPUs
• 2x72b (including ECC) DDR4 up to 3.2GT/s
− 51GB/s memory BW
• High Speed IO
• Multiple PCIe Gen3 controllers
• Multiple Ethernet MACs (up to 100G)
Auto Quality
• AEC Q100 Grade 3 (105 Tj)
• 15 years product longevity
• ZD-like approach to reduce risk of DPPM
or Life failures
• Expected Operating Life fail rate <10 FIT
• Mission Profile: 10 years, 90C Tj-effective
Security• 50Gbps Crypto Acceleration
• MACSEC, IPsec, SSL
• Trust Architecture
− Secure Boot
− Secure Debug
− Secure Storage
− Tamper Detection
− HW Enforced Partitioning
− ARM Trust Zone
Functional Safety• Target ASIL-B*
• ECC protected memories
• Fault localization, containment and recovery
• Soft lockstep with determinism
• Excellent support for virtualization, containerization
Process & Package
• 16FFC, ~25W Thermal Max @ 105C – 2.0GHz
• 40x40mm, Lidded FCBGA, 1mm pitch (1517 pins)
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Queue Manager
Buffer Manager
SEC – 50G
DCE – 50G
Secure Boot
Trust Zone
Power Mgt
SD/eMMC
2x DUART / 8x I2C
2x CAN-FD
SPI, GPIO, JTAG
2x USB3.0 + PHY
Wire Rate IO Processor
2MB Packet Buffer
SERDES 24 lanes @ up to 25GHz
10/25/40/50/100 Ethernet MACs
L2 Switching
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
1MB Banked L2
ARM
A72
ARM
A72
COMPANY PUBLIC 33
Layerscape in Automotive
• Highest CPU and IO performance SoCs in NXP
• Scalability – 1-16 ARM core SoCs
• Quality & Longevity – Best quality available in high
performance processing. Many devices already on 15
year longevity program.
• Safety – We’ve demonstrated safety for mil/aero and
other critical infrastructure applications. Working to prove
ASIL-B equivalence with auto-centric collateral (FMEDA,
Safety Manual).
• Security – Secure Boot, Secure Debug, Hardware
Enforced Partitioning & Virtualization
• Software – SDKs with a very PC-like look & feel. Broad
support in Linux, history of working with WindRiver, GHS,
and QNX.