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CMOS VLSI Design 4th Ed.0: Introduction 2
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration(VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication Rest of the course: How to build a good CMOS chip
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CMOS VLSI Design 4th Ed.0: Introduction 3
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
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CMOS VLSI Design 4th Ed.0: Introduction 4
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
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CMOS VLSI Design 4th Ed.0: Introduction 5
p-n Junctions
A junction between p-type and n-type semiconductorforms a diode.
Current flows only in one direction
p-type n-type
anode cathode
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CMOS VLSI Design 4th Ed.0: Introduction 6
nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS)capacitor
Even though gate is
no longer made of metal*
* Metal gates are returning today!
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+Body
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CMOS VLSI Design 4th Ed.0: Introduction 7
nMOS Operation
Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+D
0
S
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nMOS Operation Cont.
When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type Now current can flow through n-type silicon fromsource through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO
2
Polysilicon
n+D
1
S
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CMOS VLSI Design 4th Ed.0: Introduction 9
pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
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CMOS VLSI Design 4th Ed.0: Introduction 10
Power Supply Voltage
GND = 0 V
,QV9DD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors Lower VDD saves power
VDD
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CMOS VLSI Design 4th Ed.0: Introduction 11
Transistors as Switches
We can view MOS transistors as electricallycontrolled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFFON
ONOFF
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CMOS VLSI Design 4th Ed.0: Introduction 12
0
VDD
A Y
GND
CMOS Inverter
A Y
0 1
1 0
A Y
OFF
ON1
ON
OFF
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CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
OFFOFF
ON
ON
1
1
OFFON
OFF
ON
0
1
ONOFF
ON
OFF
1
0
ONON
OFF
OFF
0
0A
B
Y
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CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
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3-input NAND Gate
Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
A
B
Y
C
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CMOS Fabrication
CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press
On each step, different materials are deposited oretched
Easiest to understand by viewing both top andcross-section of wafer in a simplified manufacturingprocess
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Inverter Cross-section
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
n+
p substrate
p+
n well
A
Y
GND VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
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Well and Substrate Taps
Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
YGND V
DD
n+p+
substrate tapwell
tap
n+ p+
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Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND VDD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
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Detailed Mask Views
Six masks n-well
Polysilicon
n+ diffusion p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
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Fabrication
Chips are built in huge factories called fabs Contain clean rooms as large as football fields
Courtesy of InternationalBusiness Machines Corporation.Unauthorized use not permitted.
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Fabrication Steps
Start with blank wafer Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2
(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2
p substrate
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Oxidation
Grow SiO2 on top of Si wafer 900 1200 C with H2O or O2 in oxidation furnace
p substrate
SiO2
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Photoresist
Spin on photoresist Photoresist is a light-sensitive organic polymer
Softens where exposed to light
p substrate
SiO2
Photoresist
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Lithography
Expose photoresist through n-well mask Strip off exposed photoresist
p substrate
SiO2
Photoresist
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Etch
Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
p substrate
SiO2
Photoresist
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Strip Photoresist
Strip off remaining photoresist Use mixture of acids called piranah etch
1HFHVVDU\VRUHVLVWGRHVQWPHOWLQQH[WVWHS
p substrate
SiO2
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n-well
n-well is formed with diffusion or ion implantation Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
n well
SiO2
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Strip Oxide
Strip off the remaining oxide using HF Back to bare wafer with n-well
Subsequent steps involve similar series of steps
p substrate
n well
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Polysilicon
Deposit very thin layer of gate oxide < 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substraten well
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Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
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Self-Aligned Process
Use oxide and masking to expose where n+ dopantsshould be diffused or implanted
N-diffusion forms nMOS source, drain, and n-wellcontact
p substraten well
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N-diffusion
Pattern oxide and form n+ regions Self-aligned processwhere gate blocks diffusion
Polysilicon is better than metal for self-aligned gatesEHFDXVHLWGRHVQWPHOWGXULQJODWHUSURFHVVLQJ
p substraten well
n+ Diffusion
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N-diffusion cont.
Historically dopants were diffused Usually ion implantation today
But regions are still called diffusion
n wellp substrate
n+n+ n+
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N-diffusion cont.
Strip off oxide to complete patterning step
n wellp substrate
n+n+ n+
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P-Diffusion
Similar set of steps form p+ diffusion regions forpMOS source and drain and substrate contact
p+ Diffusion
p substraten well
n+n+ n+p+p+p+
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Contacts
Now we need to wire together the devices Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+n+ n+p+p+p+
Contact
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Metalization
Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
p substrate
MetalThick field oxide
n well
n+n+ n+p+p+p+
Metal
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Layout
Chips are specified with set of masks Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f= distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing designrules
Express rules in terms ofO = f/2
E.g. O = 0.3 Pm in 0.6 Pm process
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Simplified Design Rules
Conservative rules to get you started
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4th Ed.
0: Introduction 41
Inverter Layout
Transistor dimensions specified as Width / Length Minimum size is 4O / 2Osometimes called 1 unit
In f= 0.6 Pm process, this is 1.2 Pm wide, 0.6 Pmlong
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CMOS VLSI D i
4th Ed.
0 I d i 2
Summary
MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to startdesigning schematics and layout for a simple chip!