Week3 1
Overview of Microprocessors
Lecturer: Sri ParameswaranNotes by : Annie Guo
Week3 2
Lecture overview
Introduction to microprocessorsInstruction set architectureTypical commercial microprocessors
Week3 3
Microprocessors
A microprocessor is a CPU on a single chip.If a microprocessor, its associated support circuitry, memory and peripheral I/O components are implemented on a single chip, it is a microcontroller.
We use AVR microcontroller as the example in our course study
Week3 4
Microprocessor types
Microprocessors can be characterized based on
the word size8 bit, 16 bit, 32 bit, etc. processors
Instruction set structureRISC (Reduced Instruction Set Computer), CISC (Complex Instruction Set Computer)
FunctionsGeneral purpose, special purpose such image processing, floating point calculations
And more …
Week3 5
Typical microprocessorsMost commonly used
68KMotorola
x86Intel
IA-64Intel
MIPSMicroprocessor without interlocked pipeline stages
ARMAdvanced RISC Machine
PowerPCApple-IBM-Motorola alliance
Atmel AVRA brief summary will be given later
Week3 6
Microprocessor applicationsA microprocessor application system can be abstracted in a three-level architecture
ISA is the interface between hardware and software
Software
Hardware
Hardware
C program
ISA level
ISA program executedby hardware
FORTRAN 90program
FORTRAN 90program compiledto ISA program
C programcompiledto ISA program
Week3 7
ISA
Stands for Instruction Set ArchitectureProvides functional specifications for software programmers to use/program hardware to perform certain tasksProvides the functional requirements for hardware designers so that their hardware design (called micro-architectures) can execute software programs.
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What makes an ISA
ISA specifies all aspects of a computer architecture visible to a programmer
BasicInstructions
Instruction format Addressing modes
Native data typesRegistersMemory models
advancedInterrupt handling
To be covered in the later lectures
Week3 9
Instructions
This is the key part of an ISAspecifies the basic operations available to a programmerExample:
Arithmetic instructions
Instruction set is machine oriented Different machine, different instruction set
For example68K has more comprehensive instruction set than ARM
Week3 10
Instructions (cont.)
Instruction set is machine oriented Same operation, could be written differently in different machine
AVRAddition: add r2, r1 ;r2 r2+r1Branching: breq 6 ;branch if equal condition is trueLoad: ldi r30, $F0 ;r30 Mem[F0]
68K:Addition: add d1,d2 ;d2 d2+d1Branching: breq 6 ;branch if equal condition is trueLoad: mov #1234, D3 ;d2 1234
Week3 11
Instructions (cont.)
Instructions can be written in two languagesMachine language
made of binary digitsUsed by machines
Assembly languagea textual representation of machine languageEasier to understand than machine language Used by human beings
Week3 12
Machine code vs. assembly code
There is a one-to-one mapping between the machine code and assembly code
Example (Atmel AVR instruction):For increment register 16:
1001010100000011 (machine code)inc r16 (assembly language)
Assembly language also includes directives Instructions to the assemblerExample:
.def temp = r16
.include “mega64def.inc”
Week3 13
Data typesThe basic capability of using different classes of values. Typical data types
Numbers Integers of different lengths (8, 16, 32, 64 bits)
Possibly signed or unsignedCommonly available
Floating point numbers, e.g. 32 bits (single precision) or 64 bits (double precision)
Available in some processors such as PowerPCBCD (binary coded decimal) numbers
Available in some processors, such as 68KNon-numeric
Boolean Characters
Week3 14
Data types (cont.)Different machines support different data types in hardware
e.g. Pentium II:
e.g. Atmel AVR:
Data Type 8 bits 16 bits 32 bits 64 bits 128 bitsSigned integerUnsigned integerBCD integer
Floating point
Data Type 8 bits 16 bits 32 bits 64 bits 128 bitsSigned integerUnsigned integerBCD integerFloating point
Week3 15
Registers
Two typesGeneral purposeSpecial purpose
Used for special functionse.g.
Program Counter (PC)Status RegisterStack pointer (SP)Input/Output Registers
Stack pointer and Input/Output Registers will be discussed in detail later.
Week3 16
General Purpose RegistersA set of registers in the machine
Used for storing temporary data/resultsFor example
In (68K) instruction add d3, d5, operands are stored in general registers d3 and d5, and the result are stored in d5.
Can be structured differently in different machinesFor example
Separated general purpose registers for data and address68K
Different numbers registers and different size of each registers
32 32-bit in MIPS16 32-bit in ARM
Week3 17
Program counter
Special registerFor storing memory address of currently executed instruction
Can be of different sizeE.g. 16 bit, 32 bit
Can be auto-incremented By the instruction word sizeGives rise the name “counter”
Week3 18
Status register
Contains a number of bits with each bit associated with CPU operations Typical status bits
V: OverflowC: CarryZ: ZeroN: Negative
Used for controlling program execution flow
Week3 19
Memory modelsData processed by CPU is usually large and cannot be held in the registers at the same time. Both data and program code need to be stored in memory.Memory model is related to how memory is used to store dataIssues
Addressable unit sizeAddress spacesEndiannessAlignment
Week3 20
Addressable unit size
Memory has units, each of which has an addressMost common unit size is 8 bits (1 byte)Modern processors have multiple-byte unit
For example:32-bit instruction memory in MIPs16-bit Instruction memory in AVR
Week3 21
Address spaces
The range of addresses a processor can access.
The address space can be one or more than one in a processor. For example
Princeton architecture or Von Neumann architectureA single linear address space for both instructions and data memory
Harvard architectureSeparate address spaces for instructions and data memories
Week3 22
Address spaces (cont.)
Address space is not necessarily just for memories
E.g, all general purpose registers and I/O registers can be accessed through memory addresses in AVR
Address space is limited by the width of the address bus.
The bus width: the number of bits the address is represented
Week3 23
EndiannessMemory objects
Memory objects are basic entities that can be accessed as a function of the address and the length
E.g. bytes, words, longwordsFor large objects (>byte), there are two ordering conventions
Little endian – little end (least significant byte) stored first (at lowest address)
Intel microprocessors (Pentium etc)Big endian – big end stored first
SPARC, Motorola microprocessors
Week3 24
Endianness (cont.)
Most CPUs produced since ~1992 are “bi-endian” (support both)
some switchable at boot timeothers at run time (i.e. can change dynamically)
Week3 25
Big Endian & Little Endian
Example: 0x12345678—a long word of 4 bytes. It is stored in the memory at address 0x00000100
big endian:
little endian:
Address data0x00000100 120x00000101 340x00000102 560x00000103 78
Address data0x00000100 780x00000101 560x00000102 340x00000103 12
Week3 26
Alignment
Often multiple bytes can be fetched from memory Alignment specifies how the (beginning) address of a multiple-byte data is determined.
data must be aligned in some way. For example4-byte words starting at addresses 0,4,8, …8-byte words starting at addresses 0, 8, 16, …
Alignment makes memory data accessing more efficient
Week3 27
Example
A hardware design that has data fetched from memory every 4 bytes
Fetching an unaligned data (as shown) means to access memory twice.
Week3 28
Instruction format
Is a definitionhow instructions are represented in binary code
Instructions typically consist ofOpcode (Operation Code)
defines the operation (e.g. addition)Operands
what’s being operated on
Instructions typically have 0, 1, 2 or 3 operands
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Instruction format examples
OpCode OpCode
OpCodeOpCode Opd1Opd2Opd1
Opd
Opd2 Opd3
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Example (AVR instruction)Subtraction with carry
Syntax: sbc Rd, RrOperation: Rd ← Rd – Rr – CRd: Destination register. 0 ≤ d ≤ 31Rr: Source register. 0 ≤ r ≤ 31, C: Carry
Instruction format
OpCode uses 6 bits (bit 9 to bit 15).Two operands share the remaining 10 bits.
0 0 0 0 1 0 r d r r r rd d d d015
Week3 31
Instruction lengths
The number of bits an instruction hasFor some machines – instructions all have the same length
E.g. MIPS machinesFor other machines – instructions can have different lengths
E.g. M68K machine
Week3 32
Instruction encodingOperation Encoding
2n operations needs at least n bitsOperand Encoding
Depends on the addressing modes and access space.
For example: An operand in direct register addressing mode requires at most 3 bits if the the number of registers it can be stored is 8.
With a fixed instruction length, more encoding of operations means less available bits for encoding operands
Tradeoffs should be concerned
Week3 33
Example 1A machine has:
16 bit instructions16 registers (i.e. 4-bit register addresses)
Instructions could be formatted like this:
Maximally 16 operations can be defined.But what if we need more instructions and some instructions only operate on 0, 1 or 2 registers?
OpCode Operand1 Operand2 Operand3
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Example 2
For a 16 bit instruction machine with 16 registers, design OpCodes that allow for
14 3-operand instructions30 2-operand instructions30 1-operand instructions32 0-operand instructions
Week3 35
Addressing modesInstructions need to specify where to get operands fromSome possibilities
Values are in the instructionValues are in the register
Register number is in the instructionValues are in memory
address is in instructionaddress is in a register
register number is in the instructionaddress is register value plus some offset
register number is in the instructionoffset is in the instruction (or in a register)
These ways of specifying the operand locations are called addressing modes
Week3 36
Immediate Addressing
The operand is from the instruction itselfI.e the operand is immediately available from the instruction
For example, in 68K
Perform d7 99 + d7; value 99 comes from the instructiond7 is a register
addw #99, d7
Week3 37
Register Direct Addressing
Data from a register and the register number is directly given by the instructionFor example, in 68K
Perform d7 d7 + d0; add value in d0 to value in d7 and store result to d7d0 and d7 are registers
addw d0,d7
Week3 38
Memory direct addressing
The data is from memory, the memory address is directly given by the instructionWe use notion: (addr) to represent memory value with a given address, addrFor example, in 68K
Perform d7 d7 + (0x123A); add value in memory location 0x123A to register d7
addw 0x123A, d7
Week3 39
Memory Register Indirect Addressing
The data is from memory, the memory address is given by a register and the register number is directly given by the instructionFor example, in 68K
Perform d7 d7 + (a0); add value in memory with the address stored in register a0, to register d7
For example, if a0 = 100 and (100) = 123, then this adds 123 to d7
addw (a0),d7
Week3 40
Memory Register Indirect Auto-increment
The data is from memory, the memory address is given by a register, which is directly given by the instruction; and the value of the register is automatically increased – to point to the next memory object.
Think about i++ in CFor example, in 68K
d7 d7 + (a0); a0 a0 + 2
addw (a0)+,d7
Week3 41
Memory Register Indirect Auto-decrement
The data is from memory, the memory address is given by a register and the register number is directly given by the instruction; but the value of the register is automatically decreased before such an operation.
Think --i in CFor example, in 68K
a0 a0 –2; d7 d7 + (a0);
addw -(a0),d7
Week3 42
Memory Register Indirect with Displacement
Data is from the memory with the address given by the register plus a constant
Used in the access of a member in a data structure
For example, in 68K
d7 (a0+8) +d7
addw a0@(8), d7
Week3 43
Address Register Indirect with Index and displacement
The address of the data is sum of the initial address and the index address as compared to the initial address plus a constant
Used in accessing element of an arrayFor example, in 68K
d7 (a0 + d3+8)With a0 as an initial address and d3 as an index dynamically pointing to different elements, plus a constant for a certain member in an array element.
addw a0@(d3)8, d7
Week3 44
RISC
RICS stands for reduced instruction set computer
Smaller and simpler set of instructionsSmaller: small number of instructions in the instruction setSimpler: instruction encoding is simple
Such as fixed instruction length
All instructions take about the same amount of time to execute
Week3 45
CISC
CISC stands for complex instruction set computer
Each instructions can execute several low-level operations
Such operations of load memory, arithmetic and store memory in one instructionsRequired complicated hardware support
All instructions take different amount of time to execute
Week3 46
Recall: Typical processorsMost commonly implemented in hardware
68KMotorola
x86Intel
IA-64Intel
MIPSMicroprocessor without interlocked pipeline stages
ARMAdvanced RISC Machine
PowerPCApple-IBM-Motorola alliance
Atmel AVR
Week3 47
X86CISC architecture
16 bit 32-bit 64-bitWords are stored in the little endian orderAllow unaligned memory access.Current x86-processors employs a few “extra”decoding steps to (during execution) split (most) x86 instructions into smaller pieces (micro-instructions) which are then readily executed by a RISC-like micro-architecture.Application areas (dominant)
Desktop, portable computer, small servers
Week3 48
68K
CISC processorEarly generation, hybrid 8/16/32 bit chip (8-bit bus)Late generation, fully 32-bitSeparate data registers and address registersBig endian
Area applicationsEarly used in for calculators, control systems, desktop computersLater used in microcontroller/embedded microprocessors.
Week3 49
MIPSRISC processor
A large family designs with different configurationsDeep pipeline (>=5 stages)
With additional featuresClean instruction setCould be booted either big-endian or little-endian
Many application areas, including embedded systemsThe design of the MIPS CPU family, together with SPARC, another early RISC architecture, greatly influenced later RISC designs
Week3 50
ARM32-bit RISC processor
Three-address architectureNo support for misaligned memory accesses16 x 32 bit register fileFixed opcode width of 32 bit to ease decoding and pipelining, at the cost of decreased code densityMostly single-cycle execution
With additional featuresConditional execution of most instructions
reducing branch overhead and compensating for the lack of a branch predictorPowerful indexed addressing modes
Power saving
Week3 51
PowerPC
Superscalar RISC32-bit, 64-bit implementationWith both big-endian and little endian modes, can switch from one mode to the other at run-time. Intended for high performance PC, for high-end machines
Week3 52
Reading Material
Chap.2 in Microcontrollers and Microcomputers.
Week3 53
Questions
1. Given an address bus width in a processor as 16-bit, determine the maximal address space.
2. Assume a memory address is 0xFFFF, how many locations this address can represent if the related computer is?
I) a Harvard machineII) a Von Neumann machine