[M2] Traffic Control
Group 2Chun Han ChenTimothy Kwan
Tom BoldsShang Yi Lin
ManagerRandal HongWed. Sep 22
Overall Project Objective :
Dynamic Control The Traffic Lights
Status
Design Proposal Chip Architecture Behavioral Verilog Implementation Size estimates/ floorplanning Behavioral Verilog simulated Gate Level Design Component Layout/Simulation Chip Layout Complete Simulation
Traffic Flows
Sensors (Blue)To detect the car entered
Sensors (Red)To detect the car leaved
Traffic Light Flow
Whenever pedestrian push the button, then this light will insert in the end of this cycle.
ARM 1
ARM 2
Red
Green Y
Green (Straight + Right) Y Red+Green(Left)
Red
Y Red
Green (Straight + Right) Y Red+Green(Left) Y
Phase A
Phase C
Phase B Phase A Phase BARM1 ARM1 ARM2 ARM2
PED
We define three phases (A,B,C) for different operations.
SW – Switch light
G – Green
R – Red
Y – Yellow
T – Time for Yellow
PED – Pedestrian
SW (1bit)
ARM (1bit)
PED(1bit)
T (2bits)
Phase(2bits)FSM
Initial
G.R
Y.R
R+Left.R
Y.R
R.G
R.Y
R.Y
R.R+Left
PED
SW = 0 SW =0
SW = 1 SW = 1
T < 2 T < 2
T = 2 T = 2
SW = 1 SW = 1
SW =0
SW = 0
PED = 1
T = 2
PED = 1
T = 2
T<= 2 T<= 2
SW = 0
SW = 1
T = 2
PED = 0
T = 2
PED = 0
ARM = 0 ARM = 1
Init. Ped = 0Choose the Phase
Hold until n1 or n2 changes
Light favorsn1 or n2 ?
n1 n2
T<r1? T<r2?
T>= R1?
T>= R2?
n1=0?
n2=0?
f1<=0?
f2<=0?
Switch Light
ResetT = 0
No
Yes
Yes Yes
YesYes
Yes YesNoNo
No
No No
No
Yes
No
Light favorsarm1 or arm2 ?
n1 n2
T<rleft? T<rleft?
T>= Rleft? T>= Rleft?
No
Yes
Yes Yes
YesYesNo
No
Yes
Non1 not change in T = 5?
No
No
Control
reset Pedestrian For Green light
For Red + Left
T>= Rp ?
Yes
No
For Pedestrian
n2 not change in T = 5?
n1, n2 :# of carsT :Time spent in this phaseRi , ri : Max. and Min. time for each phasefi : the control functionf1 = α1*n1+ β1 – n2 f2 = α2*n2+ β2 – n1
Adder
Subtractor
Register
(Total Number)
AdderAdder
N2
F
Accumulator Alpha
&
BetaAccumulator
Arm 1
Arm 2
Compute N2, α2 and β2
Ni = Number of cars queuedF1(t) = α1N1(t) + β1 – N2(t) F2(t) = α2N2(t) + β2 – N1(t) T = time elapsed since last change of phaser , R = minimum, maximum allowable durations of phase for arm_i
FUNCTION BLOCK
Initialize & User Inputs
Comparator FSM Switch
CounterTime Clock
Pedestrian
Register
Provide comparator some values, such as r, R, T, α,β, N1 and N2.
Compute N1
Compute β
Inputs and Initialized
T
Reset T=0
Decide when to switch
Floating Point Representation
12 bit representation1 bit – sign4 bit – excess-7 exponent with radix 27 bit – Significand/Mantissa
Addition & SubtractionAlign decimal places
Shifting Mantissa, alter exponent if neededAdd
Add MantissasNormalize resultSubtraction
Align decimal placesSubtract by altering input signals to reuse
adderNormalize
Multiplication
Multiply MantissasAdd True Exponents
Unbias both exponents to get trueRe-bias exponentNormalize result
Division
Using the Newton Raphson approximationGiven
f(x) = D – 1/X Xn+1 = Xn(2-D*Xn)X1 = reciprocal of D
Plan to use ~20 iterationsX1 will be obtained via a look up table based
on the exponent of the D
Design Decisions
Removal of Division and Subtraction block from transitor CountIncreased amounts of Demux/Mux
into multiply and adder blockInsertion of ROM for lookup table
`define FP_ADD 2'd0`define FP_SUB 2'd1`define FP_MULT 2'd2`define NAN (32'hFFFFFFFF)module FPU (Y, A, B, SEL, Valid);`include "fpu_tasks.v“ output [31:0] Y; input [31:0] A,B; input [1:0] SEL; output Valid; reg [31:0] Y; reg Valid; reg [7:0] expA, expB, expY; reg [26:0] sigA, sigB; reg [27:0] sigY; reg signA, signB, signY; reg overflow, underflow; reg diff_sign,exp_ovf,sticky; reg [47:0] mtmp; reg [7:0] i; reg [5:0] leading_zs; reg [6:0] leading_mzs; reg exp0;
always @(A or B or SEL) beginsigA = 0;sigB = 0;underflow = 0;overflow = 0;sticky=0;{signA, expA, sigA[25:3]} = A[31:0];{signB, expB, sigB[25:3]} = B[31:0];sigA[26] = ( A[30:0] != 0 );sigB[26] = ( B[30:0] != 0 );diff_sign = signA ^ signB;
{signY,sigY,expY} = 0;leading_zs = 0;leading_mzs = 0;i = 0;mtmp = 0;exp0 = 0;
casex (SEL)
// Case of FP_ADD, FP_SUB2'b0?: begin
/*****************************//* Handle Some special cases *//*****************************/signB = (SEL == `FP_SUB) ? ~signB : signB;if (expA == 8'hFF || expB == 8'hFF) begin
if (expA == 8'hFF && A[22:0] != 0){signY,expY,sigY[25:3]} = `NAN;
else if (expB == 8'hFF && B[22:0] != 0){signY,expY,sigY[25:3]} = `NAN;
else if (expA == 8'hFF && expB != 8'hFF ){signY,expY,sigY[25:3]} = A;
else if (expA != 8'hFF && expB == 8'hFF ){signY,expY,sigY[25:3]} = {signB, B[30:0]};
else if (A == B ){signY,expY,sigY[25:3]} = A;
else{signY,expY,sigY[25:3]} = `NAN;
endelse begin
/**********************************//* Correct for Addition overflow *//**********************************/if ( !diff_sign && sigY[27] ) begin
sticky = sigY[0];sigY = sigY >> 1;sigY[0] = sticky | sigY[0];if (expY >= 254)
overflow = 1;expY = expY+1;
endelse if (diff_sign) begin
/*Right shifting for exponent adjustment*/LeadingZeros_27(sigY[26:0],leading_zs);if (leading_zs < 27 && (expY > leading_zs) ) begin
sigY = sigY << leading_zs;expY = expY - leading_zs;
endelse if (leading_zs < 27 && (expY <= leading_zs)) begin
expY = 0;sigY = sigY << expY;
endend
/*********************************//* Do the complicated Arithmetic *//*********************************/diff_sign = signA ^ signB;i = (expA - expB);
/* If B is has a smaller exponent, right shift align it */if (i == 0) begin
sigB = sigB; sigA = sigA; expA = expA; expB = expB;
end else if (i[7] == 0 || expB==0) begingetSticky_27(sigB, i[4:0], sticky);sigB = sigB >> i[4:0];expB = expB + i[4:0];
end /*If A has the smaller exponent, right shift align it */else if (i[7] == 1 || expA==0) begin
i = ~i+1;getSticky_27(sigA, i[4:0], sticky);sigA = sigA >> i[4:0];expA = expA + i[4:0];
endexpY = expA;/* Do the Addition/Subtraction */if (!diff_sign)
sigY = {1'b0,sigA} + {1'b0,sigB};else if (signA)
sigY = {1'b1,~sigA} + {1'b0,sigB} + 1;else
sigY = {1'b0,sigA} + {1'b1,~sigB} + 1;/* Set the final sign bit */if (diff_sign)
signY = sigY[27];else
signY = signA;
/* Make positive again if needed */if (sigY[27] && diff_sign)
sigY = ~sigY + 1;else
sigY = sigY;
if(sigY==0) /* Zero Result */expY=0;
else expY = expY;
/************************//* Round the numbers *//************************/if (!sigY[2]) begin /* Truncate */
{sigY,expY} = {sigY,expY};end else if (sigY[2] && (|sigY[1:0])) begin /* Round Up */
sigY[27:3] = sigY[27:3] + 1;if (sigY[27]) begin
if (expY == 254)overflow = 1;sigY = sigY >> 1;expY = expY + 1;
endend else begin // If guard bits are 100.
if (sigY[3]) beginsigY[27:3] = sigY[27:3] + 1;
if (sigY[27]) beginif (expY >= 254)
overflow = 1;sigY = sigY >> 1;expY = expY + 1;
endend else begin
{expY,sigY} = {expY,sigY};// $display("Round Down on 100");
endend
if (overflow) begin /* If overflow, go to Infinity */expY = 8'hFF;sigY = 0;
end else if (sigY == 0) /* If zero, zero out Exponent */expY = 0;
end /* finished Complicated Arithmetic */end /* End of Add/Sub Case */`FP_MULT: beginsignY = diff_sign;exp0 = ((expA == 8'h7f) || (expB == 8'h7f));expY = expA + expB + 8'h81;
if (exp0){overflow,underflow} = 0;
else beginoverflow = expA[7] && expB[7] && (!expY[7]) && (expY != 8'h7f);underflow = !expA[7] && !expB[7] && expY[7];
end// mtmp = sigA[26:3] * sigB[26:3];mult_24(sigA[26:3], sigB[26:3], mtmp);
if (mtmp[47]) beginif (expY >= 254)
overflow = 1;expY = expY + 1;mtmp = mtmp >> 1;
endLeadingZeros_47(mtmp[46:0], leading_mzs);if (leading_mzs < 47 && (expY > leading_mzs) ) beginmtmp = mtmp << leading_mzs;expY = expY - leading_mzs;
endelse if (leading_mzs < 47 && (expY <= leading_mzs)) begin
expY = 0;mtmp = mtmp << expY;
endsigY[27:3] = (!mtmp[22:0]) ? mtmp[46:23] : mtmp[46:23]+1;if (sigY[27]) begin
if (expY >= 254)overflow = 1;
expY = expY + 1;sigY = sigY >> 1;
endif (overflow) begin /* Set to infty */
expY = 8'hFF;sigY = 0;
endelse if (underflow) begin /* Set to Zero */
expY = 0;sigY = 0;
end/* If Zero happened then make zero */else if (sigY == 0)
expY = 0;if ({expY,sigY} == 0)
signY = 0;/* In these special Cases */if (expA == 8'hFF || expB == 8'hFF) begin
if (expA == 8'hFF && A[22:0] != 0){signY,expY,sigY[25:3]} = `NAN;
else if (expB == 8'hFF && B[22:0] != 0){signY,expY,sigY[25:3]} = `NAN;
else if (expA == 8'hFF && expB != 8'hFF ){signY,expY,sigY[25:3]} = A;
else if (expA != 8'hFF && expB == 8'hFF ){signY,expY,sigY[25:3]} = {signB, B[30:0]};
else if (A == B ){signY,expY,sigY[25:3]} = A;
else{signY,expY,sigY[25:3]} = `NAN;
endendendcaseY = {signY, expY, sigY[25:3]};End endmodule
`define FP_ONE_VAL (32'h3f800000) `define FP_TWO_VAL (32'h40000000) `define FP_PI_VAL (32'h403a7efa)`include "fpu.v"`include "LookupTable.v"
Verilog Behavioral Modeling - FP Divider (portion)
module Divide(N, D, Q, clk, DONE, START);
output reg [31:0] Q; input [31:0] N, D;input clk, START; output reg DONE;
wire [31:0] X1, Y1; wire [31:0] Q_reg, Q_regt;
reg [2:0] state, nstate; reg [31:0] D_reg, N_reg; /* FPU mult(Y1, `FP_TWO_VAL, D_reg, 2'd2, Valid); FPU sub(X1, `FP_PI_VAL, Y1, 2'd1, valid2); arrayDblock3 af(X1, D_reg, Q_regt); FPU sdz(Q_reg, Q_regt, N_reg, 2'd2, valid3); */ LookupTable blah(D_reg[30:23], X1); arrayDblock af(X1, D_reg, Q_regt); FPU sdz(Q_reg, Q_regt, N_reg, 2'd2, valid3); always @ (*) begin case(state) 0: nstate = 1; 1: nstate = 2; 2: nstate = 2; endcase end
always @ (posedge clk) begin if(START == 1) begin state <= 0; D_reg <= D; N_reg <= N; DONE <= 0; end else if(state == 1)begin DONE <=1; Q <= Q_reg; state <= nstate; end else begin state <= nstate; DONE <= 0; end end endmodule module Dblock(X, D, X2); input [31:0] X; input [31:0] D; output [31:0] X2; wire [31:0] T1, T2; FPU a(T1, D, X, 2'd2, valid1); FPU b(T2, `FP_TWO_VAL, T1, 2'd1, valid2); FPU c(X2, X, T2, 2'd2, valid3); endmodule
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Verilog Behavioral Modeling - FP Divider (portion) Cont.
'define TRUE 1'b1;'define FALSE 1'b0;'define Y2RDELAY 2;'define PEDDELAY 15; module sig_control (arm1, arm2, ped, arm, SW, PEDESTRIAN, clear, clk); output [1:0] arm1, arm2;output ped; reg [1:0] arm1, arm2;reg ped;input arm;input SW, PEDESTRIAN;input clk, clear; parameter RED = 3'd0; Yellow = 3'd1; GREEN = 3'd2; LEFT = 3'd3; PED_OFF = 3'd4; PED_ON = 3'd5; parameter S0 = 4'd0; //initial S1 = 4'd1; // G R S2 - 4'd2; // Y R S3 = 4'd2; // R+left R S4 = 4'd2; // Y R S5 = 4'd2; // R G S6 = 4'd3; // R Y S7 = 4'd3; // R R+left S8 = 4'd3; // R Y S9 = 4'd3; // Ped reg [3:0] state;reg [3:0] next_state; always @(positive clock) if(clear) state <= S0; else state <= next_state;
always @(state)begin arm1 = RED; arm2 = RED; ped = PED_OFF; case(state) S0: ; S1: begin arm1 = GREEN; arm2 = RED; end S2: arm1 = YELLOW; S3: arm1 = LEFT; S4: arm1 = YELLOW; S5: begin arm1 = RED; arm2 = GREEN; end S6: arm2 = YELLOW; S7: arm2 = LEFT; S8: arm2 = YELLOW; S9: begin arm1 = RED; arm2 = RED; ped = PED_ON; end endcaseend always @(state or SW)begin case (state) S0: if(arm) next_state = S5; else next_state = S1; S1: if(SW) next_state = S2; else next_state = S1;
S2: begin repeat('Y2RDELAY) @(posedge clk); next_state = S3; end S3: if(SW) next_state = S4; else next_state = S3; S4: begin repeat('Y2RDELAY) @(posedge clk); if(PEDESTRIAN) next_state = S9; else next_state = S5; end S5: if(SW) next_state = S6; else next_state = S5; S6: begin repeat('Y2RDELAY) @(posedge clk); next_state = S7; end S7: if(SW) next_state = S8; else next_state = S7; S8: begin repeat('Y2RDELAY) @(posedge clk); if(PEDESTRIAN) next_state = S9; else next_state = S1; end S9: begin repeat('PEDDELAY) @(posedge clk); next_state = S0; end default: next_state = S0; endcaseend
Verilog Behavior Modeling - Light Switching FSM
Issues
Other way to get X1?Linear Approximation (2.914-2*D)
Goldshmidt Division AlgorithmMuxzilla
Reuse of Adders + Multipliers