HI-6220 Rev. B
HI-6220MIL-STD-1553 BC/RT/MT
with Integrated Transformers
May 2019
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Overview
1. OverviewThe HI-6220PB family is a fully integrated and dual redundant MIL-STD-1553 BC/RT/MT interface solution which includes 1553 protocol, SRAM, dual transceivers and dual isolation transformers in a single BGA package. The device is a direct pin compatible drop-in replacement for the Data Device Corporation (DDC®) Total-ACE® Family of MIL-STD-1553 Terminals.
1.1. Bus Controller
The BC is a programmable message-sequencing engine programmed using a set of 20 instruction op codes. It greatly reduces the host’s processing workload by autonomously supporting multi-frame message scheduling, message retry schemes, storage of message data in on-chip RAM, asynchronous message insertion and status/error reporting. The Enhanced BC mode also includes a General Purpose Queue and user-defined interrupts to further enhance host communication.
1.2. Remote Terminal
The HI-6220PB RT has been fully validated by a recognized independent third party. RT memory management options include single, double, and 2 circular buffer modes for individual subaddresses. The RT performs comprehensive error checking including word and format validation and checks for various transfer errors. The RT supports flexible interrupt conditions, command illegalization and a programmable busy bit by subaddress. In addition, the device has an “auto-boot” feature necessary for MIL-STD-1760 compliance, whereby the terminal can initialize as an online RT with the busy bit set following power turn-on.
1.2.1. Simple System Remote Terminal (SSRT) ModeThe HI-6220PB may be operated in a simplified RT mode called Simple System Remote Terminal (SSRT) mode. The SSRT mode provides a low-cost MIL-STD-1553 Remote Terminal interface for a simple system that doesn’t include a microprocessor, such as A/D and D/A converters, actuators, and other discrete I/O signals. SSRT mode is activated by strapping three balls to ground.
1.3. Monitor Terminal
The HI-6220PB family supports three monitor modes including a word monitor mode, a selective message monitor mode and a combined RT/Monitor Mode. For new applications it is recommended to implement the selective message monitor mode. Selective Message Monitor allows monitoring of 1553 messages and provides the ability to filter based on RT address, T/R bit and subaddress with no host processor intervention.
1.4. Host Processor Interface
Each device provides an 8/16-bit parallel host bus interface supporting a variety of processor configurations including shared RAM and DMA configurations. The host interface supports both non-multiplexed and multiplexed address/data buses, non-zero wait mode for interfacing to processor address/data buses, and zero wait mode for interfacing to microcontroller I/O ports.
Note: DDC®, Mini-ACE®, Enhanced Mini-ACE®, Micro-ACE®, Mini-ACE® Mark3 and Total-ACE® are registered trademarks of Data Device Corporation, Bohemia, NY, USA. There is no affiliation between Data Device Corporation and Holt Integrated Circuits Inc.
Overview
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1.5. Built in Test
The HI-6220PB family provides an autonomous built-in self-test capability. The testing includes both RAM and protocol logic tests which may be initiated by the host processor.
1.6. Features
● Dual Redundant MIL-STD-1553A/B/1760 Channel
● BC, RT, MT, or RT/MT Modes
● Integrated Dual Isolation Transformers
● Direct and/or Transformer Coupled
● Supports Simple System RT Mode
● 64Kx17 or 4Kx16 SRAM
● External RT Address Inputs
● MIL-STD-1760 RT “Auto Boot”
● +3.3V Single Supply
● Built-in Self-Test
● Generic 8/16-bit Processor Interface
● -40°C to +85°C or -55°C to +125°C
○ No Limitations on transmit duty cycle
● PBGA-312
○ 15.2mm x 27.9mm x 4.7mm
1.7. Application Benefits
● Simplified Board Design and Layout
● Third Party RT Validated
● Single Die for Improved Reliability
● Cost Effective Direct Drop-in Replacement for DDC® Total-ACE®
● Fully Software Compatible to DDC® ACE, Mini-ACE®, Enhanced Mini-ACE®, Micro-ACE®, Mini-ACE® Mark3 and Total-ACE®.
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Overview
1.8. Cross Reference Guide
Holt P/N DDC P/N
HI-62213PBxFBU-64843i8-xxx
BU-64843U8-xxx
HI-62213PBxBU-64843T8-xxx
BU-64843H8-xxx
HI-62203PBxFBU-64863i8-xxx
BU-64863U8-xxx
HI-62203PBxBU-64863H8-xxx
BU-64863T8-xxx
1.9. Block Diagram
TransceiverA
TransceiverB
Dual Encoder/Decoders
MIL-STD-1553BC/RT/MT Protocol
&Memory Management
InternalTransformers
SharedRAM
AddressBuffers
Host& MemoryInterface
Logic
DataBuffers Data Bus
Address Bus
D15 - D0
A15 - A0
HostData Bus
HostAddress Bus
RT Address Bus RTAD4 - RTAD0, RTADP, RTADD_LAT
Bus A
Bus B
TX_INH B
TX_INH A
Host& Memory
Control Signals
InterruptRequest
INT
MessageStatus
CLK_IN,Control & Protocol
Inputs
Registers and Command/Status Words
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2. Registers and Command/Status WordsTable 1 summarizes the device registers and corresponding addresses.
Table 1. Register Summary
Hex Address Access Register Name
Hard Reset Default
0x0000 RD/WR Interrupt Mask Register 1 0x0000
0x0001 RD/WR Configuration Register 1
0x0002 RD/WR Configuration Register 2
0x0003 WR Start/Reset Register
0x0003 RD Non-Enhanced BC or RT Command Stack Pointer / Enhanced BC Instruction List Pointer Register
0x0004 RD/WR BC Control Word / RT Subaddress Control Word Register
0x0005 RD/WR Time Tag Register
0x0006 RD Interrupt Status Register 1
0x0007 RD/WR Configuration Register 3
0x0008 RD/WR Configuration Register 4
0x0009 RD/WR Configuration Register 5
0x000A RD/WR RT/Monitor Data Stack Address Register
0x000B RD BC Frame Time Remaining Register
0x000C RD BC Time Remaining to Next Message Register
0x000D RD/WRNon-Enhanced BC Frame Time / Enhanced BC Initial Instruction Pointer / RT Last Command/MT Trigger Word Register
0x000E RD RT Status Word Register
0x000F RD RT BIT Word Register
0x0010 − Test Mode Register 0
0x0011 − Test Mode Register 1
0x0012 − Test Mode Register 2
0x0013 − Test Mode Register 3
0x0014 − Test Mode Register 4
0x0015 − Test Mode Register 5
0x0016 − Test Mode Register 6
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Registers and Command/Status Words
Hex Address Access Register Name
Hard Reset Default
0x0017 − Test Mode Register 7
0x0018 RD/WR Configuration Register 6
0x0019 RD/WR Configuration Register 7
0x001A − Reserved
0x001B RD BC Condition Code Register
0x001B WR BC General Purpose Flag Register
0x001C RD BIT Test Status Register
0x001D RD/WR Interrupt Mask Register 2
0x001E RD Interrupt Status Register 2
0x001F RD/WR BC General Purpose Queue Pointer / RT-MT Interrupt Status Queue Pointer Register
Registers and Command/Status Words
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2.1. Interrupt Mask Register #1, Read/Write 0x0000
Interrupt Mask Registers #1 is used to enable/disable interrupt requests for various operational conditions.
Bit No. R/W Reset Bit Description
15 (MSB) − 0 Reserved
14 R/W 0RAM Parity Error
Note: RAM PARITY ERROR must be set to logic “0” for 4K RAM device options, since there is no 17-bit RAM for these devices.
13 R/W 0 BC/RT Transmitter Timeout
12 R/W 0 BC/RT Command Stack Rollover
11 R/W 0 MT Command Stack Rollover
10 R/W 0 MT Data Stack Rollover
9 R/W 0 Handshake Fail
8 R/W 0 BC Retry.
7 R/W 0 RT Address Parity Error
6 R/W 0 Time Tag Rollover
5 R/W 0 RT Circular Buffer Rollover
4 R/W 0 BC Control Word/RT Subaddress Control Word EOM
3 R/W 0 BC End of Frame
2 R/W 0 Format Error
1 R/W 0 BC Status Set/RT Mode Code/MT Pattern Trigger
0 (LSB) R/W 0 End of Message
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Registers and Command/Status Words
2.2. Configuration Register #1, Read/Write 0x0001
Configuration Registers #1 is used to select the device’s mode of operation and for software control of operational attributes such as RT Status Word bits, RT Memory Management mode selection, Time-Tagging, etc. Specific bit functionality depends on the selected mode of operation. Table 2 summarizes the relevant bits for each mode.
Table 2. Configuration Register #1 Bit Summary by Mode of Operation.
BITBC FUNCTION
(Bits 11-0, Enhanced Mode Only)
RT WITHOUT ALTERNATE STATUS
RT WITH ALTERNATE STATUS
(Enhanced Mode Only)
MONITOR FUNCTION
(Bits 12-0, Enhanced Mode Only)
15 (MSB) RT/BC-MT (Logic 0) (Logic 1) (Logic 1) (Logic 0)
14 MT/BC-RT (Logic 0) (Logic 0) (Logic 0) (Logic 1)
13 Current Area B/A Current Area B/A Current Area B/A Current Area B/A
12 Message Stop-On-Error Message Monitor Enabled (MMT) Message Monitor Enabled Message Monitor
Enabled
11 Frame Stop-On-Error Dynamic Bus Control Acceptance S10 Trigger Word Enabled
10 Status Set Stop-On-Message Busy S09 Start-On-Trigger
9 Status Set Stop-On-Frame Service Request S08 Stop-On-Trigger
8 Frame Auto-Repeat SSFLAG S07 Not Used
7 External Trigger EnabledRTFLAG
(Enhanced Mode Only) S06 External Trigger Enabled
6 Internal Trigger Enabled Not Used S05 Not Used
5 Intermessage Gap Timer Enabled Not Used S04 Not Used
4 Retry Enabled Not Used S03 Not Used
3 Doubled / Single Retry Enabled Not Used S02 Not Used
2 BC Enabled (Read Only) Not Used S01Monitor Enabled
(Read Only)
1 BC Frame In Progress (Read Only) Not Used S00Monitor Triggered
(Read Only)
0 (LSB)BC Message In
Progress (Read Only)
RT Message In Progress (Enhanced mode only, Read
Only)
RT Message In Progress (Read Only)
Monitor Active (Read Only)
Notes: 1. The combined RT/Message Monitor mode uses the RT WITHOUT ALTERNATE STATUS or the RT WITH
ALTERNATE STATUS bit definitions not the MONITOR FUNCTION bit definitions.
Registers and Command/Status Words
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2. In the alternate RT Status Word mode, bit 10 (Message Error) may also be set for an illegalized message (Broad-cast-T/R bit subaddress-word count/mode code).
Modes of operation are configured using a combination of bits 15, 14 and 12 in Configuration Register #1 and bit 15 in Configuration Register #3. See Table 3 for a summary of the bit combinations.
Table 3. Modes of Operation.
Config. Reg. #1 Config. Reg. #3 ModeBit 15 Bit 14 Bit 12 Bit 15
0 0 X 0 Non-ENHANCED BC (See Notes) (no Monitor modes available)
0 0 X 1 ENHANCED BC (no Monitor modes available)
0 1 0 X Word Monitor
0 1 1 0 Word Monitor (non-ENHANCED mode set)
0 1 1 1 Message Monitor (ENHANCED mode set)
1 0 X 0 Non-ENHANCED RT (no Monitor modes available)
1 0 0 1 ENHANCED RT/Word Monitor
1 0 1 1 ENHANCED RT/Message Monitor
1 1 X X Idle
Notes: 1. Following hardware reset (MSTCLR asserted) or software reset (by means of the Start/Reset Register), BC/RT/
MT versions of the device will initialize to (non-transmitting) BC mode, while RT only versions will initialize to Idle mode. In both cases, the values of bits 15 and 14 will initialize to logic “0.”
2. Notes 2 thru 6 are only applicable to the BC/RT/MT versions of the device: If the device is switched from RT to combined RT/Monitor mode in the middle of an RT message, the message will be completed.
3. If the device is switched from combined RT/Monitor mode to RT mode in the middle of an RT message or Monitor message, the message will be completed.
4. If the device is switched from either RT mode or Monitor mode to either BC mode or “Idle” mode in the middle of an RT message, the message will be aborted.
5. If the device is switched from non-enhanced RT mode to “Idle” mode, there is no effect.
6. If the device is switched from (ENHANCED or non-ENHANCED) BC mode to “Idle” mode in the middle of a message, the message will be aborted.
7. In BC Mode ((bits [15, 14] in Configuration Register #1 set to [0, 0] respectively), bit 12 of Configuration Register #1 functions as MESSAGE STOP-ON-ERROR bit and has no affect on mode of operation.
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Registers and Command/Status Words
2.3. Configuration Register #2, Read/Write 0x0002
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Enhanced Interrupts
14 R/W 0 RAM Parity Enable
13 R/W 0 Busy Lookup Table Enable
12 R/W 0 Rx Subaddress Double Buffer Enable
11 R/W 0 Overwrite Invalid Data
10 R/W 0 256-Word Boundary Disable
9 R/W 0 Time Tag Resolution 2
8 R/W 0 Time Tag Resolution 1
7 R/W 0 Time Tag Resolution 0
6 R/W 0 Clear Time Tag on Synchronize
5 R/W 0 Load Time Tag on Synchronize
4 R/W 0 Interrupt Status Auto Clear
3 R/W 0 Level / Pulse Interrupt Request
2 R/W 0 Clear Service Request
1 R/W 0 Enhanced RT Memory Management
0 (LSB) R/W 0 Separate Broadcast Data
2.4. Command Stack Pointer Register/ Enhanced BC Instruction List Register, Read Only 0x0003
This register provides the host processor read access to the current value of the Stack Pointer for RT, MT and non-enhanced BC modes.
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Command Stack Pointer, bit 15
.
...
.
...
0 (LSB) R 0 Command Stack Pointer, bit 0
Registers and Command/Status Words
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2.5. Start/Reset Register, Write Only 0x0003
Bit No. R/W Reset Bit Description
15 (MSB) − 0 Reserved
14 − 0 Reserved
13 − 0 Reserved
12 − 0 Reserved
11 W 0 Clear RT Halt
10 W 0 Clear Self-Test Register
9 W 0 Initiate RAM Self-Test
8 W 0 Reserved
7 W 0 Initiate Protocol Self-Test
6 W 0 BC/MT Stop-On-Message
5 W 0 BC Stop-On-Frame
4 W 0 Time Tag Test Clock
3 W 0 Time Tag Reset
2 W 0 Interrupt Reset
1 W 0 BC/MT Start
0 (LSB) W 0 Reset
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Registers and Command/Status Words
2.6. BC Control Word Register, Read/Write 0x0004
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Transmit Time Tag for Synchronize Mode Command
14 R/W 0 Message Error Mask
13 R/W 0 Service Request Bit Mask
12 R/W 0 Busy Bit Mask
11 R/W 0 Subsystem Flag Bit Mask
10 R/W 0 Terminal Flag Bit Mask
9 R/W 0 Reserved Bits Mask
8 R/W 0 Retry Enabled
7 R/W 0 Bus Channel A/B
6 R/W 0 Off-Line Self-Test
5 R/W 0 Mask Broadcast Bit
4 R/W 0 EOM Interrupt Enable
3 R/W 0 1553A/B Select
2 R/W 0 Mode Code Format
1 R/W 0 Broadcast Format
0 (LSB) R/W 0 RT-to-RT Format
Registers and Command/Status Words
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2.7. RT Subaddress Control Word Register, Read/Write 0x0004
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Rx: Double/Global Buffer Enable
14 R/W 0 Tx: EOM INT
13 R/W 0 Tx: CIRC BUF INT
12 R/W 0 Tx: Memory Management 2 (MM2)
11 R/W 0 Tx: Memory Management 1 (MM1)
10 R/W 0 Tx: Memory Management 0 (MM0)
9 R/W 0 Rx: EOM INT
8 R/W 0 Rx: CIRC BUF INT
7 R/W 0 Rx: Memory Management 2 (MM2)
6 R/W 0 Rx: Memory Management 1 (MM1)
5 R/W 0 Rx: Memory Management 0 (MM0)
4 R/W 0 BCST: EOM INT
3 R/W 0 BCST: CIRC BUF INT
2 R/W 0 BCST: Memory Management 2 (MM2)
1 R/W 0 BCST: Memory Management 1 (MM1)
0 (LSB) R/W 0 BCST: Memory Management 0 (MM0)
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Registers and Command/Status Words
2.8. Time Tag Register, Read/Write 0x0005
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Time Tag, bit 15
.
...
.
...
0 (LSB) R/W 0 Time Tag, bit 0
The resolution of the Time Tag Register (μs/LSB) is programmable by means of bits 9, 8, and 7 of “Configuration Register #2, Read/Write 0x0002” on page 11. See Table 4 below.
Table 4. Time Tag Register Resolution
Configuration Register #2Time Tag Resolution Rollover Time (Modulus)BIT9
TTR2BIT8 TTR1
BIT7 TTR0
0 0 0 64 μs 4.194 sec.
0 0 1 32 μs 2.097 sec.
0 1 0 16 μs 1.048 sec.
0 1 1 8 μs 524 ms
1 0 0 4 μs 262 ms
1 0 1 2 μs 131 ms
1 1 0 TEST MODE N/A
1 1 1 EXTERNAL CLOCK (see NOTE) N/A
Registers and Command/Status Words
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2.9. Interrupt Status Register #1, Read Only 0x0006
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Master Interrupt
14 R 0 RAM Parity Error
13 R 0 Transmitter Timeout
12 R 0 BC/RT Command Stack Rollover
11 R 0 MT Command Stack Rollover
10 R 0 MT Data Stack Rollover
9 R 0 Handshake Fail
8 R 0 BC Retry
7 R 0 RT Address Parity Error
6 R 0 Time Tag Rollover
5 R 0 RT Circular Buffer Rollover
4 R 0 BC Control Word / RT Subaddress Control Word EOM
3 R 0 BC End of Frame
2 R 0 Format Error
1 R 0 BC Status Set / RT Mode Code / MT Pattern Trigger
0 (LSB) R 0 End of Message
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Registers and Command/Status Words
2.10. Configuration Register #3, Read/Write 0x0007
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Enhanced Mode Enable
14 R/W 0 BC/RT Command Stack Size 1
13 R/W 0 BC/RT Command Stack Size 0
12 R/W 0 MT Command Stack Size 1
11 R/W 0 MT Command Stack Size 0
10 R/W 0 MT Data Stack Size 2
9 R/W 0 MT Data Stack Size 1
8 R/W 0 MT Data Stack Size 0
7 R/W 0 Illegalization Disabled
6 R/W 0 Override Mode T/R Error
5 R/W 0 Alternate Status Word Enable
4 R/W 0 Illegal Rx Transfer Disable
3 R/W 0 Busy RX Transfer Disable
2 R/W 0 RTFAIL / RTFLAG Wrap Enable
1 R/W 0 1553A Mode Codes Enable
0 (LSB) R/W 0 Enhanced Mode Code Handling
Registers and Command/Status Words
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2.11. Configuration Register #4, Read/Write 0x0008
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 External Bit Word Enable
14 R/W 0 Inhibit Bit Word If Busy
13 R/W 0 Mode Command Override Busy
12 R/W 0 Expanded BC Control Word Enable
11 R/W 0 Broadcast Mask ENA/XOR
10 R/W 0 Retry If 1553A and Message Error
9 R/W 0 Retry if Status Set
8 R/W 0 1st Retry ALT/ SAME Bus
7 R/W 0 2nd Retry ALT/ SAME Bus
6 R/W 0 Valid Message Error / No Data
5 R/W 0 Valid Busy Bit / No Data
4 R/W 0 MT Tag Gap Option
3 R/W 0 Latch RT Address with Configuration Register #5
2 R/W 0 Test Mode 2
1 R/W 0 Test Mode 1
0 (LSB) R/W 0 Test Mode 0
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Registers and Command/Status Words
2.12. Configuration Register #5, Read/Write 0x0009
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 12 / 16 MHz Clock Select
14 R/W 0 Single-Ended Select
13 R/W 0 External Tx Inhibit A
12 R/W 0 External Tx Inhibit B
11 R/W 0 Expanded Crossing Enabled
10 R/W 0 Response Time Out Select 1
9 R/W 0 Response Time Out Select 0
8 R/W 0 Gap Check Enabled
7 R/W 0 Broadcast Disabled
6 R/W 0 RT Address Latch / Transparent
5 R/W 0 RT Address 4
4 R/W 0 RT Address 3
3 R/W 0 RT Address 2
2 R/W 0 RT Address 1
1 R/W 0 RT Address 0
0 (LSB) R/W 0 RT Address Parity
2.13. RT/Monitor Data Stack Address Register, Read/Write 0x000A
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 RT/Monitor Data Stack Address, bit 15
.
...
.
...
0 (LSB) R/W 0 RT/Monitor Data Stack Address, bit 0
Registers and Command/Status Words
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2.14. BC Frame Time Remaining Register, Read Only 0x000B
Bit No. R/W Reset Bit Description
15 (MSB) R 0 BC Frame Time Remaining, bit 15
.
...
.
...
0 (LSB) R 0 BC Frame Time Remaining, bit 0
2.15. BC Message Time Remaining Register, Read Only 0x000C
Bit No. R/W Reset Bit Description
15 (MSB) R 0 BC Message Time Remaining, bit 15
.
...
.
...
0 (LSB) R 0 BC Message Time Remaining, bit 0
2.16. Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Register, Read/Write 0x000D
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Register, bit 15
.
...
.
...
0 (LSB) R/W 0 Non-Enhanced BC Frame Time/Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Register, bit 0
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Registers and Command/Status Words
2.17. RT Status Word Register, Read Only 0x000E
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Logic “0”
14 R 0 Logic “0”
13 R 0 Logic “0”
12 R 0 Logic “0”
11 R 0 Logic “0”
10 R 0 Message Error
9 R 0 Instrumentation
8 R 0 Service Request
7 R 0 Reserved
6 R 0 Reserved
5 R 0 Reserved
4 R 0 Broadcast Command Received
3 R 0 Busy
2 R 0 SSFLAG
1 R 0 Dynamic Bus Control Accept
0 (LSB) R 0 Terminal Flag
Registers and Command/Status Words
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2.18. RT Bit Word Register, Read Only 0x000F
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Transmitter Timeout
14 R 0 Loop Test Failure B
13 R 0 Loop Test Failure A
12 R 0 Handshake Failure
11 R 0 Transmitter Shutdown B
10 R 0 Transmitter Shutdown A
9 R 0 Terminal Flag Inhibited
8 R 0 Bit Test Fail
7 R 0 High Word Count
6 R 0 Low Word Count
5 R 0 Incorrect Sync Received
4 R 0 Parity/Manchester Error Received
3 R 0 RT−to−RT Gap / Sync / Address Error
2 R 0 RT−to−RT No Response Error
1 R 0 RT−to−RT 2nd Command Word Error
0 (LSB) R 0 Command Word Contents Error
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Registers and Command/Status Words
2.19. Configuration Register #6, Read/Write 0x0018
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Enhanced Bus Controller
14 R/W 0 Enhanced CPU Access
13 R/W 0 Command Stack Pointer Increment on EOM (RT, MT)
12 R/W 0 Global Circular Buffer Enable
11 R/W 0 Global Circular Buffer Size 2
10 R/W 0 Global Circular Buffer Size 1
9 R/W 0 Global Circular Buffer Size 0
8 R/W 0 Disable Invalid Messages to Interrupt Statu Queue
7 R/W 0 Disable Valid Messages to Interrupt Status Queue
6 R/W 0 Interrupt Status Queue Enable
5 R/W 0 RT Address Source
4 R/W 0 Enhanced Message Monitor
3 R/W 0 Reserved
2 R/W 0 64-Word Register Space
1 − 0 (LSB) R/W 0
Clock Select Bits [1,0]
These two bits select the Clock Frequency according to the table below.
Clock Select Bit 1 Clock Select Bit 0 Clock Frequency (MHz)
0 0 16
0 1 12
1 0 20
1 1 10
Registers and Command/Status Words
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2.20. Configuration Register #7, Read/Write 0x0019
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Memory Management Base Address 15
14 R/W 0 Memory Management Base Address 14
13 R/W 0 Memory Management Base Address 13
12 R/W 0 Memory Management Base Address 12
11 R/W 0 Memory Management Base Address 11
10 R/W 0 Memory Management Base Address 10
9 R/W 0 Reserved
8 R/W 0 Reserved
7 R/W 0 Reserved
6 R/W 0 Reserved
5 R/W 0 Reserved
4 R/W 0 RT Halt Enable
3 R/W 0 1553B Response Time
2 R/W 0 Enhanced Time Tag Synchronize
1 R/W 0 Enhanced BC Watchdog Timer Enabled
0 (LSB) R/W 0 Mode Code Reset / INCMD Select
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Registers and Command/Status Words
2.21. BC Condition Code Register, Read Only 0x001B
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Logic “1”
14 R 0 Retry 1
13 R 0 Retry 0
12 R 0 Bad Message
11 R 0 Message Status Set
10 R 0 Good Block Transfer
9 R 0 Format Error
8 R 0 No Response
7 R 0 General Purpose Flag 7
6 R 0 General Purpose Flag 6
5 R 0 General Purpose Flag 5
4 R 0 General Purpose Flag 4
3 R 0 General Purpose Flag 3
2 R 0 General Purpose Flag 2
1 R 0 Equal Flag / General Purpose Flag 1
0 (LSB) R 0 Less Than Flag / General Purpose Flag 0
Notes: 1. If the device is not online in enhanced BC mode, the BC Condition Code Register will always return a value of
0x0000.
Registers and Command/Status Words
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2.22. BC General Purpose Flag Register, Write Only 0x001B
Bit No. R/W Reset Bit Description
15 (MSB) W 0 Clear General Purpose Flag 7
14 W 0 Clear General Purpose Flag 6
13 W 0 Clear General Purpose Flag 5
12 W 0 Clear General Purpose Flag 4
11 W 0 Clear General Purpose Flag 3
10 W 0 Clear General Purpose Flag 2
9 W 0 Clear General Purpose Flag 1
8 W 0 Clear General Purpose Flag 0
7 W 0 Set General Purpose Flag 7
6 W 0 Set General Purpose Flag 6
5 W 0 Set General Purpose Flag 5
4 W 0 Set General Purpose Flag 4
3 W 0 Set General Purpose Flag 3
2 W 0 Set General Purpose Flag 2
1 W 0 Set General Purpose Flag 1
0 (LSB) W 0 Set General Purpose Flag 0
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Registers and Command/Status Words
2.23. BIT Test Status Flag Register, Read Only 0x001C
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Protocol Built-In Test Complete
14 R 0 Protocol Built-In Test In-Progress
13 R 0 Protocol Built-In Test Passed
12 R 0 Protocol Built-In Test Abort
11 R 0 Protocol Built-In Test Complete / In-Progress
10 R 0 Logic “0”
9 R 0 Logic “0”
8 R 0 Logic “0”
7 R 0 RAM Built-In Test Complete
6 R 0 RAM Built-In Test In-Progress
5 R 0 RAM Built-In Test Passed
4 R 0 Logic “0”
3 R 0 Logic “0”
2 R 0 Logic “0”
1 R 0 Logic “0”
0 (LSB) R 0 Logic “0”
Registers and Command/Status Words
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2.24. Interrupt Mask Register #2, Read/Write 0x001D
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Not Used
14 R/W 0 BC Op Code Parity Error
13 R/W 0 RT Illegal Command/Message MT Message Received
12 R/W 0 General Purpose Queue / Interrupt Status Queue Rollover
11 R/W 0 Call Stack Pointer Register Error
10 R/W 0 BC Trap Op Code
9 R/W 0 RT Command Stack 50% Rollover
8 R/W 0 RT Circular Buffer 50% Rollover
7 R/W 0 Monitor Command Stack 50% Rollover
6 R/W 0 Monitor Data Stack 50% Rollover
5 R/W 0 Enhanced BC IRQ3
4 R/W 0 Enhanced BC IRQ2
3 R/W 0 Enhanced BC IRQ1
2 R/W 0 Enhanced BC IRQ0
1 R/W 0 Bit Test Complete
0 (LSB) R/W 0 Not Used
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Registers and Command/Status Words
2.25. Interrupt Status Register #2, Read Only 0x001E
Bit No. R/W Reset Bit Description
15 (MSB) R 0 Master Interrupt
14 R 0 BC Op Code Parity Error
13 R 0 RT Illegal Command/Message MT Message Received
12 R 0 General Purpose Queue / Interrupt Status Queue Rollover
11 R 0 Call Stack Pointer Register Error
10 R 0 BC Trap Op Code
9 R 0 RT Command Stack 50% Rollover
8 R 0 RT Circular Buffer 50% Rollover
7 R 0 Monitor Command Stack 50% Rollover
6 R 0 Monitor Data Stack 50% Rollover
5 R 0 Enhanced BC IRQ3
4 R 0 Enhanced BC IRQ2
3 R 0 Enhanced BC IRQ1
2 R 0 Enhanced BC IRQ0
1 R 0 Bit Test Complete
0 (LSB) R 0 Interrupt Chain Bit
Registers and Command/Status Words
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2.26. BC General Purpose Queue Pointer Register / RT, MT Interrupt Status Queue Pointer Register, Read/Write 0x001F
Bit No. R/W Reset Bit Description
15 (MSB) R/W 0 Queue Pointer Base Address 15
14 R/W 0 Queue Pointer Base Address 14
13 R/W 0 Queue Pointer Base Address 13
12 R/W 0 Queue Pointer Base Address 12
11 R/W 0 Queue Pointer Base Address 11
10 R/W 0 Queue Pointer Base Address 10
9 R/W 0 Queue Pointer Base Address 9
8 R/W 0 Queue Pointer Base Address 8
7 R/W 0 Queue Pointer Base Address 7
6 R/W 0 Queue Pointer Base Address 6
5 R/W 0 Queue Pointer Address 5
4 R/W 0 Queue Pointer Address 4
3 R/W 0 Queue Pointer Address 3
2 R/W 0 Queue Pointer Address 2
1 R/W 0 Queue Pointer Address 1
0 (LSB) R/W 0 Queue Pointer Address 0
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Registers and Command/Status Words
The following sections list various Command and Status Words stored in RAM.
2.27. BC Mode Block Status Word
Bit No. Bit Description
15 (MSB) EOM
14 SOM
13 Channel B / A
12 Error Flag
11 Status Set
10 Format Error
9 No Response Timeout
8 Loop Test Fail
7 Masked Status Set
6 Retry Count 1
5 Retry Count 0
4 Good Data Block Transfer
3 Wrong Status Address / No Gap
2 Word Count Error
1 Incorrect Sync Type
0 (LSB) Invalid Word
Registers and Command/Status Words
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2.28. RT Mode Block Status Word
Bit No. Bit Description
15 (MSB) EOM
14 SOM
13 Channel B / A
12 Error Flag
11 RT−to−RT Format
10 Format Error
9 No Response Timeout
8 Loop Test Fail
7 Data Stack Rollover
6 Illegal Command Word
5 Word Count Error
4 Incorrect Data Sync
3 Invalid Word
2 RT−to−RT Gap / Sync / Address Error
1 RT−to−RT 2nd Command Error
0 (LSB) Command Word Contents Error
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Registers and Command/Status Words
2.29. 1553 Command Word
Bit No. Bit Description
15 (MSB) Remote Terminal Address Bit 4
14 Remote Terminal Address Bit 3
13 Remote Terminal Address Bit 2
12 Remote Terminal Address Bit 1
11 Remote Terminal Address Bit 0
10 Transmit / Receive
9 Subaddress / Mode Code Bit 4
8 Subaddress / Mode Code Bit 3
7 Subaddress / Mode Code Bit 2
6 Subaddress / Mode Code Bit 1
5 Subaddress / Mode Code Bit 0
4 Data Word Count / Mode Code Bit 4
3 Data Word Count / Mode Code Bit 3
2 Data Word Count / Mode Code Bit 2
1 Data Word Count / Mode Code Bit 1
0 (LSB) Data Word Count / Mode Code Bit 0
Registers and Command/Status Words
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2.30. Word Monitor Identification Word
Bit No. Bit Description
15 (MSB) Gap Time (MSB)
14 .
13 .
12 .
11 .
10 .
9 .
8 Gap Time (LSB)
7 Word Flag
6 This RT
5 Broadcast
4 Error
3 Command / Data
2 Channel B / A
1 Contiguous Data / Gap
0 (LSB) Mode_Code
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Registers and Command/Status Words
2.31. Message Monitor Mode Block Status Word
Bit No. Bit Description
15 (MSB) EOM
14 SOM
13 Channel B / A
12 Error Flag
11 RT−to−RT Transfer
10 Format Error
9 No Response Timeout
8 Good Data Block Transfer
7 Data Stack Rollover
6 Reserved
5 Word Count Error
4 Incorrect Sync
3 Invalid Word
2 RT−to−RT Gap / Sync / Address Error
1 RT−to−RT 2nd Command Error
0 (LSB) Command Word Contents Error
Registers and Command/Status Words
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2.32. RT/Monitor Interrupt Status Word (For Interrupt Status Queue)
Bit No. Message Interrupt Event Non-Message Interrupt Event
15 (MSB) Transmitter Timeout Not Used
14 Illegal Command Not Used
13 Monitor Data Stack 50% Rollover Not Used
12 Monitor Data Stack Rollover Not Used
11 RT Circular Buffer 50% Rollover Not Used
10 RT Circular Buffer Rollover Not Used
9 Monitor Command (Descriptor) Stack 50% Rollover Not Used
8 Monitor Command (Descriptor) Stack Rollover Not Used
7 RT Command (Descriptor) Stack 50% Rollover Not Used
6 RT Command (Descriptor) Stack Rollover Not Used
5 Handshake Fail Not Used
4 Format Error Time Tag Rollover
3 Mode Code Interrupt RT Address Parity Error
2 Subaddress Control Word EOM Protocol Self-Test Complete
1 End-Of-Message (EOM) RAM Parity Error
0 (LSB) Logic “1” Logic “0”
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Registers and Command/Status Words
2.33. 1553 Status Word
Bit No. Bit Description
15 (MSB) Remote Terminal Address Bit 4
14 Remote Terminal Address Bit 3
13 Remote Terminal Address Bit 2
12 Remote Terminal Address Bit 1
11 Remote Terminal Address Bit 0
10 Message Error
9 Instrumentation
8 Service Request
7 Reserved
6 Reserved
5 Reserved
4 Broadcast Command Received
3 Busy
2 SSFLAG
1 Dynamic Bus Control Acceptance
0 (LSB) Terminal Flag
Signal Descriptions
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3. Signal Descriptions
Table 5. Power and Ground
Signal Name Balls Description
+3.3V_XCVR
B6, B7, B8, C6, C7, C12, D12, G6, G7, G8, G9,
K12, L6, L7, L12, M6, M7, N9
+ 3.3 Volt Transceiver Power
+3.3V_LOGICB16, B17, C16, C17, F13,
F14, G13, G14, M16, M17, N19, N20
+3.3 V Logic Power
GND_XCVR A1, A2, A3, B1, B2, B3, M1, M2, M3, N1, N2, N3 Transceiver Ground
GND_XCVR/THERMAL
B9, B10, B11, C8, C9, C10, C11, D8, D9, D10, D11, E9, E10, E11, J9, J10, J11, K8, K9, K10,
K11, L8, L9, L10, L11, M9, M10, M11
Transceiver Ground/Thermal connections.
GND_LOGIC
A22, A23, A24, B20, B22, B23, B24, C22, C23, C24, E17, E18, E19, F17, F18,
F19, G17, G18, G19, H17, H18, H19, H20, J17, J18, J19, J20, L14, L15,
L22, L23, L24, M14, M15, M22, M23, M24, N22,
N23, N24
Logic Ground
Table 6. Bus Connections
Signal Name Function Balls Description
CHA_1553 Analog I/O D1, D2, D3
MIL-STD-1553 Transmit/Receive Input/Output. Transformer coupled connections.
CHA_1553 Analog I/O F1, F2, F3
CHB_1553 Analog I/O H1, H2, H3
CHB_1553 Analog I/O K1, K2, K3
CHA_1553-D Analog I/O D4, E4, F4
MIL-STD-1553 Transmit/Receive Input/Output. Direct coupled connections.
CHA_1553-D Analog I/O E1, E2, E3
CHB_1553-D Analog I/O H4, J4, K4
CHB_1553-D Analog I/O J1, J2, J3
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Signal Descriptions
Table 7. External Transceiver Interface
Important Note: When using the integrated internal transceivers, the connections outlined in the table below are mandatory.
Signal Name Function Balls Using Internal “Built-In” Transceivers Using External Transceivers
SNGL_END Digital Input A21No Connect “NC” if utilizing “Built-In”
Transceivers
If SNGL_END is connected to logic “0” the Manchester decoder inputs will be configured to accept single-ended input signals (e.g.,MIL-STD-1773 fiber optic receiver outputs).
If SNGL_END is connected to logic “1,” the decoder inputs will be configured to accept standard double-ended Manchester bi-phase input signals (i.e., MIL-STD-1553 receiver outputs).
TXINH_IN_A Digital Input A12 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals together. Connect TXINH_OUT (Digital transmit inhibit output) to the TXINH input of external MIL-STD-1553 transceivers. Assert high to inhibit when not transmitting in the respective bus.
TXINH_OUT_A Digital Output A13
TXDATA_IN_A Digital Input A9 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect TXDATA_OUT (Digital Manchester biphase transmit data output) directly to the corresponding input of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
TXDATA_OUT_A Digital Output A10
TXDATA_IN_A Digital Input B14 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect TXDATA_OUT (Digital Manchester biphase transmit data output) directly to the corresponding input of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
TXDATA_OUT_A Digital Output C14
RXDATA_IN_A Digital Input G12 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect RXDATA_IN (Digital Manchester biphase receive data input) directly to the corresponding output of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
RXDATA_OUT_A Digital Output F12
RXDATA_IN_A Digital Input G11 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect RXDATA_IN (Digital Manchester biphase receive data input) directly to the corresponding output of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
RXDATA_OUT_A Digital Output F11
TXINH_IN_B Digital Input M20 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals together. Connect TXINH_OUT (Digital transmit inhibit output) to the TXINH input of external MIL-STD-1553 transceivers. Assert high to inhibit when not transmitting in the respective bus.
TXINH_OUT_B Digital Output M19
Signal Descriptions
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Signal Name Function Balls Using Internal “Built-In” Transceivers Using External Transceivers
TXDATA_IN_B Digital Input J16 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect TXDATA_OUT (Digital Manchester biphase transmit data output) directly to the corresponding input of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
TXDATA_OUT_B Digital Output K16
TXDATA_IN_B Digital Input K18 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect TXDATA_OUT (Digital Manchester biphase transmit data output) directly to the corresponding input of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
TXDATA_OUT_B Digital Output K19
RXDATA_IN_B Digital Input M13 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect RXDATA_IN (Digital Manchester biphase receive data input) directly to the corresponding output of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
RXDATA_OUT_B Digital Output M12
RXDATA_IN_B Digital Input N13 These two signals MUST be directly connected for normal “Built-In”
transceiver operation.
Do NOT connect these two signals. Connect RXDATA_IN (Digital Manchester biphase receive data input) directly to the corresponding output of a MIL-STD-1553 or MIL-STD-1773 (fiber optic) transceiver.
RXDATA_OUT_B Digital Output N12
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Signal Descriptions
Table 8. Data Bus
Signal Name Balls Description
D15 (MSB) D21
16-bit bi-directional data bus. This bus interfaces the host processor to the internal registers and internal RAM.
D14 E24
D13 E22
D12 E23
D11 E21
D10 F24
D09 F22
D08 F23
D07 F21
D06 G23
D05 G22
D04 G24
D03 G21
D02 H23
D01 H22
D00 (LSB) H24
Signal Descriptions
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Table 9. Host Address Bus
Signal NameBalls DescriptionHI-62203x
(64K RAM)HI-62213x (4K RAM)
A15 (MSB) A15 / CLK_SEL_1 D17
16-bit bi-directional address bus.
For HI-62203x (64K RAM versions), this signal is always configured as address line A15 (MSB). Refer to the description for A11-A0 below.
For HI-62213x (4K RAM versions), if UPADDREN is connected to logic “1”, this signal operates as address line A15. If UPADDREN is connected to logic “0”, this signal operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select the clock frequency, as follows:
CLK_SEL_1 CLK_SEL_0 Clock Frequency
0 0 10 MHz
0 1 20 MHz
1 0 12 MHz
1 1 16 MHz
A14 A14 / CLK_SEL_0 A16
For HI-62203x (64K RAM versions), this signal is always configured as address line A14. Refer to the description of A11-A0 below.
For HI-62213x (4K RAM versions), if UPADDREN is connected to logic “1”, this signal operates as A14. If UPADDREN is connected to logic “0”, then this signal operates as CLK_SEL_0. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the clock frequency, as defined in the table above.
A13 A13 / LOGIC “1” D16
For HI-62203x (64K RAM versions), this signal is always configured as address line A13. Refer to the description for A11-A0 below.
For HI-62213x (4K RAM versions), if UPADDREN is connected to logic “1”, this signal operates as A13. If UPADDREN is connected to logic “0”, then this signal MUST be connected to +3.3V_LOGIC (logic “1”).
A12 A12 / RTBOOT B15
For HI-62203x (64K RAM versions), this signal is always configured as address line A12. Refer to the description for A11-A0 below.
For HI-62213x (4K RAM versions), if UPADDREN is connected to logic “1”, this signal operates as A12. If UPADDREN is connected to logic “0”, then this signal functions as RTBOOT .
If RTBOOT is connected to logic “0”, the device will initialize in RT mode with the Busy status word bit set following power turn-on (MIL-STD-1760 operation enabled). If RTBOOT is hardwired to logic “1”, the device will initialize in either Idle mode (if BC_Disable is high), or in BC mode (if BC_Disable is low).
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Signal Descriptions
Signal NameBalls DescriptionHI-62203x
(64K RAM)HI-62213x (4K RAM)
A11 A11 / (MSB) C15
Lower 12 bits of 16-bit bi-directional address bus.
In both the buffered and transparent modes, the host CPU accesses registers and internal RAM by means of A11 − A0 (HI-62213x, 4K versions). For 64K versions, A15 − A12 are also used for this purpose.
In buffered mode, A11 − A0 (or A15 − A0) are inputs only. In the transparent mode, A11 − A0 (or A15 − A0) are inputs during CPU accesses and become outputs (driving) when the 1553 protocol/memory management logic accesses up to 64K words of external RAM.
In transparent mode, the address bus is driven (outputs) only when the signal DTACK is low (indicating that the device has control of the RAM interface bus) and IOEN is high, indicating a non-host access. Most of the time, including immediately after power turn-on, A11 − A0 (or A15 − A0) will be in high impedance (input) state.
A10 A10 A15
A09 A09 A14
A08 A08 D14
A07 A07 B12
A06 A06 D15
A05 A05 E13
A04 A04 E15
A03 A03 E12
A02 A02 F15
A01 A01 E14
A00 (LSB) A00 (LSB) F16
Table 10. Host Interface
Signal Name Function Balls Description
SELECT Digital Input B18Device Select.
Used by Host to select the device for a transfer to / from either RAM or registers.
STRBD Digital Input A18
Strobe Data.
Used in conjunction with SELECT to initiate and control the data transfer cycle between the host processor and the HI-6220.
STRBD must be asserted low through the full duration of the transfer cycle.
RD / WR Digital Input A17
Read/Write.
In the 16-bit buffered mode, if POL_SEL is logic “0”, then RD / WR should be low (logic “0”) for read accesses and high (logic “1”) for write accesses.
If POL_SEL is logic “1”, or the interface is configured for a mode other than 16-bit buffered mode, then RD / WR is high (logic “1”) for read accesses and low (logic “0”) for write accesses.
Signal Descriptions
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Signal Name Function Balls Description
ADDR_LAT Digital Input
L16
Memory Output Enable or Address Latch.
In buffered mode, the ADDR_LAT input is used to configure the buffers for A15 − A0, SELECT , MEM / REG , and MSB / LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is, internal transparent latches will track the values on A15 − A0, SELECT , MEM / REG , and MSB / LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low.
In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be hardwired to logic “1”. For interfacing to processors with a multiplexed address/data bus, ADDR_LAT should be connected to a signal that indicates a valid address when ADDR_LAT is logic “1”.
In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles (normally connected to the OE input signal on external RAM chips).
MEMOE Digital Output
ZEROWAIT Digital Input
N16
Memory Write or Zero Wait.
In buffered mode, input signal ( ZEROWAIT ) is used to select between the zero wait mode ( ZEROWAIT = “0”) and the non-zero wait mode ( ZEROWAIT = “1”).
In transparent mode, active low output signal ( MEMWR ) is asserted low during memory write transfers to strobe data into external RAM (normally connected to the WR input signal on external RAM chips).
MEMWR Digital Output
16 / 8 Digital Input
L17
Data Transfer Request or Data Bus Select.
In buffered mode, input signal 16 / 8 used to select between the 16 bit data transfer mode (16 / 8 = “1”) and the 8-bit data transfer mode (16 / 8 = “0”).
In transparent mode (16-bit only), DTREQ used to request access to the processor/RAM interface bus (address and data buses).
DTREQ Digital Output
MSB / LSB Digital Input
J14
Data Transfer Grant or Most Significant Byte/Least Significant Byte.
In 8-bit buffered mode, input signal (MSB / LSB) used to indicate which byte is currently being transferred (MSB or LSB). The logic sense of MSB / LSB is controlled by the POL_SEL input. MSB / LSB is not used in the 16-bit buffered mode.
In transparent mode, DTGRT is asserted in response to the DTREQ output to indicate that control of the external processor/RAM bus has been transferred from the host processor to the HI-6220. DTGRT
Digital Input
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Signal Descriptions
Signal Name Function Balls Description
POL_SEL Digital Input
N17
Data Transfer Acknowledge or Polarity Select.
In 16-bit buffered mode, if POL_SEL is connected to logic “1”, RD / WR should be asserted high (logic “1”) for a read operation and low (logic “0”) for a write operation. In 16-bit buffered mode, if POL_SEL is connected to logic “0”, RD / WR should be asserted low (logic “0”) for a read operation and high (logic “1”) for a write operation.
In 8-bit buffered mode (TRANSPARENT / BUFFERED = “0” and 16 / 8 = “0”), POL_SEL input signal is used to control the logic sense of the MSB / LSB signal. If POL_SEL is connected to logic “0”, MSB / LSB should be asserted low (logic “0”) to indicate the transfer of the least significant byte and high (logic “1”) to indicate the transfer of the most significant byte. If POL_SEL is connected to logic “1”, MSB / LSB should be asserted high (logic “1”) to indicate the transfer of the least significant byte and low (logic “0”) to indicate the transfer of the most significant byte.
In transparent mode, DTACK used to indicate acceptance of the processor/RAM interface bus in response to a data transfer grant ( DTGRT ).
RAM transfers over A15 − A0 and D15 − D0 will be framed by the time that DTACK is asserted low.
DTACK Digital Output
TRIG_SEL Digital Input
M18
Memory Enable or Trigger Select input.
In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which byte pairs are transferred to or from the device by the host processor. In the 8-bit buffered mode, TRIG_SEL should be asserted high (logic "1") if the byte order for both read operations and write operations is MSB followed by LSB. TRIG_SEL should be asserted low (logic "0") if the byte order for both read operations and write operations is LSB followed by MSB. This signal has no operation in the 16-bit buffered mode (it does not need to be connected).
In transparent mode, MEMENA_IN is used as a Chip Select (CS) input to the internal shared RAM. If only internal RAM is used, MEMENA_IN should be connected directly to the output of a gate that is OR'ing the DTACK and IOEN output signals.
MEMENA_IN Digital Input
MEM/ REG Digital Input C18
Memory or Register.
Selects between memory access (MEM / REG = "1") or register access (MEM / REG = "0"). Usually connected to either a CPU address line or address decoder output.
Signal Descriptions
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Signal Name Function Balls Description
SSFLAG Digital Input
K14
Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input.
In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the RT Status Word. If the SSFLAG input is logic "0" while bit 8 of Configuration Register #1 (SUBSYSTEM FLAG) has been programmed to logic "1", the Subsystem Flag RT Status Word bit will become logic "1," but bit 8 of Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG register bit.
In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the external BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will issue a BC Start Command, starting execution of the current BC frame.
In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction.
In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will initiate a monitor start.
This input has no effect in Message Monitor mode.
EXT_TRIG Digital Input
TRANSPARENT / BUFFERED
Digital Input D22
Used to select between the buffered mode (when strapped to logic "0") and transparent/DMA mode (when strapped to logic "1") for the host processor interface.
READYD Digital Output C21
Handshake output to host processor.
For a nonzero wait state read access, READYD is asserted at the end of a host transfer cycle to indicate that data is available to be read on D15 through D0. For a nonzero wait state write cycle, READYD is asserted at the end of the cycle to indicate that data has been transferred to a register or RAM location.
For both nonzero wait reads and writes, the host must assert STRBD low until READYD is asserted low.
In the (buffered) zero wait state mode, this output is normally logic "1", indicating that the device is in a state ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from high to low during (or just after) a host transfer cycle, when the device initiates its internal transfer to or from registers or internal RAM. When the internal transfer is complete, READYD returns to logic "1", indicating it is ready for the host to initiate a subsequent transfer cycle.
IOEN Digital Output C20
I/O Enable.
Tri-state control for external address and data buffers. Generally not used in buffered mode.
When low, indicates that the device is currently performing a host access to an internal register, or internal RAM (external RAM for transparent mode). In transparent mode, IOEN (low) should be used to enable external address and data bus tri-state buffers.
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Signal Descriptions
Table 11. RT Address
Signal Name Function Balls Description
RTAD4 (MSB) Digital Input J21
RT Address input.
If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the RT address is provided by means of these 5 input signals. In addition, if RT ADDRESS SOURCE is logic "0", the source of RT address parity is RTADP.
If RT ADDRESS SOURCE is programmed to logic "1", then the RT address and parity are under software control, via data lines D5-D0. In this case, the RTAD4 − RTAD0 and RTADP signals are not used.
RTAD3 Digital Input J24
RTAD2 Digital Input J22
RTAD1 Digital Input K23
RTAD0 (LSB) Digital Input K21
RTADP Digital Input J23Remote Terminal Address Parity.
This input signal must provide an odd parity sum with RTAD4 − RTAD0 in order for the RT to respond to non-broadcast commands.
RT_AD_LAT Digital Input K24
RT Address Latch.
Input signal used to control the internal RT address latch. If RT_AD_LAT is connected to logic "0", then the RT is configured to accept a hardwired RT address from RTAD4 − RTAD0 and RTADP.
If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4 − RTAD0 and RTADP will be latched internally on the rising edge of RT_AD_LAT.
If RT_AD_LAT is connected to logic "1", then the RT address is latchable under host processor control. In this case, there are two possibilities:
1. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the source of the RT Address is the RTAD4 − RTAD0 and RTADP input signals.
2. If RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the lower 6 bits of the processor data bus, D5 − D1 (for RTAD4 − 0) and D0 (for RTADP).
In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched by:
1. Writing bit 15 of Configuration Register #3, ENHANCED MODE ENABLE, to logic "1".
2. Writing bit 3 of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1".
3. Writing to Configuration Register #5. In the case of RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity must be written to the lower 6 bits of Configuration Register #5, via D5 − D0.
In the case where RT ADDRESS SOURCE = "0", the bit values presented on D5 − D0 become "don't care".
Signal Descriptions
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Table 12. Miscellaneous Signals
Signal NameFunction Balls DescriptionHI-62203x
(64K RAM)HI-62213x (4K RAM)
+3.3V_Logic UPADDREN Digital Input A19
UPADDREN is used to control the function of the upper 4 address inputs (A15 − A12).
If UPADDREN is connected to logic "1", then these four signals operate as address lines A15 − A12.
If UPADDREN is connected to logic "0", then A15 and A14 function as CLK_SEL_1 and CLK_ SEL_0 respectively; A13 MUST be connected to LOGIC "1"; and A12 functions as RTBOOT.
SLEEPIN Digital Input H10 Connecting this input has no effect.
INCMD Digital Output H21
For BC, RT, or Selective Message Monitor modes, INCMD is asserted low whenever a message is being processed. In Word Monitor mode, INCMD will be asserted low for as long as the monitor is online.
MCRST Digital Output D19For RT mode MCRST will be asserted low for two clock cycles following receipt of a Reset Remote Terminal mode command.
RSTBITEN Digital Input K22
If this input is set to logic "1", the Built-In-Self-Test (BIST) will be enabled after hardware reset (for example, following power-up).
A logic "0" input disables both the power-up and user-initiated automatic BIST.
INT Digital Output D24
Interrupt Request output.
If the LEVEL / PULSE interrupt bit (bit 3) of Configuration Register #2 is logic "0", a negative pulse of approximately 500 ns is output on INT to signal an interrupt request.
If LEVEL / PULSE is high, a low level interrupt request output will be asserted on INT . The level interrupt will be cleared (high) after either:
1. The processor writes a value of logic "1" to INTERRUPT RE-SET, bit 2 of the Start/Reset Register; or
2. If bit 4 of Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1", then reading the Interrupt Status Register (#1 and/or #2) that is requesting an interrupt enabled by the corresponding Interrupt Mask Register will clear INT. However, for the case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits set reflecting interrupt events, it will be necessary to read both interrupt status registers in order to clear INT.
CLOCK_IN Digital Input N18 20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input.
TX_INH_A Digital Input A20Transmitter inhibit inputs for Channel A and Channel B.
For normal operation, these inputs should be connected to logic "0". To force a shutdown of Channel A and / or Channel B, a value of logic "1" should be applied to the respective TX_INH input.TX_INH_B
Digital Input D20
HOLT INTEGRATED CIRCUITS49
Signal Descriptions
Signal NameFunction Balls DescriptionHI-62203x
(64K RAM)HI-62213x (4K RAM)
MSTCLR Digital Input D18Master Clear.
Active low Reset input, normally asserted low following power turn-on.
TAG_CLK Digital Input D23
Time Tag Clock.
External clock that may be used to increment the Time Tag Register. This option is selected by setting Bits 7, 8 and 9 of Configuration Register # 2 to Logic "1".
BC_Disable Digital Input B21Hardware lockout to disable BC opertation and operate the part in RT-Only mode.
Drive high to disable BC, low to enable all modes of operation.
NC -
A4, A5, A6, A7, A8, A11, B4,
B5, B13, B19, C1, C2, C3, C4, C5, C13, C19, D5, D6, D7, D13, E5, E6, E7, E8,
E16, E20, F5, F6, F7, F8, F9, F10, F20, G1, G2, G3, G4,
G5, G10, G15, G16, G20, H5,
H6, H7, H8, H9, H11, H12, H13, H14, H15, H16, J5, J6, J7, J8, J12, J13, J15,
K5, K6, K7, K13, K15, K17,
K20, L1, L2, L3, L4, L5, L13, L18, L19, L20, L21, M4, M5, M8, M21, N4,
N5, N6, N7, N8, N10, N11, N14,
N15, N21
No User Connections to these balls allowed.
Host Interface
HOLT INTEGRATED CIRCUITS50
4. Host InterfaceThe most commonly used host interface is the 16-bit buffered, non-zero wait mode. This configuration may be used to interface the device with a 16 or 32-bit microprocessor. In this mode the device does not access external host memory and uses the internal 4K or 64K words of RAM for storing MIL-STD-1553 data and related buffering. Figure 1 and Table 13 illustrate host read timing and Figure 2 and Table 14 illustrate host write timing respectively.
4.1. Host RAM/Register Read (16-BIT Buffered, Nonzero Wait)
Clock In
t6t1
t5
t2
VALID
t3
t7
t8
t14 t18
t15t11
t13
VALID
t4 t10t9
t19
t12
t16
t17
VALID
SELECT(Note 2,7)
STRBD(Note 2)
MEM/REG(Note 3,4,7)
RD/WR(Note 4,5)
IOEN(Note 2,6)
READYD(Note 6)
A15-A0(Note 7,8,9)
D15-D0(Note 6)
Figure 1. Host RAM/Register Read Timing Diagram (16-BIT Buffered, Nonzero Wait)
Notes for Figure 1: 1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT / BUFFERED must be connected to logic “0”.
ZERO_WAIT and DTREQ / 16/8 must be connected to logic “1”. The inputs TRIGGER_SEL and MSB/LSB may be connected to either Vcc or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1) and the devices’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high.
3. MEM / REG must be high for memory access, low for register access.
4. MEM / REG and RD / WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM / REG and RD / WR become latched internally.
HOLT INTEGRATED CIRCUITS51
Host Interface
5. The logic sense for RD / WR in the diagram assumes that POLARITY_SEL is connected to logic ”1”. If POLARITY_SEL is connected to logic “0”, RD / WR must be asserted low to read.
6. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD and D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. The timing for A15-A0, MEM / REG and SELECT assumes that ADDR-LAT is connected to logic “1”. Refer to Address Latch timing for additional details.
8. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally.
9. Setup time given for use in worst case timing calculation. None of the device’s input signals are required to be synchronized to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flipflop, an additional clock cycle will be inserted between the falling clock edge that latches MEM / REG and RD / WR and the rising clock edge that latches the Address (A15-A0). When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be increased by one clock cycle.
Table 13. Host RAM/Register Read Timing (16-BIT Buffered, Nonzero Wait)
Time Description NotesResponse Time
UnitsMin. Typ. Max.
t1 SELECT and STRBD low setup time prior to clock rising edge 2, 9 15 ns
t2
SELECT and STRBD low to IOEN low
(uncontended access @ 20 MHz)2, 6 105 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz) 2, 6 3.6 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz) 2, 6 520 ns
(uncontended access @ 16 MHz) 2, 6 117 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz) 2, 6 4.6 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 16 MHz) 2, 6 635 ns
(uncontended access @ 12 MHz) 2, 6 138 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz) 2, 6 6.0 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz) 2, 6 820 ns
(uncontended access @ 10 MHz) 2, 6 155 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz) 2, 6 7.2 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz) 2, 6 970 ns
t3
Time for MEM / REG and RD / WR to become valid following SELECT and STRBD low
(@ 20 MHz)3, 4, 5, 7 10 ns
(@ 16 MHz) 3, 4, 5, 7 16 ns
(@ 12 MHz) 3, 4, 5, 7 27 ns
(@ 10 MHz) 3, 4, 5, 7 35 ns
Host Interface
HOLT INTEGRATED CIRCUITS52
Time Description NotesResponse Time
UnitsMin. Typ. Max.
t4
Time for Address to become valid following SELECT and STRBD low
(@ 20 MHz)12 ns
(@ 16 MHz) 25 ns
(@ 12 MHz) 45 ns
(@ 10 MHz) 62 ns
t5 CLOCK IN rising edge delay to IOEN falling edge 6 40 ns
t6 SELECT hold time following IOEN falling 2 0 ns
t7 MEM / REG , RD / WR setup time prior to CLOCK IN falling edge 3, 4, 5, 7 15 ns
t8 MEM / REG , RD / WR hold time following CLOCK IN falling edge 3, 4, 5, 7 30 ns
t9 Address valid setup time prior to CLOCK IN rising edge 7, 8 35 ns
t10 Address valid hold time following CLOCK IN rising edge 7, 8, 9 30 ns
t11
IOEN falling delay to READYD falling
(@ 20 MHz)6, 9 135 150 165 ns
(@ 16 MHz) 6, 9 170 187.5 205 ns
(@ 12 MHz) 6, 9 235 250 265 ns
(@ 10 MHz) 6, 9 285 300 315 ns
t12
Output Data valid prior to READYD falling (@ 20 MHz) 6 11 ns
(@ 16 MHz) 6 23 ns
(@ 12 MHz) 6 44 ns
(@ 10 MHz) 6 61 ns
t13 CLOCK IN rising edge delay to READYD falling 6 40 ns
t14 READYD falling to STRBD rising release time ∞ ns
t15 STRBD rising edge delay to IOEN rising edge and READYD rising edge 6 40 ns
t16 Output Data hold time following STRBD rising edge 0 ns
t17 STRBD rising delay to output data tri-state 40 ns
t18 STRBD high hold time from READYD rising 0 ns
t19 CLOCK IN rising edge delay to output data valid 40 ns
HOLT INTEGRATED CIRCUITS53
Host Interface
4.2. Host RAM/Register Write (16-BIT Buffered, Nonzero Wait)
t7t1
t6
t2
VALID
t3
t8
t9
t16 t18
t17t14
t15
VALID
t4 t12t10
VALID
t13
t5 t11
Clock In
SELECT(Note 2,7)
STRBD(Note 2)
MEM/REG(Note 3,4,7)
RD/WR(Note 4,5)
IOEN(Note 2,6)
READYD(Note 6)
A15-A0(Note 7,8,9)
D15-D0(Note 8,9)
Figure 2. Host RAM/Register Write Timing Diagram (16-BIT Buffered, Nonzero Wait)
Notes for Figure 2: 1. For the 16-bit buffered nonzero wait configuration, TRANSPARENT / BUFFERED must be connected to logic “0”.
ZERO_WAIT and DTREQ / 16/8 must be connected to logic “1”. The inputs TRIGGER_SEL and MSB/LSB may be connected to either Vcc or ground.
2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT • STRBD is sampled low (satisfying t1) and the devices’s protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high.
3. MEM / REG must be high for memory access, low for register access.
4. MEM / REG and RD / WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM / REG and RD / WR become latched internally.
5. The logic sense for RD / WR in the diagram assumes that POLARITY_SEL is connected to logic ”1”. If POLARITY_SEL is connected to logic “0”, RD / WR must be asserted high to write.
6. The timing for IOEN and READYD assumes a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max.
7. The timing for A15-A0, MEM / REG and SELECT assumes that ADDR-LAT is connected to logic “1”. Refer to Address Latch timing for additional details.
8. The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 and D15-D0 become latched internally.
Host Interface
HOLT INTEGRATED CIRCUITS54
9. Setup time given for use in worst case timing calculations. None of the device’s input signals are required to be synchronized to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flipflop, an additional clock cycle may be inserted between the falling clock edge that latches MEM / REG and RD / WR and the rising clock edge that latches the Address (A15-A0) and Data (D15-D0). When this occurs, the delay from IOEN falling to READYD falling (t14) increases by one clock cycle and the address and data hold times (t12 and t13 respectively) must be increased by one clock cycle.
Table 14. Host RAM/Register Write Timing (16-BIT Buffered, Nonzero Wait)
Time Description NotesResponse Time
UnitsMin. Typ. Max.
t1 SELECT and STRBD low setup time prior to clock rising edge 2, 10 15 ns
t2
SELECT and STRBD low to IOEN low
(uncontended access @ 20 MHz)2, 6 105 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 20 MHz) 2, 6 3.6 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 20 MHz) 2, 6 470 ns
(uncontended access @ 16 MHz) 2, 6 117 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 16 MHz) 2, 6 4.6 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 16 MHz) 2, 6 570 ns
(uncontended access @ 12 MHz) 2, 6 138 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 12 MHz) 2, 6 6.0 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 12 MHz) 2, 6 737 ns
(uncontended access @ 10 MHz) 2, 6 155 ns
(contended access, with ENHANCED CPU ACCESS = “0” @ 10 MHz) 2, 6 7.2 μs
(contended access, with ENHANCED CPU ACCESS = “1” @ 10 MHz) 2, 6 870 ns
t3
Time for MEM / REG and RD / WR to become valid following SELECT and STRBD low
(@ 20 MHz)3, 4, 5, 7 10 ns
(@ 16 MHz) 3, 4, 5, 7 16 ns
(@ 12 MHz) 3, 4, 5, 7 27 ns
(@ 10 MHz) 3, 4, 5, 7 35 ns
t4
Time for Address to become valid following SELECT and STRBD low
(@ 20 MHz)12 ns
(@ 16 MHz) 25 ns
(@ 12 MHz) 45 ns
(@ 10 MHz) 62 ns
HOLT INTEGRATED CIRCUITS55
Host Interface
Time Description NotesResponse Time
UnitsMin. Typ. Max.
t5
Time for Data to become valid following SELECT and STRBD low
(@ 20 MHz)32 ns
(@ 16 MHz) 45 ns
(@ 12 MHz) 65 ns
(@ 10 MHz) 82 ns
t6 CLOCK IN rising edge delay to IOEN falling edge 6 40 ns
t7 SELECT hold time following IOEN falling 2 0 ns
t8 MEM / REG , RD / WR setup time prior to CLOCK IN falling edge 3, 4, 5, 7 15 ns
t9 MEM / REG , RD / WR hold time following CLOCK IN falling edge 3, 4, 5, 7 35 ns
t10 Address valid setup time prior to CLOCK IN rising edge 7, 8 35 ns
t11 Data valid setup time prior to CLOCK IN rising edge 15 ns
t12 Address valid hold time following CLOCK IN rising edge 7, 8, 9 30 ns
t13 Data valid hold time following CLOCK IN rising edge 9 15 ns
t14
IOEN falling delay to READYD falling
(@ 20 MHz)6, 9 85 100 115 ns
(@ 16 MHz) 6, 9 110 125 140 ns
(@ 12 MHz) 6, 9 152 167 182 ns
(@ 10 MHz) 6, 9 185 200 215 ns
t15 CLOCK IN rising edge delay to READYD falling 6 40 ns
t16 READYD falling to STRBD rising release time ∞ ns
t17 STRBD rising edge delay to IOEN rising edge and READYD rising edge 6 40 ns
t18 STRBD high hold time from READYD rising 10 ns
Pin Descriptions
HOLT INTEGRATED CIRCUITS56
5. Pin Descriptions
Table 15. HI-62213PBx (4K RAM) Package Pinout
Ball Signal Notes Ball Signal Notes
A1 GND_XCVR B1 GND_XCVR
A2 GND_XCVR B2 GND_XCVR
A3 GND_XCVR B3 GND_XCVR
A4 NC B4 NC
A5 NC B5 NC
A6 NC B6 +3.3V_XCVR
A7 NC B7 +3.3V_XCVR
A8 NC B8 +3.3V_XCVR
A9 TXDATA_IN_A Connect to ball A10 B9 GND_XCVR/THERMAL
A10 TXDATA_OUT_A Connect to ball A9 B10 GND_XCVR/THERMAL
A11 NC B11 GND_XCVR/THERMAL
A12 TXINH_IN_A Connect to ball A13 B12 A07
A13 TXINH_OUT_A Connect to ball A12 B13 NC
A14 A09 B14 TXDATA_IN_A Connect to ball C14
A15 A10 B15 A12 / RTBOOT
A16 A14 / CLK_SEL_0 B16 +3.3V_LOGIC
A17 RD / WR B17 +3.3V_LOGIC
A18 STRBD B18 SELECT
A19 UPADDREN B19 NC
A20 TX_INH_A B20 GND_LOGIC
A21 SNGL_END B21 BC_DISABLE
A22 GND_LOGIC B22 GND_LOGIC
A23 GND_LOGIC B23 GND_LOGIC
A24 GND_LOGIC B24 GND_LOGIC
Continued ...
HOLT INTEGRATED CIRCUITS57
Pin Descriptions
Ball Signal Notes Ball Signal Notes
C1 NC D1 CHA_1553
C2 NC D2 CHA_1553
C3 NC D3 CHA_1553
C4 NC D4 NC / CHA_1553-D
C5 NC D5 NC
C6 +3.3V_XCVR D6 NC
C7 +3.3V_XCVR D7 NC
C8 GND_XCVR/THERMAL D8 GND_XCVR/THERMAL
C9 GND_XCVR/THERMAL D9 GND_XCVR/THERMAL
C10 GND_XCVR/THERMAL D10 GND_XCVR/THERMAL
C11 GND_XCVR/THERMAL D11 GND_XCVR/THERMAL
C12 +3.3V_XCVR D12 +3.3V_XCVR
C13 NC D13 NC
C14 TXDATA_OUT_A Connect to ball B14 D14 A08
C15 A11 / (MSB) D15 A06
C16 +3.3V_LOGIC D16 A13 / LOGIC “1”
C17 +3.3V_LOGIC D17 A15 / CLK_SEL_1
C18 MEM / REG D18 MSTCLR
C19 NC D19 MCRST
C20 IOEN D20 TX_INH_B
C21 READYD D21 D15 (MSB)
C22 GND_LOGIC D22TRANSPARENT /
BUFFERED
C23 GND_LOGIC D23 TAG_CLK
C24 GND_LOGIC D24 INT
Continued ...
Pin Descriptions
HOLT INTEGRATED CIRCUITS58
Ball Signal Notes Ball Signal Notes
E1 NC / CHA_1553-D F1 CHA_1553
E2 NC / CHA_1553-D F2 CHA_1553
E3 NC / CHA_1553-D F3 CHA_1553
E4 NC / CHA_1553-D F4 NC / CHA_1553-D
E5 NC F5 NC
E6 NC F6 NC
E7 NC F7 NC
E8 NC F8 NC
E9 GND_XCVR/THERMAL F9 NC
E10 GND_XCVR/THERMAL F10 NC
E11 GND_XCVR/THERMAL F11 RXDATA_OUT_A Connect to ball G11
E12 A03 F12 RXDATA_OUT_A Connect to ball G12
E13 A05 F13 +3.3V_LOGIC
E14 A01 F14 +3.3V_LOGIC
E15 A04 F15 A02
E16 NC F16 A00 (LSB)
E17 GND_LOGIC F17 GND_LOGIC
E18 GND_LOGIC F18 GND_LOGIC
E19 GND_LOGIC F19 GND_LOGIC
E20 NC F20 NC
E21 D11 F21 D07
E22 D13 F22 D09
E23 D12 F23 D08
E24 D14 F24 D10
Continued ...
HOLT INTEGRATED CIRCUITS59
Pin Descriptions
Ball Signal Notes Ball Signal Notes
G1 NC H1 CHB_1553
G2 NC H2 CHB_1553
G3 NC H3 CHB_1553
G4 NC H4 NC / CHB_1553-D
G5 NC H5 NC
G6 +3.3V_XCVR H6 NC
G7 +3.3V_XCVR H7 NC
G8 +3.3V_XCVR H8 NC
G9 +3.3V_XCVR H9 NC
G10 NC H10 SLEEPIN Connecting this input has no effect
G11 RXDATA_IN_A Connect to ball F11 H11 NC
G12 RXDATA_IN_A Connect to ball F12 H12 NC
G13 +3.3V_LOGIC H13 NC
G14 +3.3V_LOGIC H14 NC
G15 NC H15 NC
G16 NC H16 NC
G17 GND_LOGIC H17 GND_LOGIC
G18 GND_LOGIC H18 GND_LOGIC
G19 GND_LOGIC H19 GND_LOGIC
G20 NC H20 GND_LOGIC
G21 D03 H21 INCMD
G22 D05 H22 D01
G23 D06 H23 D02
G24 D04 H24 D00 (LSB)
Continued ...
Pin Descriptions
HOLT INTEGRATED CIRCUITS60
Ball Signal Notes Ball Signal Notes
J1 NC / CHB_1553-D K1 CHB_1553
J2 NC / CHB_1553-D K2 CHB_1553
J3 NC / CHB_1553-D K3 CHB_1553
J4 NC / CHB_1553-D K4 NC / CHB_1553-D
J5 NC K5 NC
J6 NC K6 NC
J7 NC K7 NC
J8 NC K8 GND_XCVR/THERMAL
J9 GND_XCVR/THERMAL K9 GND_XCVR/THERMAL
J10 GND_XCVR/THERMAL K10 GND_XCVR/THERMAL
J11 GND_XCVR/THERMAL K11 GND_XCVR/THERMAL
J12 NC K12 +3.3V_XCVR
J13 NC K13 NC
J14 MSB / LSB / DTGRT K14 SSFLAG / EXT_TRIG
J15 NC K15 NC
J16 TXDATA_IN_B Connect to ball K16 K16 TXDATA_OUT_B Connect to ball J16
J17 GND_LOGIC K17 NC
J18 GND_LOGIC K18 TXDATA_IN_B Connect to ball K19
J19 GND_LOGIC K19 TXDATA_OUT_B Connect to ball K18
J20 GND_LOGIC K20 NC
J21 RTAD4 (MSB) K21 RTAD0 (LSB)
J22 RTAD2 K22 RSTBITEN
J23 RTADP K23 RTAD1
J24 RTAD3 K24 RT_AD_LAT
Continued ...
HOLT INTEGRATED CIRCUITS61
Pin Descriptions
Ball Signal Notes Ball Signal Notes
L1 NC M1 GND_XCVR
L2 NC M2 GND_XCVR
L3 NC M3 GND_XCVR
L4 NC M4 NC
L5 NC M5 NC
L6 +3.3V_XCVR M6 +3.3V_XCVR
L7 +3.3V_XCVR M7 +3.3V_XCVR
L8 GND_XCVR/THERMAL M8 NC
L9 GND_XCVR/THERMAL M9 GND_XCVR/THERMAL
L10 GND_XCVR/THERMAL M10 GND_XCVR/THERMAL
L11 GND_XCVR/THERMAL M11 GND_XCVR/THERMAL
L12 +3.3V_XCVR M12 RXDATA_OUT_B Connect to ball M13
L13 NC M13 RXDATA_IN_B Connect to ball M12
L14 GND_LOGIC M14 GND_LOGIC
L15 GND_LOGIC M15 GND_LOGIC
L16 ADDR_LAT / MEMOE M16 +3.3V_LOGIC
L17 16 / 8 / DTREQ M17 +3.3V_LOGIC
L18 NC M18 TRIG_SEL / MEMENA_IN
L19 NC M19 TXINH_OUT_B Connect to ball M20
L20 NC M20 TXINH_IN_B Connect to ball M19
L21 NC M21 NC
L22 GND_LOGIC M22 GND_LOGIC
L23 GND_LOGIC M23 GND_LOGIC
L24 GND_LOGIC M24 GND_LOGIC
Continued ...
Pin Descriptions
HOLT INTEGRATED CIRCUITS62
Ball Signal Notes
N1 GND_XCVR
N2 GND_XCVR
N3 GND_XCVR
N4 NC
N5 NC
N6 NC
N7 NC
N8 NC
N9 +3.3V_XCVR
N10 NC
N11 NC
N12 RXDATA_OUT_B Connect to ball N13
N13 RXDATA_IN_B Connect to ball N12
N14 NC
N15 NC
N16 ZEROWAIT / MEMWR
N17 POL_SEL / DTACK
N18 CLOCK_IN
N19 +3.3V_LOGIC
N20 +3.3V_LOGIC
N21 NC
N22 GND_LOGIC
N23 GND_LOGIC
N24 GND_LOGIC
HOLT INTEGRATED CIRCUITS63
Pin Descriptions
Table 16. HI-62203PBx (64K RAM) Package Pinout
Ball Signal Notes Ball Signal Notes
A1 GND_XCVR B1 GND_XCVR
A2 GND_XCVR B2 GND_XCVR
A3 GND_XCVR B3 GND_XCVR
A4 NC B4 NC
A5 NC B5 NC
A6 NC B6 +3.3V_XCVR
A7 NC B7 +3.3V_XCVR
A8 NC B8 +3.3V_XCVR
A9 TXDATA_IN_A Connect to ball A10 B9 GND_XCVR/THERMAL
A10 TXDATA_OUT_A Connect to ball A9 B10 GND_XCVR/THERMAL
A11 NC B11 GND_XCVR/THERMAL
A12 TXINH_IN_A Connect to ball A13 B12 A07
A13 TXINH_OUT_A Connect to ball A12 B13 NC
A14 A09 B14 TXDATA_IN_A Connect to ball C14
A15 A10 B15 A12
A16 A14 B16 +3.3V_LOGIC
A17 RD / WR B17 +3.3V_LOGIC
A18 STRBD B18 SELECT
A19 +3.3V_LOGIC B19 NC
A20 TX_INH_A B20 GND_LOGIC
A21 SNGL_END B21 BC_DISABLE
A22 GND_LOGIC B22 GND_LOGIC
A23 GND_LOGIC B23 GND_LOGIC
A24 GND_LOGIC B24 GND_LOGIC
Continued ...
Pin Descriptions
HOLT INTEGRATED CIRCUITS64
Ball Signal Notes Ball Signal Notes
C1 NC D1 CHA_1553
C2 NC D2 CHA_1553
C3 NC D3 CHA_1553
C4 NC D4 NC / CHA_1553-D
C5 NC D5 NC
C6 +3.3V_XCVR D6 NC
C7 +3.3V_XCVR D7 NC
C8 GND_XCVR/THERMAL D8 GND_XCVR/THERMAL
C9 GND_XCVR/THERMAL D9 GND_XCVR/THERMAL
C10 GND_XCVR/THERMAL D10 GND_XCVR/THERMAL
C11 GND_XCVR/THERMAL D11 GND_XCVR/THERMAL
C12 +3.3V_XCVR D12 +3.3V_XCVR
C13 NC D13 NC
C14 TXDATA_OUT_A Connect to ball B14 D14 A08
C15 A11 / (MSB) D15 A06
C16 +3.3V_LOGIC D16 A13
C17 +3.3V_LOGIC D17 A15
C18 MEM / REG D18 MSTCLR
C19 NC D19 MCRST
C20 IOEN D20 TX_INH_B
C21 READYD D21 D15 (MSB)
C22 GND_LOGIC D22TRANSPARENT /
BUFFERED
C23 GND_LOGIC D23 TAG_CLK
C24 GND_LOGIC D24 INT
Continued ...
HOLT INTEGRATED CIRCUITS65
Pin Descriptions
Ball Signal Notes Ball Signal Notes
E1 NC / CHA_1553-D F1 CHA_1553
E2 NC / CHA_1553-D F2 CHA_1553
E3 NC / CHA_1553-D F3 CHA_1553
E4 NC / CHA_1553-D F4 NC / CHA_1553-D
E5 NC F5 NC
E6 NC F6 NC
E7 NC F7 NC
E8 NC F8 NC
E9 GND_XCVR/THERMAL F9 NC
E10 GND_XCVR/THERMAL F10 NC
E11 GND_XCVR/THERMAL F11 RXDATA_OUT_A Connect to ball G11
E12 A03 F12 RXDATA_OUT_A Connect to ball G12
E13 A05 F13 +3.3V_LOGIC
E14 A01 F14 +3.3V_LOGIC
E15 A04 F15 A02
E16 NC F16 A00 (LSB)
E17 GND_LOGIC F17 GND_LOGIC
E18 GND_LOGIC F18 GND_LOGIC
E19 GND_LOGIC F19 GND_LOGIC
E20 NC F20 NC
E21 D11 F21 D07
E22 D13 F22 D09
E23 D12 F23 D08
E24 D14 F24 D10
Continued ...
Pin Descriptions
HOLT INTEGRATED CIRCUITS66
Ball Signal Notes Ball Signal Notes
G1 NC H1 CHB_1553
G2 NC H2 CHB_1553
G3 NC H3 CHB_1553
G4 NC H4 NC / CHB_1553-D
G5 NC H5 NC
G6 +3.3V_XCVR H6 NC
G7 +3.3V_XCVR H7 NC
G8 +3.3V_XCVR H8 NC
G9 +3.3V_XCVR H9 NC
G10 NC H10 SLEEPIN Connecting this input has no effect
G11 RXDATA_IN_A Connect to ball F11 H11 NC
G12 RXDATA_IN_A Connect to ball F12 H12 NC
G13 +3.3V_LOGIC H13 NC
G14 +3.3V_LOGIC H14 NC
G15 NC H15 NC
G16 NC H16 NC
G17 GND_LOGIC H17 GND_LOGIC
G18 GND_LOGIC H18 GND_LOGIC
G19 GND_LOGIC H19 GND_LOGIC
G20 NC H20 GND_LOGIC
G21 D03 H21 INCMD
G22 D05 H22 D01
G23 D06 H23 D02
G24 D04 H24 D00 (LSB)
Continued ...
HOLT INTEGRATED CIRCUITS67
Pin Descriptions
Ball Signal Notes Ball Signal Notes
J1 NC / CHB_1553-D K1 CHB_1553
J2 NC / CHB_1553-D K2 CHB_1553
J3 NC / CHB_1553-D K3 CHB_1553
J4 NC / CHB_1553-D K4 NC / CHB_1553-D
J5 NC K5 NC
J6 NC K6 NC
J7 NC K7 NC
J8 NC K8 GND_XCVR/THERMAL
J9 GND_XCVR/THERMAL K9 GND_XCVR/THERMAL
J10 GND_XCVR/THERMAL K10 GND_XCVR/THERMAL
J11 GND_XCVR/THERMAL K11 GND_XCVR/THERMAL
J12 NC K12 +3.3V_XCVR
J13 NC K13 NC
J14 MSB / LSB / DTGRT K14 SSFLAG / EXT_TRIG
J15 NC K15 NC
J16 TXDATA_IN_B Connect to ball K16 K16 TXDATA_OUT_B Connect to ball J16
J17 GND_LOGIC K17 NC
J18 GND_LOGIC K18 TXDATA_IN_B Connect to ball K19
J19 GND_LOGIC K19 TXDATA_OUT_B Connect to ball K18
J20 GND_LOGIC K20 NC
J21 RTAD4 (MSB) K21 RTAD0 (LSB)
J22 RTAD2 K22 RSTBITEN
J23 RTADP K23 RTAD1
J24 RTAD3 K24 RT_AD_LAT
Continued ...
Pin Descriptions
HOLT INTEGRATED CIRCUITS68
Ball Signal Notes Ball Signal Notes
L1 NC M1 GND_XCVR
L2 NC M2 GND_XCVR
L3 NC M3 GND_XCVR
L4 NC M4 NC
L5 NC M5 NC
L6 +3.3V_XCVR M6 +3.3V_XCVR
L7 +3.3V_XCVR M7 +3.3V_XCVR
L8 GND_XCVR/THERMAL M8 NC
L9 GND_XCVR/THERMAL M9 GND_XCVR/THERMAL
L10 GND_XCVR/THERMAL M10 GND_XCVR/THERMAL
L11 GND_XCVR/THERMAL M11 GND_XCVR/THERMAL
L12 +3.3V_XCVR M12 RXDATA_OUT_B Connect to ball M13
L13 NC M13 RXDATA_IN_B Connect to ball M12
L14 GND_LOGIC M14 GND_LOGIC
L15 GND_LOGIC M15 GND_LOGIC
L16 ADDR_LAT / MEMOE M16 +3.3V_LOGIC
L17 16 / 8 / DTREQ M17 +3.3V_LOGIC
L18 NC M18 TRIG_SEL / MEMENA_IN
L19 NC M19 TXINH_OUT_B Connect to ball M20
L20 NC M20 TXINH_IN_B Connect to ball M19
L21 NC M21 NC
L22 GND_LOGIC M22 GND_LOGIC
L23 GND_LOGIC M23 GND_LOGIC
L24 GND_LOGIC M24 GND_LOGIC
Continued ...
HOLT INTEGRATED CIRCUITS69
Pin Descriptions
Ball Signal Notes
N1 GND_XCVR
N2 GND_XCVR
N3 GND_XCVR
N4 NC
N5 NC
N6 NC
N7 NC
N8 NC
N9 +3.3V_XCVR
N10 NC
N11 NC
N12 RXDATA_OUT_B Connect to ball N13
N13 RXDATA_IN_B Connect to ball N12
N14 NC
N15 NC
N16 ZEROWAIT / MEMWR
N17 POL_SEL / DTACK
N18 CLOCK_IN
N19 +3.3V_LOGIC
N20 +3.3V_LOGIC
N21 NC
N22 GND_LOGIC
N23 GND_LOGIC
N24 GND_LOGIC
Electrical Characteristics
HOLT INTEGRATED CIRCUITS70
6. Electrical Characteristics
6.1. Absolute Maximum Ratings
Supply voltages
Logic -0.3 V to +6.0 V
Transceivers (not transmitting) -0.3 V to +6.0 V
Transceivers (transmitting) -0.3 V to +4.5 V
Logic input voltage range -0.3 V to +6.0 V
Receiver differential voltage 10 Vp-p
Power dissipation at 25°C 1.0W
Solder Temperature (reflow) 260oC
Junction Temperature 175oC
Storage Temperature -65oC to +150oC
6.2. Recommended Operating Conditions
ParametersLimits
UnitMin Typ Max
Supply VoltagesLogic 3.0 3.3 3.6 V
Transceivers 3.14 3.3 3.46 V
Temperature RangeIndustrial -40 85 oC
Extended -55 125 oC
HOLT INTEGRATED CIRCUITS71
Electrical Characteristics
6.3. DC Electrical Characteristics
Unless otherwise stated, VDD = 3.3V, GND = 0V, TA = Operating Temperature Range
Parameters Symbol ConditionsLimits
UnitMin Typ Max
Power Supply
Operating Supply VoltagesLogic VLogic 3.0 3.3 3.6 V
Transceivers VDD 3.14 3.3 3.46 V
Power Supply Current See Note 1
ICC1 Not Transmitting - 10 15 mA
ICC2 Continuous supply current while one bus transmits @ 50% duty
cycle, 70Ω resistive load- 365 380 mA
ICC23Continuous supply current while one bus transmits @ 100% duty
cycle, 70Ω resistive load- 685 700 mA
Power Dissipation See Note 2
PD1 Not Transmitting - - 60 mW
PD2Transmit one bus @ 50% duty
cycle, 70Ω resistive load - 380 500 mW
PD3Transmit one bus @ 100% duty
cycle, 70Ω resistive load - 510 680 mW
Logic
Input Voltage (High) VIHAll digital inputs, except CLKIN 2.1 - - V
CLKIN 0.8 VDD
Input Voltage (Low) VILAll digital inputs, except CLKIN - - 0.7 V
CLKIN 0.2 VDD
Input Current (High) IIH
All digital inputs, except CLKINVLOGIC = 3.6V, VIH = 2.5V
-100 - -10 μA
CLKIN -10 - 10 μA
Input Current (Low) IIL
All digital inputs, except CLKINVLOGIC = 3.6V, VIL = 0V
-100 - -20 μA
CLKIN -10 - 10 μA
Output Voltage (High) VOHVLOGIC = 3.0V, VIH = 2.7V,
VIL = 0.2V, IOH = max2.4 - - V
Output Voltage (Low) VOLVLOGIC = 3.0V, VIH = 2.7V,
VIL = 0.2V, IOL = max- - 0.5 V
Output Current (High) IOH VLOGIC = 3.0V - - -2.2 mA
Output Current (Low) IOL VLOGIC = 3.0V 2.2 - - mA
RECEIVER (Measured at Point “AD” in Figure 4 unless otherwise specified)
Input Resistance RIN Differential 20 - - kΩ
Input Capacitance CIN Differential - - 5 pF
Electrical Characteristics
HOLT INTEGRATED CIRCUITS72
Parameters Symbol ConditionsLimits
UnitMin Typ Max
Common Mode Rejection Ratio CMRR 40 - - dB
Input Level VIN Differential - - 9 Vp-p
Input Common Mode Voltage VICM -10 - +10 V-pk
Threshold Voltage (Direct-Coupled)
Detect VTHD 1 MHz Sine Wave (Measured at Point “AD“ in Figure 4)
1.2 - 20.0 Vp-p
No Detect VTHND - - 0.28 Vp-p
Threshold Voltage (Transformer-Coupled)
Detect VTHD 1 MHz Sine Wave (Measured at Point “AT“ in Figure 5)
0.86 - 14.0 Vp-p
No Detect VTHND - - 0.2 Vp-p
TRANSMITTER (Measured at Point “AD” in Figure 4 unless otherwise specified)
Output Voltage
Direct Coupled VOUT 35Ω Load 6.0 7.2 9.0 Vp-p
Transformer Coupled VOUT70Ω Load (Measured at Point
“AT“ in Figure 5) 20.0 21.5 27.0 Vp-p
Output Noise VON Differential, inhibited - - 14.0 mVRMS
Output Dynamic Offset Voltage
Direct Coupled VDYN 35Ω Load -90 - 90 mV
Transformer Coupled VDYN70Ω Load (Measured at Point
“AT“ in Figure 5) -250 - 250 mVp
Rise/Fall Time tr/f 100 150 300 ns
Output Resistance ROUT Differential,