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m
t Time/Counters
Eig
ION:
PIN DESCRIPTION
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BLOCK DIAGRAM OF MICROCONTROLLER
or.
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address locations
First line 80 81 82 83 84 85 86
troug 8F
!econd line C0 C1 C2 C3 C4 C5 C6
troug CF
"ogic status on control lines:
E # 0 $ccess to "C% disa&led # 1 $ccess to "C% ena&led
'/( # 0 )riting data to "C% # 1 'eading data *rom "C%
'! # 0 +nstructions # 1 Caracter
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PIN DESCRIPTION
COMMANDS OF LCD :
Code ,-e Command to "C% instruction 'egister
1 Clear disla screen
2 'eturn ome
4 %ecrement cursor,si*t cursor to le*t
6 +ncrement cursor,si*t cursor to rigt
5 !i*t disla rigt !i*t disla le*t
8 %isla o** Cursor o**
$ %isla o** Cursor on
C %isla on Cursor o**
E %isla on Cursor &lining
F %isla on Cursor &lining
+ !79" +/ %E!C'+T+
1 ;ss ## 0 to select command register '!>1 to
select data register
5 '/( + '(>0 *or )rite '(>1 *or delete6 E +/ Ena&le
%90 +/ 8#&it data &us
8 %91 +/ 8#&it data &us
? %92 +/ 8#&it data &us
10 %93 +/ 8#&it data &us
11 %94 +/ 8#&it data &us
12 %95 +/ 8#&it data &us
13 %96 +/ 8#&it data &us
14 %9 +/ 8#&it data &us
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10 !i*t cursor osition to le*t
14 !i*t cursor osition to rigt
18 !i*t te entire disla to te le*t
1C !i*t te entire disla to te rigt
80 Force cursor to te &eginning o* te *irst line
C0 Force cursor to te &eginning o* te second line
555 TIMER
$ll +C timers rel uon an eternal
caacitor to determine te o**#on
time inter@als o* te outut ulses.
$s ou recall *rom our stud o*
&asic electronics it taes a *inite
eriod o* time *or a caacitor ,C to
carge or discarge troug aresistor ,'. Tose times are clearl
de*ined and can &e calculated gi@en
te @alues o* resistance and
caacitance.
Te &asic 'C carging circuit isso)n in *ig. 4. $ssume tat te
caacitor is initiall discarged.
(en te s)itc is closed te
caacitor &egins to carge troug
te resistor. Te @oltage across tecaacitor rises *rom Aero u to te@alue o* te alied %C @oltage. Te carge cur@e *or te circuit is so)n in *ig.
6. Te time tat it taes *or te caacitor to carge to 63.B o* te alied @oltage
is no)n as te time constant ,t. Tat time can &e calculated )it te simle
eression:
t = R X C
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Definition of Pin Function:
'e*er to te internal 555 scematic o* Fig. 4#2
Pin ! "G#oun$%: Te ground ,or common in is
te most#negati@e sul otential o* te de@ice
)ic is normall connected to circuit common,ground )en oerated *rom ositi@e sul
@oltages.
Pin & "T#i''e#%: Tis in is te inut to te
lo)er comarator and is used to set te latc
)ic in turn causes te outut to go ig. Tis iste &eginning o* te timing seuence in monosta&le oeration. Triggering is
accomlised & taing te in *rom a&o@e to &elo) a @oltage le@el o* 1/3 ;= ,or
in general one#al* te @oltage aearing at in 5. Te action o* te trigger inut
is le@el#sensiti@e allo)ing slo) rate#o*#cange )a@e*orms as )ell as ulses to &e
used as trigger sources. Te trigger ulse must &e o* sorter duration tan te time
inter@al determined & te eternal ' and C. +* tis in is eld lo) longer tantat te outut )ill remain ig until te trigger inut is dri@en ig again. ne
recaution tat sould &e o&ser@ed )it te trigger inut signal is tat it must not
remain lo)er tan 1/3 ;= *or a eriod o* time longer tan te timing ccle. +* tis
is allo)ed to aen te timer )ill re#trigger itsel* uon termination o* te *irst
outut ulse. Tus )en te timer is dri@en in te monosta&le mode )it inut
ulses longer tan te desired outut ulse )idt te inut trigger sould
e**ecti@el &e sortened & di**erentiation. Te minimum#allo)a&le ulse )idt
*or triggering is some)at deendent uon ulse le@el &ut in general i* it is
greater tan te 1u! ,micro#!econd triggering )ill &e relia&le. $ second
recaution )it resect to te trigger inut concerns storage time in te lo)ercomarator. Tis ortion o* te circuit can ei&it normal turn#o** delas o*
se@eral microseconds a*ter triggeringD tat is te latc can still a@e a trigger inut
*or tis eriod o* time a*ter te trigger ulse. +n ractice tis means te minimum
monosta&le outut ulse )idt sould &e in te order o* 10u! to re@ent ossi&le
dou&le triggering due to tis e**ect. Te @oltage range tat can sa*el &e alied to
te trigger in is &et)een ;= and ground. $ dc current termed te trigger current
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must also *lo) *rom tis terminal into te eternal circuit. Tis current is ticall
500n$ ,nano#am and )ill de*ine te uer limit o* resistance allo)a&le *rom in
2 to ground. For an asta&le con*iguration oerating at ;= > 5 @olts tis resistance
is 3 ega#omD it can &e greater *or iger ;= le@els.
Pin ( "Out)ut%: Te outut o* te 555 comes *rom a ig#current totem#ole
stage made u o* transistors 20 # 24. Transistors 21 and 22 ro@ide dri@e
*or source#te loads and teir %arlington connection ro@ides a ig#state outut
@oltage a&out 1. @olts less tan te ;= sul le@el used. Transistor 24 ro@ides
current#sining caa&ilit *or lo)#state loads re*erred to ;= ,suc as tical TT"inuts. Transistor 24 as a lo) saturation @oltage )ic allo)s it to inter*ace
directl )it good noise margin )en dri@ing current#sining logic. Eact outut
saturation le@els @ar maredl )it sul @oltage o)e@er *or &ot ig and
lo) states. $t a ;= o* 5 @olts *or instance te lo) state ;ce,sat is ticall 0.25
@olts at 5 m$. erating at 15 @olts o)e@er it can sin 200m$ i* an outut#lo)
@oltage le@el o* 2 @olts is allo)a&le ,o)er dissiation sould &e considered in
suc a case o* course. -ig#state le@el is ticall 3.3 @olts at ;= > 5 @oltsD 13.3
@olts at ;= > 15 @olts. 9ot te rise and *all times o* te outut )a@e*orm are
uite *ast tical s)itcing times &eing 100n!. Te state o* te outut in )ill
al)as re*lect te in@erse o* te logic state o* te latc and tis *act ma &e seen
& eamining Fig. 3. !ince te latc itsel* is not directl accessi&le tis
relationsi ma &e &est elained in terms o* latc#inut trigger conditions. To
trigger te outut to a ig condition te trigger inut is momentaril taen *roma iger to a lo)er le@el. see Gin 2 # TriggerGH. Tis causes te latc to &e set and
te outut to go ig. $ctuation o* te lo)er comarator is te onl manner in
)ic te outut can &e laced in te ig state. Te outut can &e returned to a
lo) state & causing te tresold to go *rom a lo)er to a iger le@el see Gin 6 #
TresoldGH )ic resets te latc. Te outut can also &e made to go lo) &
taing te reset to a lo) state near ground see Gin 4 # 'esetGH. Te outut @oltage
a@aila&le at tis in is aroimatel eual to te ;cc alied to in 8 minus 1.;.
Pin * "Reet%: Tis in is also used to reset te latc and return te outut to a
lo) state. Te reset @oltage tresold le@el is 0. @olt and a sin current o* 0.1m$*rom tis in is reuired to reset te de@ice. Tese le@els are relati@el
indeendent o* oerating ;= le@elD tus te reset inut is TT" comati&le *or an
sul @oltage. Te reset inut is an o@erriding *unctionD tat is it )ill *orce te
outut to a lo) state regardless o* te state o* eiter o* te oter inuts. +t ma tus
&e used to terminate an outut ulse rematurel to gate oscillations *rom GonG to
Go**G etc. %ela time *rom reset to outut is ticall on te order o* 0.5 I! and
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te minimum reset ulse )idt is 0.5 I!. eiter o* tese *igures is guaranteed
o)e@er and ma @ar *rom one manu*acturer to anoter. +n sort te reset in is
used to reset te *li#*lo tat controls te state o* outut in 3. Te in is
acti@ated )en a @oltage le@el an)ere &et)een 0 and 0.4 @olt is alied to te
in. Te reset in )ill *orce te outut to go lo) no matter )at state te oter
inuts to te *li#*lo are in. (en not used it is recommended tat te reset inut&e tied to ;= to a@oid an ossi&ilit o* *alse resetting.
Pin 5 "Cont#o+ ,o+t-'e%: Tis in allo)s direct access to te 2/3 ;= @oltage#
di@ider oint te re*erence le@el *or te uer comarator. +t also allo)s indirect
access to te lo)er comarator as tere is a 2:1 di@ider ,'8 # '? *rom tis oint
to te lo)er#comarator re*erence inut 13. Jse o* tis terminal is te otion o*
te user &ut it does allo) etreme *lei&ilit & ermitting modi*ication o* te
timing eriod resetting o* te comarator etc. (en te 555 timer is used in a
@oltage#controlled mode its @oltage#controlled oeration ranges *rom a&out 1 @olt
less tan ;= do)n to )itin 2 @olts o* ground ,altoug tis is not guaranteed.;oltages can &e sa*el alied outside tese limits &ut te sould &e con*ined
)itin te limits o* ;= and ground *or relia&ilit. 9 aling a @oltage to tis in
it is ossi&le to @ar te timing o* te de@ice indeendentl o* te 'C net)or.Te control @oltage ma &e @aried *rom 45 to ?0B o* te ;cc in te monosta&le
mode maing it ossi&le to control te )idt o* te outut ulse indeendentl o*
'C. (en it is used in te asta&le mode te control @oltage can &e @aried *rom
1.; to te *ull ;cc. ;aring te @oltage in te asta&le mode )ill roduce a
*reuenc modulated ,F outut. +n te e@ent te control#@oltage in is not used
it is recommended tat it &e &assed to ground )it a caacitor o* a&out 0.01uF
,10nF *or immunit to noise since it is a comarator inut. Tis *act is noto&@ious in man 555 circuits since + a@e seen man circuits )it Kno#in#5K
connected to anting &ut tis is te roer rocedure. Te small ceramic ca
ma eliminate *alse triggering.
Pin . "T/#e/o+$%: in 6 is one inut to te uer comarator ,te oter &eingin 5 and is used to reset te
latc )ic causes te outut to
go lo). 'esetting @ia tis
terminal is accomlised &
taing te terminal *rom &elo)
to a&o@e a @oltage le@el o* 2/3;= ,te normal @oltage on in
5. Te action o* te tresold
in is le@el sensiti@e allo)ing
slo) rate#o*#cange )a@e*orms.
Te @oltage range tat can sa*el &e alied to te tresold in is &et)een ;=
and ground. $ dc current termed te tresold current must also *lo) into tis
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terminal *rom te eternal circuit. Tis current is ticall 0.1I$ and )ill de*ine
te uer limit o* total resistance allo)a&le *rom in 6 to ;=. For eiter timing
con*iguration oerating at ;= > 5 @olts tis resistance is 16 ega#om. For 15
@olt oeration te maimum @alue o* resistance is 20 egams.
Pin 0 "Dic/-#'e%: Tis in is connected to te oen collector o* a nn transistor
,14 te emitter o* )ic goes to ground so tat )en te transistor is turnedGonG in is e**ecti@el sorted to ground. Jsuall te timing caacitor is
connected &et)een in and ground and is discarged )en te transistor turns
GonG. Te conduction state o* tis transistor is identical in timing to tat o* te
outut stage. +t is GonG ,lo) resistance to ground )en te outut is lo) and Go**G
,ig resistance to ground )en te outut is ig. +n &ot te monosta&le and
asta&le time modes tis transistor s)itc is used to clam te aroriate nodes o*
te timing net)or to ground. !aturation @oltage is ticall &elo) 100m; ,milli#;olt *or currents o* 5 m$ or
less and o**#state leaage is
a&out 20n$ ,tese arameters
are not seci*ied & all
manu*acturers o)[email protected] collector current is
internall limited & design
tere& remo@ing restrictions on
caacitor siAe due to ea ulse#
current discarge. +n certain
alications tis oen collector outut can &e used as an auiliar outut terminal)it current#sining caa&ilit similar to te outut ,in 3.
Pin 1 ", 2%: Te ;= in ,also re*erred to as ;cc is te ositi@e sul @oltage
terminal o* te 555 timer +C. !ul#@oltage oerating range *or te 555 is =4.5
@olts ,minimum to =16 @olts ,maimum and it is seci*ied *or oeration
&et)een =5 @olts and = 15 @olts. Te de@ice )ill oerate essentiall te same o@ertis range o* @oltages )itout cange in timing eriod. $ctuall te most
signi*icant oerational di**erence is te outut dri@e caa&ilit )ic increases *or
&ot current and @oltage range as te sul @oltage is increased. !ensiti@it o*
time inter@al to sul @oltage cange is lo) ticall 0.1B er @olt. Tere aresecial and militar de@ices a@aila&le tat oerate at @oltages as ig as 18 ;.
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O)e#-tin' Mo$e:Te 555 timer as t)o &asic oerational modes: one sot and
asta&le. +n te one#sot mode te 555 acts lie a monosta&le multi@i&rator. $
monosta&le is said to a@e a single sta&le state##tat is te o** state. (ene@er it is
triggered & an inut ulse te monosta&le s)itces to its temorar state. +t
remains in tat state *or a eriod o* time determined & an 'C net)or. +t tenreturns to its sta&le state. +n oter )ords te monosta&le circuit generates a single
ulse o* a *ied time duration eac time it recei@es and inut trigger ulse. Tus
te name one#sot. ne#sot multi@i&rators are used *or turning some circuit or
eternal comonent on or o** *or a seci*ic lengt o* time. +t is also used togenerate delas. (en multile one#sots are cascaded a @ariet o* seuential
timing ulses can &e generated. Tose ulses )ill allo) ou to time and seuencea num&er o* related oerations.
Te oter &asic oerational mode o* te 555 is as and asta&le multi@i&rator. $n
asta&le multi@i&rator is siml and oscillator. Te asta&le multi@i&rator generates a
continuous stream o* rectangular o**#on ulses tat s)itc &et)een t)o @oltage
le@els. Te *reuenc o* te ulses and teir dut ccle are deendent uon te 'Cnet)or @alues.
ne#!ot eration: Fig. 4 so)s te &asic circuit o* te 555 connected as a
monosta&le multi@i&rator. $n eternal 'C net)or is connected &et)een te
sul @oltage and ground. Te Lunction o* te resistor and caacitor is connected
to te tresold inut )ic is te inut to te uer comarator. Te internaldiscarge transistor is also connected to te Lunction o* te resistor and te
caacitor. $n inut trigger ulse is alied to te trigger inut )ic is te inut
to te lo)er comarator.
(it tat circuit con*iguration te control *li#*lo is initiall reset. Tere*ore te
outut @oltage is near Aero @olts. Te signal *rom te control *li#*lo causes T1 toconduct and act as a sort circuit across te eternal caacitor. For tat reason te
caacitor cannot carge. %uring tat time te inut to te uer comarator is
near Aero @olts causing te comarator outut to ee te control *li#*lo reset.
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Monot-3+e Mo$e:
Te 555 in *ig. ?a is so)n ere in itKs utmost &asic mode o* oerationD as a
triggered monosta&le. ne immediate o&ser@ation is te etreme simlicit o* tis
circuit. nl t)o comonents to mae u a timer a caacitor and a resistor. $nd
*or noise immunit ma&e a caacitor on in 5. %ue to te internal latcingmecanism o* te 555 te timer )ill al)as time#out once triggered regardless o*
an su&seuent noise ,suc as &ounce on te inut trigger ,in 2. Tis is a greatasset in inter*acing te 555 )it nois sources. Must in case ou donKt no) )at
K&ounceK is: &ounce is a te o* *ast sort term noise caused & a s)itc rela etc.
and ten iced u & te inut in.
Te trigger inut is initiall ig ,a&out 1/3 o* =;. (en a negati@e#going triggerulse is alied to te trigger inut ,see *ig. ?a te tresold on te lo)er
comarator is eceeded. Te lo)er comarator tere*ore sets te *li#*lo. Tat
causes T1 to cut o** acting as an oen circuit. Te setting o* te *li#*lo also
causes a ositi@e#going outut le@el )ic is te &eginning o* te outut timing
ulse.
Te caacitor no) &egins to carge troug te eternal resistor. $s soon as te
carge on te caacitor eual 2/3 o* te sul @oltage te uer comarator
triggers and resets te control *li#*lo. Tat terminates te outut ulse )ic
s)itces &ac to Aero. $t tis time T1 again conducts tere& discarging te
caacitor. +* a negati@e#going ulse is alied to te reset inut )ile te outut
ulse is ig it )ill &e terminated immediatel as tat ulse )ill reset te *li#*lo.
(ene@er a trigger ulse is alied to te inut te 555 )ill generate its single#
duration outut ulse. %eending uon te @alues o* eternal resistance and
caacitance used te outut timing ulse ma &e adLusted *rom aroimatel onemillisecond to as ig as on undred seconds. For time inter@als less tanaroimatel 1#millisecond it is recommended tat standard logic one#sots
designed *or narro) ulses &e used instead o* a 555 timer. +C timers are normall
used )ere long outut ulses are reuired. +n tis alication te duration o* te
outut ulse in seconds is aroimatel eual to:
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T = !4! R C "in econ$%
Te outut ulse )idt is de*ined & te a&o@e *ormula and )it relati@el *e)
restrictions timing comonents ',t and C,t can a@e a )ide range o* @alues.
Tere is actuall no teoretical uer limit on T ,outut ulse )idt onl
ractical ones. Te lo)er limit is 10u!. 7ou ma consider te range o* T to &e10u! to in*init &ounded onl & ' and C limits. !ecial ',t and C,t tecniues
allo) *or timing eriods o* das )ees and e@en monts i* so desired.
-o)e@er a reasona&le lo)er limit *or ',t is in te order o* a&out 10Nilo om
mainl *rom te standoint o* o)er econom. ,$ltoug ',t can &e lo)er tat
10N )itout arm tere is no need *or tis *rom te standoint o* acie@ing a
sort ulse )idt. $ ractical minimum *or C,t is a&out ?5FD &elo) tis te
stra e**ects o* caacitance &ecome noticea&le limiting accurac and
redicta&ilit. !ince it is o&@ious tat te roduct o* tese t)o minimums ields a
T tat is less te 10u! tere is muc *lei&ilit in te selection o* ',t and C,t.
Jsuall C,t is selected *irst to minimiAe siAe ,and eenseD ten ',t is cosen.
Te uer limit *or ',t is in te order o* a&out 15 ega om &ut sould &e less
tan tis i* all te accurac o* )ic te 555 is caa&le is to &e acie@ed. Tea&solute uer limit o* ',t is determined & te tresold current lus te
discarge leaage )en te oerating @oltage is =5 @olt. For eamle )it a
tresold lus leaage current o* 120n$ tis gi@es a maimum @alue o* 14 *or
',t ,@er otimistic @alue. $lso i* te C,t leaage current is suc tat te sum
o* te tresold current and te leaage current is in ecess o* 120 n$ te circuit
)ill ne@er time#out &ecause te uer tresold @oltage )ill not &e reaced.
Tere*ore it is good ractice to select a @alue *or ',t so tat )it a @oltage droo* 1/3 ;= across it te @alue sould &e 100 times more i* ractical.
!o it sould &e o&@ious tat te real limit to &e laced on C,t is its leaage not
itKs caacitance @alue since larger#@alue caacitors a@e iger leaages as a *act
o* li*e. "o)#leaage tes lie tantalum or are a@aila&le and re*erred *or
long timing eriods. !ometimes inut trigger source conditions can eist tat )illnecessitate some te o* signal conditioning to ensure comati&ilit )it te
triggering reuirements o* te 555. Tis can &e acie@ed & adding anoter
caacitor one or t)o resistors and a small signal diode to te inut to *orm a ulse
di**erentiator to sorten te inut trigger ulse to a )idt less tan 10u! ,in
general less tan T. Teir @alues and criterion are not criticalD te main one is
tat te )idt o* te resulting di**erentiated ulse ,a*ter C sould &e less tan tedesired outut ulse *or te eriod o* time it is &elo) te 1/3 ;= trigger le@el.
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At-3+e Mo$e :
Figure ?& so)s te 555 connected as an asta&le multi@i&rator. 9ot te triggerand tresold inuts ,ins 2 and 6 to te t)o comarators are connected togeter
and to te eternal caacitor. Te caacitor carges to)ard te sul @oltage
troug te t)o resistors '1 and '2. Te discarge in , connected to te
internal transistor is connected to te Lunction o* tose t)o resistors.(en o)er is *irst alied to te circuit te caacitor )ill &e uncarged
tere*ore &ot te trigger and tresold inuts )ill &e near Aero @olts ,see Fig.10. Te lo)er comarator sets te control *li#*lo causing te outut to s)itc
ig. Tat also turns o** transistor T1. Tat allo)s te caacitor to &egin carging
troug '1 and '2. $s soon as te carge on te caacitor reaces 2/3 o* te
sul @oltage te uer comarator )ill trigger causing te *li#*lo to reset.
Tat causes te outut to s)itc lo). Transistor T1 also conducts. Te e**ect o* T1
conducting causes resistor '2 to &e connected across te eternal caacitor.'esistor '2 is e**ecti@el connected to ground troug internal transistor T1. Te
result o* tat is tat te caacitor no) &egins to discarge troug '2.Te onl di**erence &et)een te single 555 dual 556 and uad 558 ,&ot 14#in
tes is te common o)er rail. For te rest e@erting remains te same as te
single @ersion 8#in 555.
$s soon as te @oltage across te caacitor reaces 1/3 o* te sul @oltage te
lo)er comarator is triggered. Tat again causes te control *li#*lo to set and te
outut to go ig. Transistor T1 cuts o** and again te caacitor &egins to carge.
Tat ccle continues to reeat )it te caacitor alternatel carging and
discarging as te comarators cause te *li#*lo to &e reeatedl set and reset.Te resulting outut is a continuous stream o* rectangular ulses.
Te *reuenc o* oeration o* te asta&le circuit is deendent uon te @alues o*
'1 '2 and C. Te *reuenc can &e calculated )it te *ormula:
f = !6"4.7( C "R! 2 & R&%%
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Te Freuenc * is in -A '1 and '2 are in oms and C is in *arads. Te time
duration &et)een ulses is no)n as te KeriodK and usuall designated )it a KtK.
Te ulse is on *or t1 seconds ten o** *or t2 seconds. Te total eriod ,t is t1 =
t2 ,see *ig. 10. Tat time inter@al is related to te *reuenc & te *amiliar
relationsi:
f = !6t o# t = !6f
Te time inter@als *or te on and o** ortions o* te outut deend uon te @alues
o* '1 and '2. Te ratio o* te time duration )en te outut ulse is ig to te
total eriod is no)n as te dut#ccle. Te dut#ccle can &e calculated )it te*ormula:
D = t!6t = "R! 2 R&% 6 "R! 2 &R&%
7ou can calculate t1 and t2 times )it te *ormulas &elo):
t! = 4.7("R!2R&%C
t& = 4.7( R& C
Te 555 )en connected as so)n in Fig. ?& can roduce dut#ccles in te
range o* aroimatel 55 to ?5B. $ dut#ccle o* 80B means tat te outut
ulse is on or ig *or 80B o* te total eriod. Te dut#ccle can &e adLusted &
@aring te @alues o* '1 and '2.
A))+ic-tion:
Tere are literall tousands o* di**erent )as tat te 555 can &e used in
electronic circuits. +n almost e@er case o)e@er te &asic circuit is eiter a one#
sot or an asta&le. Te alication usuall reuires a seci*ic ulse time duration
oeration *reuenc and dut#ccle. $dditional comonents ma a@e to &econnected to te 555 to inter*ace te de@ice to eternal circuits or de@ices. +n te
remainder o* tis eeriment ou )ill &uild &ot te one#sot and asta&le circuits
and learn a&out some o* te di**erent inds o* alications tat can &eimlemented. Furtermore te last age o* tis document contains 555 eamles
)ic ou can &uild and eeriment )it.
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C O M
A
B
N C
N O
RELA8
$ rela is an electricall oerated s)itc and actuall te
redecessor o* te transistor. !olenoids are relas also &ut te
@er large tes )ic carr uge amounts o* current. 'elas are
te smaller tes. 'elas come in tree tes: electro mecanicalsolid#state and so#called &rids )ic are a com&ination o* te
*irst t)o. Tere are also some secialiAed tes tat *all into
neiter categor &ut + )ill deal )it tem later in tis tutorial. "ets
tae electro#mecanical tes *irst te are a@aila&le in tree main
modelsD armature lunger and reed. Te $rmature 'elas are te
oldest &ut elegant. lent turns o* @er *ine magnet#)ire are )ound
around an iron core to *orm an electro#magnet. Te mo@a&le metal armature as
an electrical contact tat is ositioned o@er a *ied contact attaced to te rela*rame. $ sring olds te armature u so tat te mo@a&le and *ied contacts are
normall searated ,oen. (en te coil is energiAed it attracts te i@otingarmature and ulls it do)n closing ,mae te !!T contacts and comletes te
o)er circuit.
Tis rela dri@er &oosts te inut imedance )it
a regular 23?04 transistor. ;er common dri@er.
+t can dri@e a @ariet o* relas including a reed#
rela. Transistor 1 is a simle common#emitter
amli*ier tat increases te e**ecti@e sensiti@it o*
te 12 @olt rela coil a&out a 100 times or in
oter )ords te current gain *or tis circuit is100. Jsing tis setu reduces te rela sensiti@it
to a *e) @olts. '1 restricts te inut current to 1
to a sa*e limit ,te imedance is eual to te @alue
o* '1 lus 1N. %iodes %1 and %2 are EF damers and *ilter o** an saring
)en te rela de#energiAes.
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9-#$-#e info#m-tion
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COMPONENT ;SEDICS ;SED
icro#controller
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CAPACITORS
T)o Caacitance o* 103 ico *arad
T)o Caacitance o* 100 micro*arad
ne Caacitance o* 104ico *arad
ne Caacitance o* 24ico *arad
ne Caacitance o* 22 ico *arad
ne Caacitance o* 10 micro*aradne Caacitance o* 1000 micro*arad
ne Caacitance o* 0.4 micro*arad
Tree Caacitance o* 0.01 micro*aradne Caacitance o* 0.22micro*arad
ne Caacitance o* 10 micro*arad
MISCELLANEO;S:
C'7!T$" 1 # 11.05?2 -A Ceramic crstals *or icrocontrollerC'7!T$" 2 O 3.5?54 -P Crstal *or decoder
Trans*ormer # 230; rimar to 0#12; 500m$ !econdar Trans*ormer
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C+'CJ+T %+$
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CODING
RincludeGreg52.G
s*r dtm*data>0?0D //dtm* data on 0
s*r lcddata>0a0D //lcd data on 1
s&it lcdrs>085D //lcdrs on 3S0
s&it lcdr)>086D // 3S1
s&it lcden>08D //3S2
s&it lcd&us>0aD //1S
s&it eoc>0?3D //0S4
s&it acen>0&1D//2S5
s&it rl>0&5D //2S4
s&it rl1>0&4D //2S3
s&it rl2>0&3D //2S2
s&it rl3>0&2D //2S1
s&it ring>0&0D //2S6
@oid dela,unsigned intD // to ro@ide dela
@oid )dc,@oidD //to cec ass)ord
@oid eader,@oidD //to disla colgroL name
@oid rname,@oidD //disla roLect name
@oid rddata,@oidD //cec de@ice code *or door oen closecannel1 Q cannel
2
@oid disono*,unsigned carunsigned carD //disla on or o**@oid disdoroen,@oidD //disla door oen
@oid disdorclos,@oidD //disla door close
@oid init,@oidD
@oid lcdinit,@oidD
unsigned car datacon@,unsigned carD
@oid dis)do,@oid D
unsigned car c1cnt>0c2cnt>0dtm*cod*lag>0*lag1>0cnt>0D
Rde*ine mesg1 G !.;.C.E. GRde*ine mesg2 G +%'E G
Rde*ine mesg3 G 9+"E G
Rde*ine mesg4 G CT'" %' GRde*ine mesg5 G%E;E"E% 97 # G
Rde*ine mesg6 G'+7$ ;E% G
Rde*ine mesg G'+C-$ T+($'+ G
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Rde*ine mesg8 G'+T+N$ T+($'+ G
Rde*ine mesg? GETE' $!!('% G
Rde*ine mesg10 G$!!('% N G
Rde*ine mesg11 GC-$E" G
Rde*ine mesg12 G%' E G
Rde*ine mesg13 G%' C"!E GRde*ine mesg14 G-N FF G
Rde*ine mesg1? G'+< G
@oid dela,unsigned int n // 10 msec dela
unsigned int iD
unsigned int LD
*or,i>0DiUnDi==
*or,L>0DLU1200DL==//5
V
V V
@oid eader,@oid
unsigned car iD
lcdcomnd,0W01D //clear disla screen lcdcomnd,0W80D //cursor at line 1osition 1
*or,i>0DiU16Di==
lcddatar),mesg1iHD
dela,25D V
lcdcomnd,0C0D //cursor at line 2osition 1
*or,i>0DiU16Di==
lcddatar),mesg2iHD dela,25D
V
dela,100D
lcdcomnd,0W01D //clear disla screen
lcdcomnd,0W80D //cursor at line 1osition 1
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*or,i>0DiU16Di==
lcddatar),mesg3iHD
dela,25D
V
lcdcomnd,0C0D //cursor at line 1osition 1
*or,i>0DiU16Di==
lcddatar),mesg4iHD
dela,25D
V
dela,100D
lcdcomnd,0W01D //clear disla screenlcdcomnd,080D
*or,i>0DiU16Di==
lcddatar),mesg5iHD
dela,25D
V
lcdcomnd,0C0D //cursor at line 1osition 1
*or,i>0DiU16Di==
lcddatar),mesg6iHD
dela,25D
V
dela,100D
lcdcomnd,0W01D //clear disla screenlcdcomnd,080D
*or,i>0DiU16Di==
lcddatar),mesgiHD
dela,25D
V
lcdcomnd,0C0D //cursor at line 1osition 1
*or,i>0DiU16Di==
lcddatar),mesg8iHD
dela,25D
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V
dela,100D
lcdcomnd,0W01D //clear disla screen
V
@oid disdoroen,@oid
unsigned car iD
lcdcomnd,0W01D //clear disla screen
lcdcomnd,080D //cursor at + line + osition
*or,i>0DiU16Di== //disla ass)ord o
lcddatar),mesg12iHD
dela,10D
Vdela,100D
lcdcomnd,0W01D //clear disla screen
V
@oid disdorclos,@oid
unsigned car iD
lcdcomnd,0W01D //clear disla screen
lcdcomnd,080D //cursor at + line + osition
*or,i>0DiU16Di== //disla ass)ord o
lcddatar),mesg13iHD
dela,10D
V
dela,100Dlcdcomnd,0W01D //clear disla screen
V
@oid )dc,@oid
unsigned car is)d10HD lcdcomnd,0W01D //clear disla screen
lcdcomnd,080D
lcddatar),KKD
lcddatar),K)KD
lcddatar),KdKD
lcddatar),K>KD
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*or,i>0DiU10Di==
)ile,eoc>>0D //)ait *or e ressed
dtm*cod>dtm*data Q 0*0D //recei@e data
s)diH > datacon@,dtm*codD
lcddatar),KXKDacen>1D
dela,50D
acen>0D
V
dela,100D
i*,s)d0H>>002 Q s)d1H>>00a Q s)d2H>>00a Q s)d3H>>00? Q
s)d4H>>003 Q s)d5H>>005 Qs)d6H>>004 Q s)dH>>002 Q
s)d8H>>004 Q s)d?H>>003 //cec ass)ord,00 is o or not
acen>1D
dela,100D
acen>0Ddis)do,D //disla ass)ord o
rddata,D
V
V
@oid dis)do,@oid
unsigned car iD
lcdcomnd,0W01D //clear disla screen
lcdcomnd,080D //cursor at + line + osition
*or,i>0DiU16Di== //disla ass)ord o
lcddatar),mesg10iHD
dela,10D
V
dela,100D
V
@oid disout,@oid
unsigned car iD
lcdcomnd,0W01D //clear disla screen
lcdcomnd,080D //cursor at + line + osition
*or,i>0DiU16Di== //disla ass)ord o
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lcddatar),mesg14iHD
dela,10D
V
dela,100D
lcdcomnd,0W01D //clear disla screenV
@oid rddata,@oid
rl1>1D //motor sul
rl2>0D //motor direction c)/cc)
dela,150D
rl1>0D
rl2>0D
acen>1D
dela,50D
acen>0D
)ile,1
)ile,eoc>>0D
dtm*cod>dtm*data Q 0*0D
dtm*cod>datacon@,dtm*codD
i*,dtm*cod>>00C //door close ,R
rl1>1D
rl2>1D dela,200D
rl1>0D
rl2>0D
disdorclos,D
lcdcomnd,001D rl>0D
disout,D
&reaD
V
V
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V
unsigned car datacon@,unsigned car tem
i*,tem>>050
tem>0W00Delse i*,tem>>080
tem>001D
else i*,tem>>040
tem>002D
else i*,tem>>0C0
tem>003D
else i*,tem>>020
tem>004D
else i*,tem>>0$0
tem>005D else i*,tem>>060
tem>006D
else i*,tem>>0E0 tem>00D
else i*,tem>>010
tem>008D
else i*,tem>>0?0
tem>00?D
else i*,tem>>0d0 //code *or X
tem>00&Delse i*,tem>>030 //code *or R
tem>00cD
return,temD
V
@oid lcdinit,@oid
lcdcomnd,038D //initialiAe "C% 2 line 5X matri
lcdcomnd,00eD // disla on cursor on
lcdcomnd,001D //clear lcd
lcdcomnd,006D //si*t cursor rigtV
@oid init,@oid
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lcd&us>1D
dtm*data>0**D
ring>1D
eoc>1D
acen>0D rl>0D
rl1>0D
rl2>0D
V
@oid main,@oid
unsigned car i>0e12H>0>0rc@cod>0data&>0D
init,Dlcdinit,D
eader,D
lcdcomnd,080D)ile,1
i*,eoc>>1
rc@cod > dtm*data Q 0*0D
eiH>datacon@,rc@codD
eiH>eiH Y 030D
dela,8D // 8 )/o no. dis
i==D
i*,i>>10
i*,,e0H>>03? Q ,e1H>>033 Q ,e2H>>030 Q
,e3H>>031 Q ,e4H>>03? Q ,e5H>>035 Q ,e6H>>03? Q
,eH>>035 Q ,e8H>>030 Q ,e?H>>030
rl>1D //?301?5?500
)ile,eoc>>0D //)ait *or e ressed dtm*cod>dtm*data Q 0*0D //recei@e data
data& > datacon@,dtm*codD
i*,data&>>00&
)dc,D
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V
else
rl>0D
>1D
V else
>1D
lcdcomnd,001D
lcdcomnd,080D
lcddatar),e0HD
lcddatar),e1HD
lcddatar),e2HD
lcdda lcddatar),e?HD
dela,250D V
V
i*,>>1
i>0D
>0D
V
V
VV
tar),e3HD lcddatar),e4HD
lcddatar),e5HD
lcddatar),e6HD
lcddatar),eHD
lcddatar),e8HD
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DATA S9EETS
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;-'e Futu#e A)ect
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APPLICATIONS
Tis microcontroller &ased em&edded sstem is uite use*ul Q economical *or
todaZs automatic and remote alications. Te main teme o* tis roLect is to
control te oeration o* door using a seci*ic mo&ile one tat act as te e *orte sstem. 9 using te &asic idea o* tis roLect )e can also construct man
use*ul sstems.
!ome o* its alications are:
1. -igl secure sstem:
+t is &asicall designed *or securit urose.
For eamle: +n &ans )ere te locers o* customer a@e dou&le locing sstem.
+n tat case one o* te loc can &e tis sstem.
2. 9EW: ersonall 9ranced Teleone Ecange:
9 using tis roLect )e can construct
ersonall &ranced teleone ecange +n man o* te 9EW )e see in te
o**ices reuire one oerator to di@ert te incoming calls to te resecti@e internal
teleone line. -ere it does not reuire an suc oerator to oerate tis ecange.
Te erson *rom a remote section can ress te etension num&er to get connected
to te resecti@e num&er. +n tis te o* 9EW onl 12 etensions can &e used.
3. Controlling aliances remotel:
+n certain cases )en )e need to control an ind o* aliance ma &e at
ome or at o**ice tis sstem is o* great utilit. ne can also /FF a
de@ice &e*ore in and )en reuired.
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CONCL;SION
Tis roLect consists o* a control unit troug )ic ou can control our
door. +t contains one teleone line and a "ocal Control !ection.Te door )ic is to &e controlled must &e connected to teleone line
troug control unit. Control unit is et )it a su**icient &acu.
Te main art o* te circuit is ser@ed & +C T880 tat acts as a %TF
decoder. Tis +C taes %TF signal coming *rom te one and con@erts te
signals into resecti@e 9C% num&er.
Te main teme o* tis roLect is to control te door o* omes and o**ices
using a mo&ile one *or securit urose Q tis is tried to &e satis*actoril
acie@ed. -ere te securit is maintained & gi@ing a seci*ic code tat )ill&e no)n & te user onl.
+t is a uniue sstem in itsel* Q is sel* comlete in case o* securit as
reuired. Furter ' Q % in tis direction )ould ield muc more ad@anced
sstem )it etra *eatures.
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BIBLIOGRAP98
Boo>:
1. icro Electronics $nalog Communication -and&oo# +TE"
!emiconductors
2. Electronics roLects# '..arston
3. Teleone roLects *or Electronic Eeriments
4. #$ms Q "inear +ntegrated Circuits# 'amaant