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A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile µP Platforms
Custom Integrated Circuits Conference (CICC) 2005
Michael S. McCorquodale, Ph.D.Mobius Microsystems, Inc.
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Outline
Introduction
Background
Clock synthesizer reference oscillator and architecture
Experimental results
Conclusions and future work
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Introduction
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Introduction
Much recent work exploring alternative technologies to XTALs for clock generation and frequency synthesis
MEMS microresonators
FBAR
Insufficient exploration of all-Si CMOS approaches
Build on recent work in free-running and open-loop compensation of LC oscillators as frequency references for clock generation
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Introduction
Goals Develop an accurate and stable clock synthesizer without an external
frequency reference (i.e. XTAL or ceramic resonator)
Develop a clock synthesizer with very low frequency scaling latency
Develop a clock synthesizer with very low start-up latency
Characterize performance over PVT
Demonstrate in a multi-chip module
Approach Explore free-running RF LC oscillators as frequency references
Utilize a “top-down” synthesis architecture
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Background
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Architecture
Reference oscillator Free-running high-Q LC oscillator at a high frequency
Simple frequency trimming interface
Open loop compensation to stabilize over PVT
Very low phase noise
Very low start-up latency
Clock synthesis Divide down to target clock frequencies
Decrease phase noise by 20log10(N) for divide by N
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Background
iic
-g m
+ _
+_
RL
L C
v+_
RCRo
Ro
tgm0
i(t)
t
ic(t)
Resonant frequency
Sources of frequency drift
Real losses: RL and RC
Frequency modulation from harmonic content of driving amplifier
Filter response of LC network and amplifier output resistance
L
CR
LCLCR
LCR
LCL
C
Lo
2
2
2
111
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Background
fo vs. gm relationship
gmo → minimum gm for start-up
fo → decreases as gm increases (harmonic content increases)
fmin → approached as harmonic content approaches square wave
Can utilize harmonic modulation to self-compensate drift by modulating gm through bias current
No oscillation
fo
gmgmo
fmax
fmin
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Clock Synthesizer Reference Oscillator and Architecture
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Reference Oscillator
vcal
R
+out
6.1nH
0.8-2.5pF
R
out-
50k
50k
300A
MRn
MRn
MRp
250
0.52.5m
0.5
430
0.53430
0.53
215
0.53
215
0.53
0.8-2.5pF
3pF
R
Complementary cross-coupled architecture with PMOS tail for low phase noise
Bias current, temperature dependent and scaled by ~10x in mirror
Resistor divider self-biases control voltage and reduces VDD sensitivity
vcal trims frequency
Reset transistors disable oscillator
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Architecture
÷2BUF1
0
÷8 Out
Out
S
1.056GHz528MHz
66MHz
50MHz
vcal
EN1
EN0
R ÷10
“Top-down” or divisive architecture reduces phase noise and period jitter of reference oscillator by 20log10(N) and sqrt(N)
RF reference oscillator can be started with low latency
Any available frequency can be selected asynchronously: low scaling latency
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Experimental Results
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Die Micrograph
Fabricated in IBM’s 0.18m 7RF-CMOS process
Core macro size: <0.4mm2
Test macros populate periphery
Output drivers drive 10pF with 100ps rise/fall times at 20mArms
Wire-bonded and characterized in 16-pin ceramic DIP
Au studs for flip-chip module assembly
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Temperature and Voltage Drift
VDD±10%
25°C: ±0.17%
100°C: ±0.33%
Temperature
0 – 70°C: ±0.75%
-40 – 100°C: ±1.5%
PVT Total
Best: <±1%
Worst: ~±1.5%
Temp. compensation
Under-compensated
1.6mV/°C, R2 = 0.9984
-40 -20 0 20 40 60 80 1000.55
0.6
0.65
0.7
0.75
0.8
v cal R
equi
red
to k
eep
f o Con
stan
t (V
)
-40 -20 0 20 40 60 80 100-2
-1.5
-1
-0.5
0
0.5
1
1.5
Nor
mal
ized
Fre
quen
cy D
rift,
f/
f o (%
)
Temperature (C)
VDD = 1.98V
VDD = 1.80V
VDD = 1.62V
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Start-up Latency
3.2s
Measured 3.2s start-up latency from leakage only power state
Latency originates primarily from bias start-up time
Bias circuitry can be modified to reduce latency to ~ns
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Period Jitter
Measured with Agilent Infinium 4GSa/s scope
250k samples per edge
66MHz clock measurement shown
RMS jitter determined by removing trigger jitter
psrmsJ 214.343.40 22
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Performance Summary
Parameter Measured UnitPower supply voltage (nom./min.) 1.8/1.12 V
Power supply current (VDD = 1.8V/1.12V) 5.1/3.5 mA
Standby power supply current (VDD = 1.8V) 300 nA
Power dissipation (VDD = 1.8V) 9.2 mW
Output frequencies
49.5 – 56.2
61.9 – 70.2
495.2 – 561.6
MHz
Frequency calibration (tuning) range ±6.2 %
RMS period jitter (528/66/50 MHz output) 7.4/21/33 ps
Temperature frequency drift (-40 to 100°C) ±1.5 %
Power supply frequency drift (VDD ±10%) ±0.33 %
Total freq. accuracy (process, voltage, temp.) ±1.8 %
Start-up latency 3.2 s
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Conclusions and Future Work
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Conclusions and Future Work
Demonstrated a self-referenced LC clock synthesizer with no external reference
Low jitter and scaling/start-up latency
Low overall drift, though drift under-compensated
Temperature compensation correction linear
Alternative compensation techniques already in Si Very high total accuracy over PVT to be reported soon
Potentially an all-Si approach to stable and accurate clock synthesis
Never underestimate what can be done with CMOS alone
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Questions welcome