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NON-MULTIPLEXED MODES
8-BIT DATA BUS
16-BIT DATA BUS 32-BIT DATA BUS ISOLATION
8-BIT DATA
L4 EMB_AD00 D0 D0 D0 D0 D0 A0 A0 D0
L3 EMB_AD01 D1 D1 D1 D1 D1 A1 A1 D1
L2 EMB_AD02 D2 D2 D2 D2 D2 A2 A2 D2
L1 EMB_AD03 D3 D3 D3 D3 D3 A3 A3 D3
M5 EMB_AD04 D4 D4 D4 D4 D4 A4 A4 D4
M3 EMB_AD05 D5 D5 D5 D5 D5 A5 A5 D5
M1 EMB_AD06 D6 D6 D6 D6 D6 A6 A6 D6
N4 EMB_AD0 D D D D D A A DN3 EMB_AD08 A0 D8 D8 D8 D8 A8 A8 0
N2 EMB_AD0! A1 D! D! D! D! A! A! 0
N1 EMB_AD10 A2 D10 D10 D10 D10 A10 A10 0
P3 EMB_AD11 A3 D11 D11 D11 D11 A11 A11 0
P5 EMB_AD12 A4 D12 D12 D12 D12 A12 A12 0
P4 EMB_AD13 A5 D13 D13 D13 D13 A13 A13 0
P2 EMB_AD14 A6 D14 D14 D14 D14 A14 A14 0
P1 EMB_AD15 A D15 D15 D15 D15 A15 A15 0
R3 EMB_AD16 A8 A0 A1 D16 D16 A16 A16 0
R1 EMB_AD1 A! A1 A2 D1 D1 A1 A1 0
T2 EMB_AD18 A10 A2 A3 D18 D18 A18 A18 0
R5 EMB_AD1! A11 A3 A4 D1! D1! A1! A1! 0
T3 EMB_AD20 A12 A4 A5 D20 D20 A20 A20 0
T4 EMB_AD21 A13 A5 A6 D21 D21 A21 A21 0
T1 EMB_AD22 A14 A6 A D22 D22 A22 A22 0 T5 EMB_AD23 A15 A A8 D23 D23 A23 A23 0
U3 EMB_AD24 A16 A8 A! D24 D24 A24 A24 0
U1 EMB_AD25 A1 A! A10 D25 D25 A25 A25 0
"1 EMB_AD26 A18 A10 A11 D26 D26 A26 A26 0
"2 EMB_AD2 A1! A11 A12 D2 D2 A2 A2 0
"3 EMB_AD28 A20 A12 A13 D28 D28 A28 A28 0
U5 EMB_AD2! A21 A13 A14 D2! D2! A2! A2! 0
"4 EMB_AD30 A22 A14 A15 D30 D30 A30 A30 0
W1 EMB_AD31 A23 A15 A16 D31 D31 A31 A31 0
W2 EMB_AX00 (ALE) A24 A16 A1 A0 A2 ALE ALE ALE
"5 EMB_AX01 (TSI#0) A25 A1 A18 A1 A3 TSI#0 TSI#0 TSI#0
W3 EMB_AX02 (TSI#1) A26 A18 A1! A2 A4 TSI#1 TSI#1 TSI#1
W4 LP$_AX03 (TS) A2 A1! A20 A3 A5 1 1 TS
G2 LP$_AX04 A28 A20 A21 A4 A6 %&' 0 %&' 0 %&' 0
G3 LP$_AX05 A2! A21 A22 A5 A %&' 0 %&' 0 %&' 0H5 LP$_AX06 A30 A22 A23 A6 A8 %&' 0 %&' 0 %&' 0
*2 LP$_AX0 A31 A23 A24 A A! %&' 0 %&' 0 %&' 0
H1 LP$_AX08 %&' 0 A24 A25 A8 A10 %&' 0 %&' 0 %&' 0
G4 LP$_AX0! %&' 0 A25 A26 A! A11 %&' 0 %&' 0 %&' 0
8-BIT DATABUS
ADDRESSPHASE
8-BIT DATPHASE
B+TEADDRESS
SHORTADDRESS
B+TEADDRESS
WORDADDRESS
N&,. LP$_&:'
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P N
>UN$TION 1 I?O >UN$TION 2 I?O >UN$TION 3 I?O >UN$TION 4 I?O$1! $AN1_RX I @ @ @ @ @ @
A18 $AN1_TX O @ @ @ @ GPIO6 I?O
B1! $AN2_RX I @ @ @ @ @ @
E16 $AN2_TX O @ @ @ @ GPIO8 I?O
+26 $STP_OUT O TPA O @ @ @ @
L4 EMB_AD00 I?O @ @ @ @ @ @
L3 EMB_AD01 I?O @ @ @ @ @ @
L2 EMB_AD02 I?O @ @ @ @ @ @
L1 EMB_AD03 I?O @ @ @ @ @ @
M5 EMB_AD04 I?O @ @ @ @ @ @
M3 EMB_AD05 I?O @ @ @ @ @ @
M1 EMB_AD06 I?O @ @ @ @ @ @
N4 EMB_AD0 I?O @ @ @ @ @ @
N3 EMB_AD08 I?O @ @ @ @ @ @
N2 EMB_AD0! I?O @ @ @ @ @ @N1 EMB_AD10 I?O @ @ @ @ @ @
P3 EMB_AD11 I?O @ @ @ @ @ @
P5 EMB_AD12 I?O @ @ @ @ @ @
P4 EMB_AD13 I?O @ @ @ @ @ @
P2 EMB_AD14 I?O @ @ @ @ @ @
P1 EMB_AD15 I?O @ @ @ @ @ @
R3 EMB_AD16 I?O @ @ @ @ @ @
R1 EMB_AD1 I?O @ @ @ @ @ @
T2 EMB_AD18 I?O @ @ @ @ @ @
R5 EMB_AD1! I?O @ @ @ @ @ @
T3 EMB_AD20 I?O @ @ @ @ @ @
T4 EMB_AD21 I?O @ @ @ @ @ @
T1 EMB_AD22 I?O @ @ @ @ @ @
T5 EMB_AD23 I?O @ @ @ @ @ @
U3 EMB_AD24 I?O @ @ @ @ @ @
U1 EMB_AD25 I?O @ @ @ @ @ @
"1 EMB_AD26 I?O @ @ @ @ @ @
"2 EMB_AD2 I?O @ @ @ @ @ @
"3 EMB_AD28 I?O @ @ @ @ @ @
U5 EMB_AD2! I?O @ @ @ @ @ @
"4 EMB_AD30 I?O @ @ @ @ @ @
W1 EMB_AD31 I?O @ @ @ @ @ @
W2 EMB_AX00 (ALE) O @ @ @ @ @ @
"5 EMB_AX01 (TSI#0) O @ @ @ @ GPIO3 I?O
W3 EMB_AX02 (TSI#1) O @ @ @ @ GPIO2 I?O
A1! GPIO28 I @ @ @ @ @ @
E1 GPIO2! I @ @ @ @ @ @
$18 GPIO30 I @ @ @ @ @ @
B18 GPIO31 I @ @ @ @ @ @
D18 HIB_MODE O @ @ @ @ @ @
W24 HRESET I?O @ @ @ @ @ @
A$23 I2$0_S$L I?O @ @ @ @ GPIO?GPT I?O
AD26 I2$0_SDA I?O @ @ @ @ GPIO1 I?O
AB22 I2$1_S$L I?O @ @ SPDI>_TX O GPIO2 I?O
AB23 I2$1_SDA I?O @ @ SPDI>_RX I GPIO3 I?O
A$25 I2$2_S$L I?O @ @ $AN4_TX @ GPIO4 I?O
AA22 I2$2_SDA I?O LP$_$S6 @ $AN4_RX @ GPIO5 I?O
A$26 IR0 I @ @ $AN3_TX @ GPIO4?GPT4 I?O
AB25 IR1 I SPDI>_TX$L I $AN3_RX @ GPIO5?GPT5 I?O
AA24 *1850_RX I $AN4_RX O LP$_$S6 O GPIO2 I?O
+22 *1850_TX O $AN4_TX I @ @ GPIO4 I?O
AA2 LP$_A$ I?O LP$_$S O @ @ GPIO24 I?O
W4 EMB_AX03 (TS) O @ @ GPIO1 I?O
AA4 LP$_$L O TPA O $STP_IN I @ @W5 LP$_$S0 0 @ @ GPIO25 I?O
+3 LP$_$S1 O SPDI>_TX$L I @ @ GPIO I?O
+1 LP$_$S2 O N>$_$E_1 O @ @ GPIO0 I?O
+5 LP$_OE O @ @ @ @ @ @
AA1 LP$_R?W O @ @ @ @ @ @
AD1 MA0 O @ @ @ @ @ @
AB16 MA1 O @ @ @ @ @ @
A>22 MA10 O @ @ @ @ @ @
A$1! MA11 O @ @ @ @ @ @
AE21 MA12 O @ @ @ @ @ @
AD20 MA13 O @ @ @ @ @ @
AB1! MA14 O @ @ @ @ @ @
AE22 MA15 O @ @ @ @ @ @
AE18 MA2 O @ @ @ @ @ @
A>20 MA3 O @ @ @ @ @ @AD18 MA4 O @ @ @ @ @ @
AB1 MA5 O @ @ @ @ @ @
AE1! MA6 O
N Note: RED coloring indicates that the indicated functionwill be available on the second tape out.
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P24 P$I_AD13 I?O @ @ >E$_RXD_3 I GPIO18 I?O
P25 P$I_AD14 I?O @ @ >E$_TXD_0 O GPIO1 I?O
N26 P$I_AD15 I?O @ @ >E$_TXD_1 O GPIO16 I?O
L22 P$I_AD16 I?O @ @ >E$_TXD_2 O GPIO15 I?O25 P$I_AD1 I?O @ @ >E$_TXD_3 O GPIO14 I?O
*26 P$I_AD18 I?O @ @ USB1_DIR I GPIO13 I?O
24 P$I_AD1! I?O @ @ USB1_$L I GPIO12 I?O
*25 P$I_AD20 I?O @ @ USB1_NEXT I GPIO11 I?O
H26 P$I_AD21 I?O @ @ USB1_STOP O GPIO10 I?O
23 P$I_AD22 I?O @ @ USB1_DATA0 I?O GPIO! I?O
*24 P$I_AD23 I?O @ @ USB1_DATA1 I?O GPIO8 I?O
H24 P$I_AD24 I?O @ @ USB1_DATA2 I?O GPIO I?O
*23 P$I_AD25 I?O @ @ USB1_DATA3 I?O GPIO6 I?O
G25 P$I_AD26 I?O @ @ USB1_DATA4 I?O GPIO5 I?O
*22 P$I_AD2 I?O @ @ USB1_DATA5 I?O GPIO4 I?O
>26 P$I_AD28 I?O @ @ USB1_DATA6 I?O GPIO3 I?O
G24 P$I_AD2! I?O @ @ USB1_DATA I?O GPIO2 I?O
>24 P$I_AD30 I?O USB0_DIR I DIU_LD23 O GPIO1 I?O
H22 P$I_AD31 I?O USB0_$L I DIU_LD22 O GPIO0 I?OP22 P$I_$?BE0 I?O USB0_DATA5 I?O DIU_LD03 O GPIO4 I?O
N24 P$I_$?BE1 I?O USB0_DATA4 I?O DIU_LD02 O GPIO5 I?O
L24 P$I_$?BE2 I?O USB0_DATA3 I?O DIU_LD00 O GPIO6 I?O
G26 P$I_$?BE3 I?O USB0_DATA2 I?O DIU_LD01 O GPIO I?O
$26 P$I_$L O @ @ DIU_LD14 O GPIO15 I?O
L26 P$I_DE"SEL I?O @ @ DIU_LD06 O GPIO1! I?O
M23 P$I_>RAME I?O @ @ DIU_LD10 O GPIO1 I?O
E25 P$I_GRANT0 I?O @ @ DIU_LD12 O GPIO12 I?O
G22 P$I_GRANT1 O @ @ DIU_LD1! O GPIO10 I?O
E24 P$I_GRANT2 O @ @ DIU_LD21 O GPIO8 I?O
22 P$I_IDSEL I?O @ @ DIU_LD0 O GPIO18 I?O
U23 P$I_INTA O USBPH+DBG_DATAO O DIU_LD15 O GPIO14 I?O
26 P$I_IRD+ I?O USB0_DATA I?O DIU_LD05 O GPIO20 I?O
N22 P$I_PAR I?O USB0_DATA0 I?O DIU_LD0! O GPIO23 I?O
M25 P$I_PERR I?O USB0_STOP O DIU_LD16 O GPIO24 I?O
G23 P$I_RE0 I?O @ @ DIU_LD11 O GPIO13 I?O
E26 P$I_RE1 I @ @ DIU_LD18 O GPIO11 I?O
D26 P$I_RE2 I @ @ DIU_LD20 O GPIO! I?O
>22 P$I_RST_OUT O @ @ DIU_LD13 O GPIO16 I?O
M26 P$I_SERR I?O USB0_NEXT I DIU_LD1 O GPIO25 I?O
M24 P$I_STOP I?O USB0_DATA1 I?O DIU_LD08 O GPIO22 I?O
M22 P$I_TRD+ I?O USB0_DATA6 I?O DIU_LD04 O GPIO21 I?O
W23 PORESET I @ @ @ @ @ @
D16 PS$0_0 I?O >E$_$OL I USB0_DATA I?O GPIO8 I?O
A1 PS$0_1 I?O >E$_TX_EN O USB0_DATA6 I?O GPIO! I?O
E15 PS$0_2 I?O >E$_TX_$L I USB0_DATA5 I?O GPIO10 I?O
$16 PS$0_3 I?O >E$_TXD_0 O USB0_DATA4 I?O GPIO11 I?O
B16 PS$0_4 I?O >E$_TXD_1 O USB0_DATA3 I?O GPIO0?GPT0 I?O
$13 PS$10_0 I?O @ @ DIU_LD11 O GPIO8 I?O
B13 PS$10_1 I?O @ @ DIU_LD12 O GPIO! I?O
A13 PS$10_2 I?O @ @ DIU_LD13 O GPIO10 I?O
$12 PS$10_3 I?O @ @ DIU_LD14 O GPIO11 I?O
E12 PS$10_4 I?O @ @ DIU_LD15 O GPIO2?GPT2 I?O
A12 PS$11_0 I?O @ @ DIU_LD18 O GPIO12 I?O
B11 PS$11_1 I?O @ @ DIU_LD1! O GPIO13 I?O
$11 PS$11_2 I?O @ @ DIU_LD20 O GPIO14 I?O
E11 PS$11_3 I?O @ @ DIU_LD21 O GPIO15 I?O
D11 PS$11_4 I?O USBPH+DBG_IDDIG O DIU_DE O GPIO3?GPT3 I?O
$15 PS$1_0 I?O >E$_TXD_2 O USB0_DATA2 I?O GPIO12 I?O
A16 PS$1_1 I?O >E$_TXD_3 O USB0_DATA1 I?O GPIO13 I?O
E14 PS$1_2 I?O >E$_MD$ O USB0_DATA0 I?O GPIO14 I?O
A15 PS$1_3 I?O >E$_RX_ER I USB0_STOP O GPIO15 I?O
D14 PS$1_4 I?O >E$_RXD_3 I USB0_NEXT I GPIO1?GPT1 I?O
$14 PS$2_0 I?O >E$_RXD_2 I USB0_$L I GPIO16 I?OB14 PS$2_1 I?O >E$_RXD_1 I USB0_DIR I GPIO1 I?O
E13 PS$2_2 I?O >E$_RXD_0 I @ @ GPIO18 I?O
A14 PS$2_3 I?O >E$_MDIO I?O @ @ GPIO1! I?O
D13 PS$2_4 I?O >E$_RX_$L I @ @ GPIO2?GPT2 I?O
A>3 PS$3_0 I?O USB1_DATA0 I?O @ @ GPIO20 I?O
AB5 PS$3_1 I?O USB1_DATA1 I?O @ @ GPIO21 I?O
A$4 PS$3_2 I?O USB1_DATA2 I?O @ @ GPIO22 I?O
AD4 PS$3_3 I?O USB1_DATA3 I?O @ @ GPIO23 I?O
A>4 PS$3_4 I?O @ @ @ @ GPIO3?GPT3 I?O
AB1 PS$4_0 I?O USB1_DATA4 I?O @ @ GPIO24 I?O
AA3 PS$4_1 I?O USB1_DATA5 I?O @ @ GPIO25 I?O
AB3 PS$4_2 I?O USB1_DATA6 I?O @ @ GPIO26 I?O
AA5 PS$4_3 I?O USB1_DATA I?O @ @ GPIO2 I?O
A$2 PS$4_4 I?O @ @ GPIO4?GPT4 I?O
A$1 PS$5_0 I?O USB1_$L I @ @ GPIO8 I?OA$3 PS$5_1 I?O USB1_NEXT I @ @ GPIO! I?O
AD1 PS$5_2 I?O USB1_STOP O @ @ GPIO10 I?O
AD2 PS$5 3 I?O USB1 DIR I GPIO11 I?O
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P N T/ &, :& S,&&% 1 (: , , &,)
>UN$TION 1 I?O >UN$TION 2 I?O >UN$TION 3 I?O >UN$TION 4 I?O
$1! $AN1_RX I @ @ @ @ @ @ U24
A18 $AN1_TX O @ @ @ @ GPIO6 I?O "26
B1! $AN2_RX I @ @ @ @ @ @ U25
E16 $AN2_TX O @ @ @ @ GPIO8 I?O R22
+26 $STP_OUT O TPA O @ @ @ @ U26
L4 EMB_AD00 I?O @ @ @ @ @ @ T24
L3 EMB_AD01 I?O @ @ @ @ @ @ R23
L2 EMB_AD02 I?O @ @ @ @ @ @ T26
L1 EMB_AD03 I?O @ @ @ @ @ @ R26
M5 EMB_AD04 I?O @ @ @ @ @ @ P23
M3 EMB_AD05 I?O @ @ @ @ @ @ R24
M1 EMB_AD06 I?O @ @ @ @ @ @ R25
N4 EMB_AD0 I?O @ @ @ @ @ @ P26N3 EMB_AD08 I?O @ @ @ @ @ @ P24
N2 EMB_AD0! I?O @ @ @ @ @ @ P25
N1 EMB_AD10 I?O @ @ @ @ @ @ N26
P3 EMB_AD11 I?O @ @ @ @ @ @ L22
P5 EMB_AD12 I?O @ @ @ @ @ @ 25
P4 EMB_AD13 I?O @ @ @ @ @ @ *26
P2 EMB_AD14 I?O @ @ @ @ @ @ 24
P1 EMB_AD15 I?O @ @ @ @ @ @ *25
R3 EMB_AD16 I?O @ @ @ @ @ @ H26
R1 EMB_AD1 I?O @ @ @ @ @ @ 23
T2 EMB_AD18 I?O @ @ @ @ @ @ *24
R5 EMB_AD1! I?O @ @ @ @ @ @ H24
T3 EMB_AD20 I?O @ @ @ @ @ @ *23
T4 EMB_AD21 I?O @ @ @ @ @ @ G25
T1 EMB_AD22 I?O @ @ @ @ @ @ *22
T5 EMB_AD23 I?O @ @ @ @ @ @ >26
U3 EMB_AD24 I?O @ @ @ @ @ @ G24
U1 EMB_AD25 I?O @ @ @ @ @ @ >24
"1 EMB_AD26 I?O @ @ @ @ @ @ H22
"2 EMB_AD2 I?O @ @ @ @ @ @ P22
"3 EMB_AD28 I?O @ @ @ @ @ @ N24
U5 EMB_AD2! I?O @ @ @ @ @ @ L24
"4 EMB_AD30 I?O @ @ @ @ @ @ G26
W1 EMB_AD31 I?O @ @ @ @ @ @ $26
W2 EMB_AX00 (ALE) O @ @ @ @ @ @ L26
"5 EMB_AX01 (TSI#0) O @ @ @ @ GPIO3 I?O M23
W3 EMB_AX02 (TSI#1) O @ @ @ @ GPIO2 I?O E25
A1! GPIO28 I @ @ @ @ @ @ G22
E1 GPIO2! I @ @ @ @ @ @ E24
$18 GPIO30 I @ @ @ @ @ @ 22
B18 GPIO31 I @ @ @ @ @ @ U23
D18 HIB_MODE O @ @ @ @ @ @ 26
W24 HRESET I?O @ @ @ @ @ @ N22
A$23 I2$0_S$L I?O @ @ @ @ GPIO?GPT I?O M25
AD26 I2$0_SDA I?O @ @ @ @ GPIO1 I?O G23
AB22 I2$1_S$L I?O @ @ SPDI>_TX O GPIO2 I?O E26
AB23 I2$1_SDA I?O @ @ SPDI>_RX I GPIO3 I?O D26
A$25 I2$2_S$L I?O @ @ @ GPIO4 I?O >22
AA22 I2$2_SDA I?O @ @ GPIO5 I?O M26
A$26 IR0 I @ @ @ GPIO4?GPT4 I?O M24
AB25 IR1 I SPDI>_TX$L I @ GPIO5?GPT5 I?O M22
AA24 *1850_RX I O LP$_$S6 O GPIO2 I?O W23
+22 *1850_TX O I @ @ GPIO4 I?O D16
AA2 LP$_A$ I?O LP$_$S O @ @ GPIO24 I?O A1 W4 EMB_AX03 (TS) O @ @ GPIO1 I?O E15
AA4 LP$_$L O TPA O $STP_IN I @ @ $16
W5 LP$_$S0 0 @ @ GPIO25 I?O B16
+3 LP$_$S1 O SPDI>_TX$L I @ @ GPIO I?O $13
+1 LP$_$S2 O N>$_$E_1 O @ @ GPIO0 I?O B13
+5 LP$_OE O @ @ @ @ @ @ A13
AA1 LP$_R?W O @ @ @ @ @ @ $12
AD1 MA0 O @ @ @ @ @ @ E12
AB16 MA1 O @ @ @ @ @ @ A12
A>22 MA10 O @ @ @ @ @ @ B11
A$1! MA11 O @ @ @ @ @ @ $11
AE21 MA12 O @ @ @ @ @ @ E11
AD20 MA13 O @ @ @ @ @ @ D11
AB1! MA14 O @ @ @ @ @ @ $15
AE22 MA15 O @ @ @ @ @ @ A16 AE18 MA2 O @ @ @ @ @ @ E14
A>20 MA3 O @ @ @ @ @ @ A15
AD18 MA4 O D14
PC'P
N
PCP
N
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*3 PATA_INTR I SDH$_D1_IR I?O LP$_AX06 O GPIO15 I?O A20
*2 PATA_IO$HRD+ I SDH$_D0 I?O LP$_AX0 O GPIO14 I?O
*1 PATA_IOR O SDH$_$L O @ @ GPIO12 I?O
5 PATA_IOW O SDH$_$MD I?O LP$_AX08 O GPIO13 I?O
3 PATA_ISOLATE O @ @ @ GPIO11 I?O
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!
$%CN$
D
D
ESET
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P N
>UN$TION 1 I?O >UN$TION 2 I?O >UN$TION 3 I?O >UN$TION 4 I?
$1! $AN1_RX I @ @ @ @ @ @
A18 $AN1_TX O @ @ @ @ GPIO6 I?
B1! $AN2_RX I @ @ @ @ @ @
E16 $AN2_TX O @ @ @ @ GPIO8 I?
+26 $STP_OUT O TPA O @ @ @ @
L4 @ @ EMB_AD00?PATA_AD00 I?O @ @
L3 @ @ EMB_AD01?PATA_AD01 I?O @ @
L2 @ @ EMB_AD02?PATA_AD02 I?O @ @
L1 @ @ EMB_AD03?PATA_AD03 I?O @ @M5 @ @ EMB_AD04?PATA_AD04 I?O @ @
M3 @ @ EMB_AD05?PATA_AD05 I?O @ @
M1 @ @ EMB_AD06?PATA_AD06 I?O @ @
N4 @ @ EMB_AD0?PATA_AD0 I?O @ @
N3 @ @ EMB_AD08?PATA_AD08 I?O @ @
N2 @ @ EMB_AD0!?PATA_AD0! I?O @ @
N1 @ @ EMB_AD10?PATA_AD10 I?O @ @
P3 @ @ EMB_AD11?PATA_AD11 I?O @ @
P5 @ @ EMB_AD12?PATA_AD12 I?O @ @
P4 @ @ EMB_AD13?PATA_AD13 I?O @ @
P2 @ @ EMB_AD14?PATA_AD14 I?O @ @
P1 @ @ EMB_AD15?PATA_AD15 I?O @ @
R3 @ @ EMB_AD16?N>$_D00 I?O @ @
R1 @ @ EMB_AD1N>$_D01 I?O @ @
T2 @ @ EMB_AD18N>$_D02 I?O @ @R5 @ @ EMB_AD1!N>$_D03 I?O @ @
T3 @ @ EMB_AD20N>$_D04 I?O @ @
T4 @ @ EMB_AD21?N>$_D05 I?O @ @
T1 @ @ EMB_AD22?N>$_D06 I?O @ @
T5 @ @ EMB_AD23N>$_D0 I?O @ @
U3 @ @ EMB_AD24N>$_D08 I?O @ @
U1 @ @ EMB_AD25N>$_D0! I?O @ @
"1 @ @ EMB_AD26?N>$_D10 I?O @ @
"2 @ @ EMB_AD2?N>$_D11 I?O @ @
"3 @ @ EMB_AD28?N>$_D12 I?O @ @
U5 @ @ EMB_AD2!?N>$_D13 I?O @ @
"4 @ @ EMB_AD30?N>$_D14 I?O @ @
W1 @ @ EMB_AD31?N>$_D15 I?O @ @
W2 @ @ EMB_AX00 (ALE) O @ @
"5 @ @ EMB_AX01 (TSI#0) O GPIO3 I?
W3 @ @ EMB_AX02 (TSI#1) O GPIO2 I?
A1! GPIO28 I @ @ @ @ @ @
E1 GPIO2! I @ @ @ @ @ @
$18 GPIO30 I @ @ @ @ @ @
B18 GPIO31 I @ @ @ @ @ @
D18 HIB_MODE O @ @ @ @ @ @
W24 HRESET I?O @ @ @ @ @ @
A$23 I2$0_S$L I?O @ @ @ @ GPIO?GPT I?
AD26 I2$0_SDA I?O @ @ @ @ GPIO1 I?
AB22 I2$1_S$L I?O @ @ SPDI>_TX O GPIO2 I?
AB23 I2$1_SDA I?O @ @ SPDI>_RX I GPIO3 I?
A$25 I2$2_S$L I?O @ @ $AN4_TX @ GPIO4 I?
AA22 I2$2_SDA I?O @ $AN4_RX @ GPIO5 I?
A$26 IR0 I @ @ $AN3_TX @ GPIO4?GPT4 I?AB25 IR1 I SPDI>_TX$L I $AN3_RX @ GPIO5?GPT5 I?
AA24 *1850_RX I LP$_$S6 O $AN4_RX O
+22 *1850_TX O GPIO4 I?O $AN4_TX I
AA2 LP$_A$ I?O LP$_$S O @ @ GPIO24 I?
W4 EMB_AX03 (TS) O @ @ GPIO1 I?
AA4 LP$_$L O TPA O $STP_IN I @ @
W5 LP$_$S0 0 @ @ GPIO25 I?
+3 LP$_$S1 O SPDI>_TX$L I @ @ GPIO I?
+1 LP$_$S2 O N>$_$E_1 O @ @ GPIO0 I?
+5 LP$_OE O @ @ @ @ @ @
AA1 LP$_R?W O @ @ @ @ @ @
AD1 MA0 O @ @ @ @ @ @
AB16 MA1 O @ @ @ @ @ @
A>22 MA10 O @ @ @ @ @ @
A$1! MA11 O @ @ @ @ @ @AE21 MA12 O @ @ @ @ @ @
AD20 MA13 O @ @ @ @ @ @
AB1! MA14 O
PC'PN
T/ &, :& S,&&% 29 I, / ,
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PATA_AD00
PATA_AD01
PATA_AD02
PATA_AD03PATA_AD04
PATA_AD05
PATA_AD06
PATA_AD0
PATA_AD08
PATA_AD0!
PATA_AD10
PATA_AD11
PATA_AD12
PATA_AD13
PATA_AD14
PATA_AD15
N>$_D0
N>$_D1
N>$_D2
N>$_D3
N>$_D4
N>$_D5
N>$_D6
N>$_D
N>$_D8
N>$_D!
N>$_D10
N>$_D11
N>$_D12
N>$_D13
N>$_D14
N>$_D15
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