HCS12 Technical Training Module 12- MSCAN, Slide 1
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msCAN
Controller Area Network
Internal Bus
SCI1
256K FLASEEPROM
12K SRAM
ATD 1
HCS12 CPU
BKP INT MMI
CM BDM MEBI
4K BYTESEEPROM
SIM
msCAN3
msCAN2
msCAN1
SCI1
SPI 2or
PWMCH4-7
BDLCor
msCAN0
msCAN4or
IIC
SPI 1or
PWMCH 0-3
SPI 0
ATD 0
PIM PLL PIT
ECT 8CHAN
PWM 8CHAN
HCS12 Technical Training Module 12- MSCAN, Slide 3
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msCAN BusFeatures:
Up to 5 msCAN Modules (msCAN)
• 3 Tx message buffers each Automatically Mapped
• 5 Background Rx Buffers
• Programmable I/O modes
• Maskable interrupts
• Programmable loop-back for self test operation
• Independent of the transmission medium (external transceiver is assumed)
• Open network architecture
• Multimaster concept
• High immunity to EMI
• Short latency time for high-priority messages
• Low power sleep mode, with programmable wake up on bus activity
Note: msCAN 0 is multiplexed with BDLC msCAN 4 is multiplexed with IIC.
HCS12 Technical Training Module 12- MSCAN, Slide 4
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CAN SPECIFICATION
• LATEST REVISION (version 2.0) DIVIDED INTO PARTS A & B
- PART A CONSISTS OF THE PREVIOUS SPECIFICATION REVISION (1.2): - Standard 11-bit Identifier Field - No specification for message filtering - Layered architecture description based on Bosch's internal model
- PART B OUTLINES ENHANCEMENTS TO THE CAN PROTOCOL, INCLUDING: - Extended 29-bit Identifier Field - Some message filtering requirements - Layer description based on ISO/OSI reference model
• MINIMUM CAN REQUIREMENTS INCLUDE COMPATIBILITY WITH SPECIFICATION VERSION 2.0, PART A
• MOST CURRENT INDUSTRIAL APPLICATIONS USE THE STANDARD (11-BIT) IDENTIFIER FORMAT
HCS12 Technical Training Module 12- MSCAN, Slide 5
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CAN PROPERTIES
• Serial communications protocol developed by Bosch, initially for automotive multiplex wiring systems
• Message prioritization defined by the user
• Guaranteed minimum latency for highest priority messages
• Multi - master protocol utilizes non - destructive collision resolution to ensure the highest priority message is transmitted onto bus
• Flexible system configuration allows the user to create the network which best fits the application
• Error detection and error signaling features are built into the CAN protocol, along with automatic retransmission of corrupted messages
• Distinction between temporary errors and permanent node failures prevents faulty nodes from causing long-term disruptions of network traffic
HCS12 Technical Training Module 12- MSCAN, Slide 6
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msCAN - Layered Architecture
• DATA LINK LAYER
• LOGICAL LINK CONTROL (LLC) SUB-LAYER
- Acceptance Filtering - Overload Notification - Recovery Management
• MEDIUM ACCESS CONTROL (MAC) SUB-LAYER
- Data Encapsulation/Decapsulation - Frame Coding (Bit Stuffing/Unstuffing) - Medium Access Management - Error Detection/Signaling - Acknowledgement - Serialization/Deserialization
• PHYSICAL LAYER
- Bit Encoding/Decoding - Bit Timing - Synchronization
HCS12 Technical Training Module 12- MSCAN, Slide 7
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msCAN Message Buffer Organization
msCAN
Tx0
Tx1
Tx2
TxE1
CPU
msCAN
TxE0
TxE2
Priority
Priority
Priority
TxBG
TxBG
TxFG
RxBGRx0
Rx1
Rx2
Receiver
Transmitter
RxBG - Receive Background Buffer
RxFG - Receive Foreground Buffer
TxBG - Transmit Background Buffer
TxFG - Transmit Foreground Buffer
Rx3Rx4
CPU
RxFRxFG
Tx Buffer Pointer
Note: All Tx Buffers map to same address
HCS12 Technical Training Module 12- MSCAN, Slide 8
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msCAN12 Buffer SchememsCAN12 Buffer Scheme
msCAN Receive / Transmit Engine
HCS12 Memory Mapped I/O
or 8 x 8 bits
InternalPriority
Scheduling
Tx Buffer 2
Priority Register
Tx Buffer 1
Priority Register
Tx Buffer 0
Priority Register
Rx Buffer
Rx Buffer
2 x 32 bits
Identifier Filtering
or 4 x 16 bits
* HCS12 FILTERING IS 2x THAT OF THE HC08
5X FIFO
HCS12 Technical Training Module 12- MSCAN, Slide 9
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• Simple user interface to CPU
• Message filtering and buffering
• Protocol handling
• Physical layer interface
CPUInterface
CANTransmit ReceiveEngine
Messagefiltering +buffering
Control + status
Physicalinterface
H/WErrors
CAN bus
Microcontroller
Requirements of a CAN Controller Requirements of a CAN Controller
TXRX
CANH
CANL
HCS12 Technical Training Module 12- MSCAN, Slide 10
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Message Buffer Structure
ID[28:18] SRR IDE ID[17:15]
ID[14:0] RTR
DATA BYTE 0 DATA BYTE 1
DATA BYTE 2 DATA BYTE 3
DATA BYTE 4 DATA BYTE 5
DATA BYTE 6 DATA BYTE 7
DLC[3:0] Tx Buffer Priority Reg.
Time Stamp
EXTENDED ID
$00x0
$00x2
$00x4
$00x6
$00x8
$00xA
$00xC
$00xE
CONTROL/STATUS
ID_HIGH
ID_LOW
ID[10 :0] RTR IDE 0 0 0
Reserved
$00x1
$00x3
STANDARD ID
$00x1
$00x3
$00x5
$00x7
$00x9
$00xB
$00xD
$00xF
$00x2
$00x4
HCS12 Technical Training Module 12- MSCAN, Slide 11
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Extended Format Frames
Field Description
Time Stamp Contains a copy of the high byte of the free running timer capturedat the beginning of the identifier field of the buffer frame on CAN bus.
ID[28:18]/[17:15] Contains 14 MS Bits of Extended identifier.
Substitute Remote Contains a fixed recessive bit, used only in extended format. It should Request (SRR) be set to ‘1’ for TX buffers. It will be stored as received in the RX buffers
ID Extended Should be set to ‘1’ for extended formats, ‘0’ otherwise. (IDE)
ID(14:0) Bits[14:0] of the extended identifier field.
Remote Transmission Request (RTR) 0 = Data frame, 1 = Remote frame
HCS12 Technical Training Module 12- MSCAN, Slide 12
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Standard Format Frames
Field Description
Time Stamp The ID LOW word, which is not needed for standard format, is used in a standard format buffer to store the value of the free-running timer which is captured at the beginning of the identifier field of the frame on the CAN bus.
ID(28:18) Contains bits (28:18) of the identifier, located in the ID HIGH word of the message buffer. The four least significant bits in this register (corresponding to the IDE bit and ID(17:15) for an extended identifier message) must all be written as logic zeros to ensure proper operation of the msCAN.
RTR This bit is located in the ID HIGH word of the message buffer; 0 = data frame, 1 = remote frame.
RTR/SRRBit Treatment If the msCAN transmits this bit as a one and receives it as a zero, an “arbitration loss” is indicated. If the msCAN transmits this bit as a zero and is receives it as a one, a bit error is indicated. If the msCAN transmits a value and receives a matching response, a successful bit transmission is indicated.
HCS12 Technical Training Module 12- MSCAN, Slide 13
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Frame Types
• A Data Frame is used to transmit data onto the multiplex bus; this is the frame used most often in a CAN network
• A Remote Frame is used to request a data frame from another node on the multiplex bus
• An Error Frame will be transmitted by any node which detects an error, corrupting the frame being transmitted
• An Overload Frame is used by a node which desires an extra delay between data or remote frames to allow it time to prepare to transmit a frame
HCS12 Technical Training Module 12- MSCAN, Slide 14
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DATA FRAME
DATA FRAMEInterframe
SpaceInterframe
Space
Start of Frame (1 bit time)
Arbitration Field (Standard ID - 12 bit times ) (Extended ID - 32 bit times)
Control Field (6 bit times) Data Field
(0-8 data bytes)
CRC Field (16 bit times)
ACK Field (2 bit times)
End of Frame (7 bit times)
HCS12 Technical Training Module 12- MSCAN, Slide 15
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ARBITRATION FIELD
Interframe Space
Control Field
Start of Frame
ARBITRATION FIELD
IdentifierRTR Bit
Note: in devices compatible with CAN ver. 2.0, Part B, the arbitration field may also contains the SRR and IDE bits, in addition to the message identifier and RTR bit.
1 BIT12 BITS FOR STANDARD ID32 BITS FOR EXTENDED ID
HCS12 Technical Training Module 12- MSCAN, Slide 16
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STANDARD Vs. EXTENDED I.D. FORMAT
Data Field
CONTROL FIELD
ARBITRATION FIELD
Identifier (11 Bits)
RTR
S O F
r1/IDE*
r 0
DLC (4 Bits)
STANDARD IDENTIFIER FORMAT
* In CAN 2.0, Part A - r1 bit in CAN 2.0, Part B - IDE bit
Interframe Space
Data Field
ARBITRATION FIELD
SRR
S O F
IDE
r 0
DLC (4 Bits)
EXTENDED IDENTIFIER FORMAT
r 1
Identifier (18 bits)
RTR
Identifier (11 Bits)
CONTROL FIELD
Interframe Space
HCS12 Technical Training Module 12- MSCAN, Slide 17
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CONTROL FIELD
Arbitration Field
Data or CRC FieldCONTROL FIELD
r0 - reserved, always dominant r1/IDE - r1 in Can 2.0, Part A, r1/IDE in Part B
Data Length Code
DLC3 DLC2 DLC1 DLC0
No. of data bytes
Data Length Code
DLC3 DLC2 DLC1 DLC0
r1/IDE r0
0 1 2 3 4 5 6 7 8
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1 0
HCS12 Technical Training Module 12- MSCAN, Slide 18
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CRC & ACKNOWLEDGEMENT FIELDS
Data or Control
Field
Ack FieldCRC FIELD
CRC Sequence (15 bit times)
CRC Delimiter
End of Frame
ACK Slot
ACK Delimiter
HCS12 Technical Training Module 12- MSCAN, Slide 19
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REMOTE FRAME
Interframe Space
Interframe SpaceREMOTE FRAME
Start of Frame (1 bit time)
Arbitration Field (Standard ID - 12 bit times ) (Extended ID - 32 bit times)
Control Field (6 bit times)
End of Frame (7 bit times)
ACK Field (2 bit times)
CRC Field (16 bit times)
HCS12 Technical Training Module 12- MSCAN, Slide 20
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ERROR FRAME
superposition of Error Flags (12 bit times)
Data Frame ERROR FRAME
Error Flag (6 bits)
Interframe Space or Overload Frame
Error DelimiterError DelimiterError DelimiterError DelimiterError DelimiterError DelimiterError DelimiterError DelimiterError Delimiter (8 bit times)
HCS12 Technical Training Module 12- MSCAN, Slide 21
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OVERLOAD FRAME
End of Frame or Error Delimiter or
Overload DelimiterOVERLOAD FRAME
Overload Flag
(6 bits)
superposition of Overload Flags
(7 bit times)
Interframe Space or Overload Frame
Overload Delimiter (8 bit times)
HCS12 Technical Training Module 12- MSCAN, Slide 22
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INTERFRAME SPACE
INTERFRAME SPACE - ERROR ACTIVE TRANSMITTER
INTERFRAME SPACEFrame Frame
Intermission (3 bit times)
Bus Idle
INTERFRAME SPACEFrame Frame
Intermission (3 bit times)
Bus Idle
Suspend Transmission (8 bit times)
INTERFRAME SPACE - ERROR PASSIVE TRANSMITTER
HCS12 Technical Training Module 12- MSCAN, Slide 23
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MESSAGE ARBITRATION
• If multiple nodes transmit simultaneously, bit-wise non-destructive arbitration during the message identifier field resolves the conflict
• Identifier defines the priority of the message as well as the target address
• Node transmitting a recessive level but detecting a dominant level immediately halts transmission and becomes a receiver
• Remote frame is lower priority than data frame
• Any loss of arbitration after the arbitration field will be interpreted as an error, and an error frame will be transmitted
HCS12 Technical Training Module 12- MSCAN, Slide 24
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
ERROR DETECTION
• Multiple Error Detection Features:
- 15-bit cyclical redundancy check (CRC)
- Bit stuffing
- Each node verifies message framing
• All global errors detected
• Up to 5 randomly distributed errors will be detected
• Corrupted messages are flagged by any nodes detecting the error
• Corrupted messages are automatically retransmitted
• Recovery time from error detection to start of message retransmission is a maximum of 29 bit times
HCS12 Technical Training Module 12- MSCAN, Slide 25
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FAULT CONFINEMENT
• Separate error counters for transmit and receive errors
• Error counters incremented by 1 or 8, decremented by 1
• 3 possible bus states:
- Error active - both error counts < 128
- Error passive - either transmit or receive error count > 127
- Bus off - transmit error count > 255
• Once error-free bus traffic resumes, nodes can recover from error states
HCS12 Technical Training Module 12- MSCAN, Slide 26
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
ERROR SIGNALING
• Error Active Node
- Transmits active error flag during error frame - Only waits for intermission period during inter-frame space
• Error Passive Node
- Transmits passive error flag during error frame - Must wait for "suspend transmission" period as well as intermission during inter-frame space
• Bus Off Node
- Output drivers switched off - Will not participate in bus traffic, only allowed to monitor bus - Bus off node will return to error active status following detection of 128 consecutive periods of 11 recessive bits
HCS12 Technical Training Module 12- MSCAN, Slide 27
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Bit TimingBit Timing
• SYNC_SEG : The bit edge is expected to lie within this segment ; always 1 time quantum (CAN clock period) long.
• PROP_SEG : Allowance for physical delays. Programmable from 1 to 8 TQ long.
PROP_SEG >= 2 x (bus propagation delay + input comparator delay + output driver delay)
• PHASE_SEG (1, 2) : Defines position of the Sample Point. May be adjusted to compensate for edge phase errors
– PHASE_SEG1: Programmable from 1 to 8 time quanta long.
– PHASE_SEG2: Is the greater of PHASE_SEG1 and the INFORMATION PROCESSING TIME.
• SAMPLE POINT : Bus value is taken as the value of the bit
• INFORMATION PROCESSING TIME: Less than or equal to 2 time quanta.
• BIT TIME : Bit Time = SYNC_SEG + PROP_SEG + PHASE_SEG1 + PHASE_SEG2
SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2
BIT TIME
Sample PointTransmit Point
HCS12 Technical Training Module 12- MSCAN, Slide 28
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msCAN Bus Timing (1 of 2)
Synchronization Jump Width
Baud Rate Prescaler
CANBTR0 - Bus Timing Register 0Address Offset $0002
HCS12 Technical Training Module 12- MSCAN, Slide 29
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msCAN Bit Timing (2 of 2)msCAN Bit Timing (2 of 2)
SAMP: 1 or 3 samples per bit
TSEG1 is determined by TSEG13...TSEG10
TSEG2 is determined by TSEG22...TSEG20
CANBTR1 - Bus Timing Register 1
TSEG22 TSEG21 TSEG20 TSEG20 0 0 1 Tq0 0 1 2 Tq0 1 0 3 Tq: : : :1 1 1 8 Tq
TSEG13 TSEG12 TSEG11 TSEG10 TSEG10 0 0 0 1 Tq0 0 0 1 2 Tq0 0 1 0 3 Tq: : : : :1 1 1 1 16 Tq
Address Offset $0002
HCS12 Technical Training Module 12- MSCAN, Slide 30
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SYNCHRONIZATION
• HARD SYNCHRONIZATION
- Occurs when recessive to dominant edge occurs during bus idle - Internal bit time is started with Sync-Seg
• Resynchronization
- Occurs on all other recessive to dominant edges (and optionally dominant to recessive edges) - Phase-Seg 1 is lengthened or Phase-Seg 2 is shortened depending upon phase error
• Phase Error - e
- e = 0 If edge lies within Sync-Seg
- e > 0 If edge lies after Sync-Seg
- e < 0 If edge lies before Sync-Seg
• Resynchronization Jump Width
- The maximum amount by which Phase-Seg 1 may be lengthened or Phase-Seg 2 may be shortened
HCS12 Technical Training Module 12- MSCAN, Slide 31
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Resynchronization (2)Resynchronization (2)
CANBus
Receiverbit timing
r
d
Negative Phase ErrorPHASE_SEG2 shortened
Positive Phase ErrorPHASE_SEG1 lengthened
Sample points
S PS P1 P2 S PS P1 P2 S PS P1 P2 S PS P1 P2 S PS P1 P2
HCS12 Technical Training Module 12- MSCAN, Slide 32
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CANPHYSICAL LAYER REQUIREMENTS
• CAN Protocol does not specify physical layer
• No specified transceiver, user's network characteristics define transceiver requirements
• Acceptable physical media can include, though not limited to:
- Twisted Pair, Shielded or Unshielded - Single Wire - Fiber Optic Cable - Transformer Coupled to power lines
• Acceptable transmission rates range from 5k to1m bit/sec
• Most implementations use NRZ bit formatting over twisted pair bus
• Three different automotive physical layers exist: ISO11898 Differential, ISOxxxx Fault-Tolerant, J2411 Single Wire
HCS12 Technical Training Module 12- MSCAN, Slide 33
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msCAN MB Identifier RegistersmsCAN MB Identifier Registers
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
ID20 ID19 ID18 RTR/SRR IDE ID17 ID16 ID15
ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7
ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR
IDR0
IDR1
IDR2
IDR3
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
Standard Identifier (IDE = 0) / Base Identifier (IDE = 1)
Extended Identifier (SRR = 1)
The priority of an Identifier is highest for the smallest binary valueie. logic ‘0’ is transmitted as dominant.The 7 most significant bits (ID28 - ID22) must not all be ‘1’ (recessive).
Address Offset $00x0
$00x1
$00x2
$00x3
HCS12 Technical Training Module 12- MSCAN, Slide 34
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msCAN MB Data RegistersmsCAN MB Data Registers
D7 D6 D5 D4 D3 D2 D1 D0DR0..7
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
DLC3 DLC2 DLC1 DLC0DLR
P7 P6 P5 P4 P3 P2 P1 P0TBPR
Priority Register for Transmit Buffers only. $00 is highest priority.
Data Length Code should be 0..8 only.
HCS12 Technical Training Module 12- MSCAN, Slide 35
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msCAN Acceptance Registers (2x32 Bit Filter)msCAN Acceptance Registers (2x32 Bit Filter)
CANIDAR0
CANIDAR1
CANIDAR2
CANIDAR3
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
Standard Identifier / Base Identifier Extended Identifier
Address Offset
$0010
$0011
$0012
$0013
$0018
$0019
$001A
$001B
CANIDAR4
CANIDAR5
CANIDAR6
CANIDAR7
AC28 AC27 AC26 AC25 AC24 AC23 AC22 AC21
AC20 AC19 AC18 RTR/SRR IDE AC17 AC16 AC15
AC14 AC13 AC12 AC11 AC10 AC9 AC8 AC7
AC6 AC5 AC4 AC3 AC2 AC1 AC0 RTR
AC28 AC27 AC26 AC25 AC24 AC23 AC22 AC21
AC20 AC19 AC18 RTR/SRR IDE AC17 AC16 AC15
AC14 AC13 AC12 AC11 AC10 AC9 AC8 AC7
AC6 AC5 AC4 AC3 AC2 AC1 AC0 RTR
HCS12 Technical Training Module 12- MSCAN, Slide 36
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msCAN Message Acceptance Mask
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM20 AM19 AM18 RTR/SRR IDE AM17 AM16 AM15
AM14 AM13 AM12 AM11 AM10 AM9 AM8 AM7
AM6 AM5 AM4 AM3 AM2 AM1 AM0 RTR
CANIDMAR0
CANIDMAR1
CANIDMAR2
CANIDMAR3
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
Standard Identifier / Base Identifier Extended Identifier
Address Offset $0014
$0015
$0016
$0017
$001C
$001D
$001E
$001F
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM20 AM19 AM18 RTR/SRR IDE AM17 AM16 AM15
AM14 AM13 AM12 AM11 AM10 AM9 AM8 AM7
AM6 AM5 AM4 AM3 AM2 AM1 AM0 RTR
CANIDMAR4
CANIDMAR5
CANIDMAR6
CANIDMAR7
HCS12 Technical Training Module 12- MSCAN, Slide 37
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msCAN Message Acceptance Registers (4x16 bit filter)
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM20 AM19 AM18 RTR/SRR IDE AM17 AM16 AM15
CANIDMAR0
CANIDMAR1
CANIDMAR2
CANIDMAR3
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
Standard Identifier / Base Identifier Extended Identifier
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM20 AM19 AM18 RTR/SRR IDE AM17 AM16 AM15
CANIDMAR4
CANIDMAR5
CANIDMAR6
CANIDMAR7
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM20 AM19 AM18 RTR/SRR IDE AM17 AM16 AM15
AM20 AM19 AM18 RTR/SRR IDE AM17 AM16 AM15
Address Offset $0010
$0011
$0012
$0013
$0018
$0019
$001A
$001B
HCS12 Technical Training Module 12- MSCAN, Slide 38
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msCAN Acceptance Registers (8x8 Bit msCAN Acceptance Registers (8x8 Bit Filter)Filter)
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
CANIDMAR0
CANIDMAR1
CANIDMAR2
CANIDMAR3
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
Standard/Extended Identifier
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
AM28 AM27 AM26 AM25 AM24 AM23 AM22 AM21
CANIDMAR4
CANIDMAR5
CANIDMAR6
CANIDMAR7
Address Offset $0010
$0011
$0012
$0013
$0018
$0019
$001A
$001B
HCS12 Technical Training Module 12- MSCAN, Slide 39
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Acceptance FiltermsCAN Acceptance Filter
• Each Acceptance Register has a corresponding Acceptance Mask Register.
• Any bit set in an Acceptance Mask Register means that bit in the Acceptance Register is
masked, ie. not compared with the Message Identifier to determine acceptance.
• Only bits in the Acceptance Register which are not masked are compared with the message
Identifier to determine acceptance.
– 16 bit filter. Bit 3 of CANIDAR1 is ‘1’ and bit 3 of CANIDMR1 is ‘0’
» Therefore IDE must be ‘1’ to be accepted ie Standard Format Identifier.
» In this case CIDMR1 bits 2,1,0 must all be ‘1’ (mask).
– As above, plus CANIDMR1 bit 4 is ‘1’ (mask).
» Therefore Data Frames or Remote Frames accepted.
HCS12 Technical Training Module 12- MSCAN, Slide 40
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Acceptance Control RegistermsCAN Acceptance Control Register
IDAM1 IDAM0 IDHIT2 IDHIT1 IDHIT0CANIIDAC
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
Identifier Acceptance Mode Settings
Identifier Acceptance Hit Indication
HCS12 Technical Training Module 12- MSCAN, Slide 41
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Receive ProcessmsCAN Receive Process
1) Set SFTRST.
2) Configure Acceptance Filter.
3) Enable Receive interrupt.
4) Clear SFTRST.
Receive Interrupt:
1) Read Identifier.
2) Read Data Field (if not Remote Frame).
3) Read Timer Stamp if enabled.
4) Release Receive buffer.
HCS12 Technical Training Module 12- MSCAN, Slide 42
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Transmit ControlmsCAN Transmit Control
TXEn = 1: Transmit buffer empty (sent or aborted).
TXEn = 0: Transmit buffer full (not sent, scheduled).
TXEIEn = 1: Enable transmit interrupt.
ABTRQn = 1: Request abort of transmission.
ABTAKn = 1: Message aborted (not sent).
ABTAKn = 0: Message not aborted (sent).
ABTRQ1 ABTRQ0CANTARQ
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
ABTRQ2
ABTAK2 ABTAK1CANTAAK ABTAK0
$0008
Address Offset $0006
TXEIE2 TXEIE1 TXEIE0CANTIER
CANTFLG TXE2 TXE1 TXE0
$0007
$0009
Write “1” to Clear Interrupt Flag
RST: 0…………………………………………………………0 1 1 1
RST: 0…………………………………………………………………………………...…………………0
RST: 0…………………………………………………………………………………...…………………0
RST: 0…………………………………………………………………………………...…………………0
HCS12 Technical Training Module 12- MSCAN, Slide 43
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Transmit ProcessmsCAN Transmit Process
1) Write Identifier, Data and Priority to empty transmit buffer.
2) Schedule buffer for transmission (clear TXEn).
3) Enable Transmit interrupt (set TXEIEn).
• The transmit buffer with the lowest value (highest Priority) that is scheduled for transmission will arbitrate for CAN bus access during the next IFS.
Transmit Interrupt:
1) Identify transmitted message buffer.
2) Disable Transmit interrupt.
3) Test ABTAK.
4) Read Time Stamp if enabled.
5) Load with new ID, data and schedule for transmission.
HCS12 Technical Training Module 12- MSCAN, Slide 44
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Interrupt ControlmsCAN Interrupt Control
• WUPIF: Wakeup interrupt flag.
• CSCIF: CAN Status Change Interrupt Flag
• OVRIF: Overrun interrupt flag.
• RXF: (Foreground) Receive buffer full.
CACRIER - Receiver Interrupt Enable Register
CANRFLG - Receiver Flag Register
RSTAT1–RSTAT0 — Receiver Status BitsThe values of the Error Counters control the actual bus status of theMSCAN. As soon as the Status Change Interrupt Flag (CSCIF) is setthese bits indicate the appropriate receiver related bus status of theMSCAN. 11 = Bus Off : 255 > Transmit Error Counter10 = RxERR: 127 < Receive Error Counter01 = RxWRN: 96 < Receive Error Counter < 127.00 = RxOK: 0 < Receive Error Counter < 96.
To clear the interrupt requestMust write a “1” to clear corresponding bit, with the event that caused it to set is no longer valid
TSTAT1–TSTAT0 — Transmitter Status BitsThe values of the Error Counters control the actual bus status of the MSCAN. As soon as the Status Change Interrupt Flag (CSCIF) is set these bits indicate the appropriate transmitter related bus status of the MSCAN.11 = Bus Off: 255 > Transmit Error Counter10 = TxERR: 127 < Transmit Error Counter < 25501 = TxWRN: 96 < Transmit Error Counter < 12700 = TxOK: 0 < Transmit Error Counter < 96
HCS12 Technical Training Module 12- MSCAN, Slide 45
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Control Register 0msCAN Control Register 0
RXFRM - Receive Frame
1= Valid message was received
0 = No message was received
RXACT - Receiver Active
1 = msCAN is currently receiving a message
0 = msCAN is transmitting or idle
CSWAI - msCAN stops in WAIT mode
1 = msCAN clock is stopped during Wait mode
0 = msCAN continues to run in Wait mode
SYNCH - Synchronized Status
1 = msCAN is synchronized to CAN bus
0 = msCAN is not synchronized
RXFRM CSWAI SYNCH WUPE SLPRQ INITRQRXACTCANCTL0
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
TIME
Address Offset $0000
TIME - Timer Enable1 = Internal timer enabled0 = Internal timer is disabled
WUPE - Wake-up Enable1 = msCAN is able to start from sleep mode0 = msCAN will not wake up from sleep mode and
ignores bus traffic
SLPRQ: SLEEP Mode Request.1 = Put the msCAN to sleep0 = msCAN functions normally
INITRQ - Initialization Mode Request1 = msCAN is in initialization mode0 = Normal operation
HCS12 Technical Training Module 12- MSCAN, Slide 46
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Control Register 1msCAN Control Register 1
CANE - msCAN Enable
1 = msCAN is enabled
0 = msCAN is disabled
CLKSRC - msCAN Clock Source
1 = The msCAN clock source from IP bus clock
0 = The msCAN clock source from the OSC-CLK
LOOPB: Internal loopback self test mode.
1 = Enable loop back mode
0 = Disable loop back mode
LISTEN - Listen only Mode
1 = Listen only mode is active
0 = Normal operation
CANE CLKSRC 0CANCTL1
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
LOOPB LISTEN WUPM SLPAK INITAK
Address Offset $0001
WUMP - Wake-up Mode
1 = msCAN wakes up the CPU upon detection of a dominant pulse that has a length of Twup while WUPE=1
0 = msCAN wakes the CPU on recessive to dominant
edge on the CAN bus while WUPE =1
SLPAK - Sleep Mode Acknowledge
1 = The msCAN entered sleep mode
0 = msCAN is running
INITAK - Initialization Mode Acknowledge
1 = Initialization mode is active
0 = Normal operation
HCS12 Technical Training Module 12- MSCAN, Slide 47
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Low Power ModesmsCAN Low Power Modes
STOP WAIT RUN
Power Down x CSWAI = 1 -
Sleep - SLPAK = 1 SLPAK = 1
Soft Reset - SFTRST = 1 SFTRST = 1
msCAN registers may still be accessed in SLEEP and Soft Reset modes.
msCAN will generate a Wakeup interrupt only if SLPAK = 1 and WUPIE = 1
The message which wakes up the msCAN will not be received.
HCS12 Technical Training Module 12- MSCAN, Slide 48
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
msCAN Error Counter
Rx & Tx Error Counters are Read Only when in sleep mode (SLPRQ = 1 & SLPAK =1) orin Initialization mode (INITRQ & INITAK)
Tx Error Counter
Rx Error CounterAddress Offset $000E
$000F
HCS12 Technical Training Module 12- MSCAN, Slide 49
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Window LiftLock
Mirror
Lock
Lock
Mirror
Lock
Universal Motor
Universal Panel
Wiper
InteriorLight Lock
Seat
Seat
RoofECU 3
ECU 1
ECU 2
OSEK OS
OSEK COM/NM
e.g. ignition
GatewayApplication
Light
OS
EK
OS
Tas
kE
Tas
kF
Tas
kD
Cli
mat
e C
on
tro
lO
SE
K C
OM
/NM
OS
EK
OS
Tas
kB
Tas
kC
Tas
kAC
entr
al B
od
yC
on
tro
lO
SE
K C
OM
/NM
Inst
rum
ent
s
ECU 4
CAN Engine Network (> 250kbps)CAN Body Network (< =125kbps)Sub Bus Network (< 50kbps)
Motorola’s System FocusMotorola’s System Focus
De
ve
lop
me
nt T
oo
ls
Drivers
Motorola Silicon
OSEK-OS, -COM, -NM
Fu
nc
tion
ality
OS Libraries
Application Code
De
sig
n T
oo
ls
Motorola Focus
Heating
Heating
HeatingHeating
HCS12 Technical Training Module 12- MSCAN, Slide 50
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
MC33388DW
Vbatt MC7805
CAN H
CAN L
ENSTBNERRTXRX
5v
HCS12
MC33186DWStatusIn1-I/O
In2-I/ODi21-I/O
DiscreteLogic
In1-I/OIn2-I/ODi21-I/O
MC33288DHStatus
M
Vbatt
MC33186DWStatusIn1-I/O
In2-I/ODi21-I/O
MC33186DWStatusIn1-I/O
In2-I/ODi21-I/O
MC33186DWStatusIn1-I/O
In2-I/ODi21-I/O
M
M
M
M
Mirror Position X
MY
Door LockVbatt
Vbatt
Vbatt
Vbatt
Window Lift
Mirror Fold
MTB75N06HDMTB75N06HD
CA
N B
us
Example of CAN in a Door SystemExample of CAN in a Door System
HCS12 Technical Training Module 12- MSCAN, Slide 51
MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2001.
Example of CAN in ISU / Gateway ApplicationExample of CAN in ISU / Gateway Application
INPUTCIRCUITRYMC33287
MC9S12DP256
SPI
Serial relay drivers
Lamps / Motors
FlasherMC33288
M M
(MC33298)L
M
L L
LCourtesy
lampsMC33286
PWM
I/O's
I/O'sI/O's
SCI
MC33388
R
R
MC7805
DIAGNOSTIC
CAN
256KFLASH
12KRAM20 - 30
INPUTS
Front/RearWiper Drivers
MC33HBRIDGE
M
M
ISU SYSTEM
Central locking driver
MC33HBRIDGE
BO
DY
CA
N B
US CANMC33388
PO
WE
RT
RA
IN C
AN
BU
S
CAN H
CAN L
CAN L
CAN H
Vbat 5V