OIF Electrical InterfacesSXI-5 and TFI-5
Tom PalkertApplied Micro Circuits Corporation (AMCC)
SERDES FramerInterface (SFI)
FEC
Data
Clock
Data
Clock
OR
OIF Electrical Specifications
Status
Link LayerNP
ATMSAR
System PacketInterface (SPI)
Data
Status
Data
Data
Data
T D MSwitch Fabric
PHYDevice
TDM Fabric to Framer Interface (TFI)
Clock
SERDES FramerInterface (SFI)
OpticalInterface (VSR)
SERDES Device
andOptics
Data
Clock
Data
Clock
SxI
Common Electrical SpecificationFor SFI-5; SPI-5; and TFI-5*
* TFI-5 optimized for backplane applications
SERDES FramerInterface (SFI)
FEC
Data
Clock
Data
Clock
OR
SERDES FramerInterface (SFI)
Data
Clock
Data
Clock
OpticalInterface
SERDES Device
andOptics
SxI-5 Common Electrical Interface
Status
Transmit Link Layer
Device
Receive Link Layer
Device
System PacketInterface (SPI)
Data
Status
Data
Data
Data
T F I
PHYDevice
TDM Fabric to Framer Interface (TFI)
SxI-5 SxI-5 SxI-5 SxI-5
SxI-5 Common Electrical Interface
TXREFCK TXREFCK TXREFCK
RXREFCK
SerdesFramerFEC
Processor
TXDCK
TXDATA [15:0]
TXCKSRC
TXDCK
TXDATA [15:0]
TXCKSRC
RXREFCK
DC
AB
DC
AB
RXDCK
RXDATA [15:0]
RXDSC
RXSAB
RXDCK
RXDATA [15:0]
RXDSC
RXSAB
Deskew signal aligns data channels
TXDSC TXDSC
S y s t e m t o O p t i c s
O p t i c s t o S y s t e m
SxI-5 Common Electrical Interface
Data
Status
Data
Status
System PacketInterface (SPI-5)
TransmitInterface(SPI-5)
ReceiveInterface(SPI-5)
SERDES FramerInterface (SFI-5)
SERDES FramerInterface (SFI-5)
Data Data
DataData
Clock
Clock
Clock
Clock
Transmit Link Layer
Device
Receive Link Layer
Device
SERDES Device
andOptics
FECDevice
PHYDevice
Provide well defined voltage levels and timing budgets
SxI-5 Common Electrical Interface
Data
Status
Data
Status
System PacketInterface (SPI-5)
TransmitInterface(SPI-5)
ReceiveInterface(SPI-5)
SERDES FramerInterface (SFI-5)
SERDES FramerInterface (SFI-5)
Data Data
DataData
Clock
Clock
Clock
Clock
Transmit Link Layer
Device
Receive Link Layer
Device
SERDES Device
andOptics
FECDevice
PHYDevice
Capable of driving at least 8 inches of FR4 with 1 or 2 connectors
8" 8" 8"
SxI-5 Common Electrical Interface
Jitter : Phase variations in a signal (clock or data).
Complement
True
Ideal0-crossingpoint
Samplingpoint
Ideal1-crossingpoint
Total Jitter is composed of both deterministic and random content.
SxI-5 Common Electrical Interface
The transmit eye mask specifies the jitter at reference points A and C
Normalized bit time [UI]
0 XT1 XT2 1-XT2 1-XT1 1
0
-YT2
-YT1
YT1
YT2
SerdesFEC
Processor
TXDATA
D
RXDATA
B
Dif
fere
ntia
l sig
nal a
mpl
itud
e [V
]C
A
SxI-5 Common Electrical Interface
The receive eye mask specifies the jitter at reference points B and D
Normalized bit time [UI]
0 1
0
-YR2
-YR1
YR1
YR2
XR1 XR2 1-XR2 1-XR1
SerdesFEC
Processor
TXDATA
C
RXDATA
AD
iffe
rent
ial s
igna
l am
plit
ude
[V]D
B
SxI-5 Common Electrical Interface
Wander: The variation in the phase of a signal (clock or data) after filtering with a low pass filter.
Relative Wanderbetween lanes xand yPeak to Peak
Skew betweenlanes x and y
Lane X
Lane Y
Skew: The constant portion of the difference in the arrival time between two signals.
TFI-5
TDM Fabric to Framer Interface
Reference Diagram
T D M
S w i t c h
SONET/SDH framer
TFI-5 link
OC-3/12/48/192/768 STM-1/4/16/64/256
SONET/SDH signals
OTU1/2/3
10 GbE LAN PHY
OTN (G.709) signals
Ethernet signals
10 GbE WAN PHY (OC-192/STM-64)
TFI-5 Mapper
OTN framer
TFI-5 Mapper
10GbE LAN PHY Framer
TFI-5 Mapper
10GbE WAN PHY Framer
TFI-5 Mapper
TFI-5 Requirements Support SONET/SDH framers with line-side interfaces of OC-48/STM-16, OC-192/STM-64, and OC-768/STM-256 and multi-channel framers with lower rate line-side interfaces with an aggregate bandwidth of N x OC-48/STM-16. (e.g. quad OC-12/STM-4).
Support G.709 OTN framers and 10GE LAN/WAN PHY framers by mapping into a SONET/SDH frame
Uses scrambling to ensure transition density. Support lane bandwidths of 2.488 Gb/s (STS-48) or optionally 3.1104 Gbps (STS-60).
Support de-skew between TFI-5 lanes originating from multiple framers or fabric devices.
Support STS-1 Switching fabrics constructed from multiple devices.
TFI-5 device shall be capable of checking for errors.
Capable of driving at least 30 inches of PCB with 2 connectors for intra-shelf environments and at least 100 meters over optics for inter-shelf environments.
Support DC coupling. AC coupling is optional.
Provide a clear forward migration path to future fabrication processes.
Wide availability of components.
TFI-5 Signal Definitions
Signal Name
Function
TFIDATA
The TFI-5 Data (TFIDATA) signal carries the data between the Framer and the Switch Fabric. The same signal definition is applicable to data transfer in the Framer to Fabric direction, and the Fabric to Framer direction.
TFIREFCK
The TFI-5 Reference Clock (TFIREFCK) signal provides timing reference to all the TFI-5 data (TFIDATA) signals in a system.
TFI8KREF
The TFI-5 8kHz Frame Reference (TFI8KREF) signal provides reference to frame boundaries for all the devices in a TFI-5 system.
TFI-5 Layered approach
Mapping Layer
Connection Layer
Link Layer
Client signal
TFI-5 Link
TFI-5 System Model detailing extent of Layers
STS-1Time Slot
Interchange
Ingress Framer #1
TFI-5 Link Layer TFI-5 Link Layer
LinkframerLink
framerLink
framerLink
framer
LinkframerLink
framerLink
framerLink
framer
LinkframerLink
framerLink
framerLink
framer
STS-1 (x48)connect.monitoring
Mappingof clientsignals
TFI-5 Connection Layer
TFI-5 Mapping Layer
STS-1 (x48)connect.monitoring
STS-1 (x48)connect.monitoring
STS-1 (x48)connect.monitoring
SwitchTFI-5 Link TFI-5 Link
Ingress Framer #n
Egress Framer #1Link
framerLink
framerLink
framerLink
framer
STS-1 (x48)connect.monitoring
Mappingof clientsignals
STS-1 (x48)connect.monitoring
STS-1 (x48)connect.monitoring
STS-1 (x48)connect.monitoring
Egress Framer #n
.....
.....
.....
.....
.....
.....
TFI-5 Frame Format
.....
2
3
4
5
6
7
8
9
2N+1 .......... 3N-1 3N 3N+1 90N............
1
1 2 N-3 N-2 N N+1 N+2 N+3 2N-1 2NN-1..... N+4 .....
.....B2 B2 B2 B2 B2
CM CM CM CM CM
B1
A1A1 A2A2A2A1
.....CSI CSI CSI CSI CSI
Link layer overhead Connection layer overhead
.....H1 H1 H1 H1 H1 .....H2 H2 H2 H2 H2 .....H3 H3 H3 H3 H3
ST
S-S
PE
/VC
are
a