Petros OikonomakosPetros Oikonomakos Mark ZwolinskiMark Zwolinski
Controller Self-checking in a Controller Self-checking in a Controller / Datapath ArchitectureController / Datapath Architecture
Electronics and Computer Science
University of Southampton, UKElectronic Systems Design Group
3rd UK ACM SIGDA Workshop on EDA
Southampton, UK, 11-12 September 2003
Outline
Introduction
Target Architecture
Parity-based Techniques
Intrinsically Secure States
Self-checking design theory
1/n self-checking
Conclusion
Introduction
Starting point : controller / datapath system, self-checking datapath [Oikonomakos et al, DATE 2003]
Goal : controller self-checking, integration with previous work
Requirements : technology independence, ease of automation (time to market), area efficiency, adherence to self-checking theory
Complete, automatically produced, controller / datapath self-checking solution!!!
Target Architecture
stat
e re
gis
ter
next state logic
……
.
….
dec
od
er
….
A B encoded state one-hot
control signals
N N+1
N+2
…
……
.
O1 O2
O3
O4
Controller / datapath architecture
Possibly several communicating FSMs
Previous work : self-checking at point A
Self-checking at point B is essential!!!
Per process parity-based self-checking
P1 P2 Pn-1 Pn
…… …
…..
……
..
……
..
……
..
……
.. …
…..
……
.. …
…..
Odd parity
checker PC1
Odd parity
checker PC2
Odd parity
checker PCn-1
Odd parity
checker PCn
……
Dual-rail checker / response compactor
Co
ntr
ol S
ign
als
Co
ntro
l Sig
nals
……
m2 mn-1
1 1
m1 mn
1 1
0
Single parity-based self-checking P1 P2 Pn-1 Pn
…… …
…..
……
..
……
..
……
..
……
.. …
…..
……
.. …
….. C
on
tro
l Sig
nal
s
Co
ntro
l Sig
nals
Odd parity checker
1
“dummy” inserted if n=2k
m2 Pd mn-1
1 1
0
1 1
m1 mn
per process parity checking : ~(NS+5×n) gates
single checker : ~NS gates
NS : total number of states
n : number of processes
the higher the degree of parallelism, the more the hardware savings!!!
Hardware Costs
Viterbi encoder synthesis results (Target Technology Xilinx Virtex XCV 1000 FPGA)
Version Area (slices)
Delay (clock cycles)
Area overhead %
original 174 4 N/A controller (parity_1)
self-checking 184 4 5.7%
controller (parity_2) self-checking
178 4 2.3%
Intrinsically Secure (I.S.) States
N N+1
N N+1
(a) Zero-error latency duplication-based self-checking design
(b) Accepting an error latency of a single clock cycle
+1 +1΄
!=
+1 +1΄ !=
Exploiting I.S. States in a process
Normal State
Intrinsically Secure State
Co
ntro
l Sig
nals
Odd Parity Checker
basic scheme
detects all single control signal faults
possibly little hardware saving
several multiple faults are also detected!!!
Per process I.S. states-based self-checking P1 P2 Pn-1 Pn
IS
IS
no
n-IS
IS
n
on
-IS
……
……
..
……
..
……
..
……
..
Odd parity
checker PC1
Odd parity
checker PC2
Odd parity
checker PCn-1
Odd parity
checker PCn
……
Dual-rail checker / response compactor
Control Signals
Control Signals
……
OR
OR
Control Signals
OR
OR
Control Signals
no
n-IS
no
n-I
S
IS
1 1
m1 mn
1 1
m2 mn-1
0
Single I.S. states-based self-checking
IS
Pd
1
P1 P2 Pn-1 Pn
IS
no
n-I
S
…… …
…..
……
..
……
..
0
Odd parity checker
Control Signals
Control Signals
OR
OR
Control Signals
OR
OR
Control Signals
no
n-IS
no
n-I
S
IS
IS
no
n-IS
m2 mn-1
1 “dummy”
inserted if n=2k
1 1
1 1
m1 mn
First experimental results
Qrs benchmark
Target Technology Alcatel CMOS .35 VLSI
Version Area (gates)
Delay (clock cycles)
Area overhead %
datapath self-checking 25132 52 N/A datapath and controller (parity_1) self-checking
25229 52 ~0.4%
datapath and controller (IS_1) self-checking
(27 IS states)
27465
51
9.3%
Self-checking design theory
Functional Circuit
Checker
Error
the fault-secure property
the self-testing property
the totally self-checking (TSC) property
checker structure + system operation
modelled faults Φ
code inputs A
code outputs B
Example
stuck-at-0 1
2
3
5-bit odd parity checker
A
B
C D
E
X Φ={all stuck-at faults}
A={01110, 01000, 00111}
B={01, 10}
Self-checking design theory
Four vectors required to achieve the TSC goal for a parity checker (Khahbaz and McCluskey, TCOMP
1984)
1 0 1…………..
0 1 1…………..
1 1 0…………..
0 0 0…………..
rows : distinct, same parity
each column : exactly 2 1s and 2 0s
Self-exercising parity checker design X1 X2 Xn
Q1 Q2 Qn ……….. D Q CK
D Q CK
D Q CK cn-1 c1 cn
.……………….…………………….
Conventional Parity Checker
taken from Tarnick, VLSI Design 1998
1/n checker by Khakbaz, TCOMP 1982
2-R
AIL
CH
EC
KE
R
CO
DE
T
RA
NS
LA
TO
R
……
……
..
……
……
..
1-out-of-n 2-rail
TSC for n>3
generic
technology-independent
friendly to design automation
sometimes criticised as slow, but this does no harm here
Per process 1/n self-checking
P1 P2 Pn-1 Pn
…… …
…..
……
..
……
..
……
..
……
.. …
…..
……
.. …
…..
1/n
checker C1
1/n
checker C2
1/n
checker Cn-1
1/n
checker Cn
……
Dual-rail checker / response compactor
Co
ntr
ol S
ign
als
Co
ntro
l Sig
nals
……
m2 mn-1
1 1
m1 mn
1 1
0
Per process 1/n self-checking utilising I.S. states P1 P2 Pn-1 Pn
IS
IS
no
n-IS
IS
n
on
-IS
……
……
..
……
..
……
..
……
..
1/n
checker C1
1/n
checker C2
1/n
checker Cn-1
1/n
checker Cn
……
Dual-rail checker / response compactor
Control Signals
Control Signals
……
OR
OR
Control Signals
OR
OR
Control Signals
no
n-IS
no
n-I
S
IS
1 1
m1 mn
1 1
m2 mn-1
0
Version Area (gates)
Delay (clock cycles)
Area overhead %
datapath self-checking 6143 22 N/A datapath and controller
parity-based self-checking 6460 22 5.2%
datapath and controller parity-based self-checking,
utilising 7 IS states
6404
22
4.2%
datapath and controller 1/n self-checking
6325 22 3.0%
datapath and controller 1/n self-checking utilising 7
IS states
6307
22
2.7%
Experimental results
Diffeq benchmark
Target Technology Alcatel CMOS .35 VLSI
Conclusion
self-checking at the raw, one-hot control signals
alternative controller self-checking schemes
datapath self-checking resource reuse (Intrinsically Secure States)
implementation within a synthesis system, providing full datapath and controller self-checking solutions