Platform-based Design
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The New System Design Paradigm
Orthogonalization of concerns: the separationof function and architecture,
of communication and computation
CPUCore
DSPCore
Software
Content
GlueLogic
HardwareBlueTooth
MemoryI/O
IEEE1394
Block-Based Design
DifferentiationSoftware
Application-SpecificHardware
CPUCore
DSPCore
Memory
I/O
RTOSBlueTooth BlueToothDriver
IEEE1394 IEEE1394Driver
Platform-Based Design
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Terms
• Function– A function is an abstract view of the behavior of the system.– It is the input/output characterization of the system with respect to
its environment. – It has not notion of implementation associated to it.
• Architecture– An architecture is a set of components, either abstract or with a
physical dimension, that is used to implement a function.
• Architecture platform– A fixed set of components with some degrees if variability in the
performance or dimensions of one or more of its components
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Communication
• Communication provides for the transmission of data and control information between functions and with the outside world.
• Communication layers– Transaction: Point-to-point transfers between VCs.
Covers the range of possible options and responses(VC interface).
– Bus Transfer: Protocols used to successfully transfer data between two components across a bus.
– Physical: Deal with the physical wiring of the buses, drive, and timing specific to process technology.
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How Platform-Based Design Works?
Derivative design
Added
ModifiedRemoved
Reference design
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8-bit MCU
Audio Codec SpeakerMicrophone
USB 1.1 Other Products
On-Chip Bus
LCDController
Flash CardInterface
Multimedia Platform: MP3
DSP
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8-bit MCU
Audio Codec SpeakerMicrophone
USB 1.1 Other Products
On-Chip Bus
LCDController
Flash CardInterface
Multimedia Platform: PC Camera
DSP
Image Sensor(CMOS)
Analog Processing
(ADC)
Lens
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32bit MCU
Audio Codec SpeakerMicrophone
USB2.0 Other Products
DRAMController
LuminanceSignal
Processing
ChrominanceSignal
ProcessingImageDSP
On-Chip Bus
Frame Transfer
CCD
CCDDriver
Drive Timing Generator
CCD Controller
Analog Signal
Processing
A/DConverter
AFE
Lens
LCDController
Flash CardInterface
NTSC/PAL Encoder
JPEG CODEC
To TV Video DAC
Multimedia Platform:DSC
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32bit MCU
NTSC/PAL Encoder
LuminanceSignal
Processing Audio Codec SpeakerMicrophone
1394/USB2.0 Other
ProductsMPEG 4 codec
ChrominanceSignal
ProcessingImageDSP
DRAMController
On-Chip Bus
Frame Transfer
CCD
CCDDriver
Drive Timing Generator
CCD Controller
Analog Signal
Processing
A/DConverter
AFE
Lens
LCDController
Flash CardInterface
To TV Video DAC
Multimedia Platform: Video Camera
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Platform-based integration
• A fully defined architecture with – Bus structure– Clocking/power distribution– OS
• A collection of IP blocks• Architecture reuse
The definition of a hardware platform is the result of a trade-off process involving
reusability, production cost and performance optimization.
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Ingredients of A Platform
• Cores– Processor IP– Bus/Interconnection– Peripheral IP– Application specific IP
• Software– Drivers– Firmware– (Real-time) OS– Application software/libraries
• Validation– HW/SW Co-Verification– Compliance test suites
• Prototyping– HW emulation– FPGA based prototyping– Platform prototypes (i.e.
dedicated prototyping devices)
– SW prototyping
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How to Build A Platform
• Architecture constraints for an integration platform:– first pick your application domain– then pick your on-chip communications architecture and structure
(levels and structure of buses/private communications)– then pick your Star IP (e.g. processors) – processors ‘drag’ along
detailed communications choices e.g. processor buses,– dedicated memory access, etc. - ARM-AMBA, etc. Also limit e.g.
RTOS– pick application specific HW and SW IP– other IP blocks not available ‘wrapped’ to the on-chip
communications may work with IP wrappers. VSI Alliance VCI is the best choice to start with for an adaptation layer
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Pros & Cons of Platform-based Design Design
• Advantages– Can substantially shorten design cycles– Large share of pre-verified components helps address
the validation bottleneck for complex designs– Enables quick derivative designs once the basic
platform works– Rapid prototyping systems can be used to quickly build
physical prototypes and start S/W development• Limitations
– Limited creativity due to predefined platform components and assembly
– Differentiation more difficult to achieve, needs to be primarily in application software
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Platform-summary
• What is a platform - a shortcut to time-to-market– Object
• Architecture reuse• HW/SW co-design
– Accessory: tools, design and test methodologies• How to differentiate a platform
– Programmability, Configurability, Scalability, Robustness– Performance, Area, Power– Application softwares
• Intention– Prototyping, product
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Types of Platform
• According to the strength of constraints on hardware– Fixed Platforms
• Software-oriented: TI's OMAPTM, Philips Nexperia™.• Application-specific: Ericsson’s BCP,
– Configurable platforms• Bus structure, multiple processor, programmable logic device• E.g.: Altera's ExcaliburTM, Triscend’s CSoC, Philips RSP, Cypress
MicroSystems’ PSoCTM, E.g.: Palmchip’s PalmPakTM, Wipro’s SOC-RaPtorTM , Tality’s ARM-based SoC.
– Programmable platform• Improv’s - PSATM Jazz
stronger
weaker
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Improv - PSATM Jazz Platform
Jazz Processor
SMemory
PMemory
IMemory
Jazz Processor
SMemory
PMemory
IMemory
PMemory
IMemory
Jazz ProcessorQ Bus
Programmable IO Module(Parallel or serial) Custom IO Blocks
Acronym I : InstructionP: Private:S: Shared
Q Bus (Queue Bus)QBus-AQbus-BArb
Pins
Acronym - PSA: Programmable Systems Architecture
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Jazz VLIW Processor - A Sample
• 3 ALUs, 1 MAC, 1 SHIFT, 1CNT (built into control unit)• 240 bit instruction width (memory image lower using instruction compression)• 32-bit datapath, 16-bit address width• 32 deep Task Queue• 1.3 BOPS at 100 MHz (5 CU ops, counter, 7 MIU ops)• ~100K gates
Jazz Processor
Left Shared Memory
MIU MIU MIU
Data Communication Module Control
Unit
InstructionMemory
TaskQueue
Private Memory
Right Shared Memory
QBus
32 BitALU
32 BitALU
32 BitMAC
64 BitShift
32 BitALU
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Features
• State-of-the-art compilation technology that supports both– Task level parallelism (with the multiple processors)– Instruction level parallelism (through the Jazz VLIW processors).
• Designer start at the Java level• No OS required• Configuration at three levels
– Platform - Collection of processors, data/instructionmemory and I/O resource
– Processor - Computation units and memory interfaces– Instruction - User can create custom logic computation units
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TI's OMAPTM Platform
• OMAP Revolutionizes: 2.5 and 3G Wireless Internet Appliances
• Dual-core architecture optimized for efficient OS and multimedia code execution– TMS320C55xTM DSP provides superior multimedia
performance while delivering the lowest system-level power consumption
– TI-enhanced ARMTM 925 core with an added LCD frame buffer to run command and control functionsand user interface applications.
Acronym - OMAP: Open Multimedia Applications Platform
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Philips - Rapid Silicon Prototyping (RSP)
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RSP7 ASIC Block Diagram
RSP7+ is targeted at customer designing SOC ASICs for:Networking PeripheralsVirtual Private NetworksSystems Requiring ARM-based Control and Wired Connectivity
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RSP7+ Emulation Board
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Triscend - Configurable System-on-Chip
• A configurable system-on-chip (CSoC) is a single device consisting of: – A dedicated, industry-standard processor
• 8051-based E5a• ARM-based for A7 device• SuperH for the future (2001.1.22 announced, 2002 available)
– An open-standard, dedicated, on-chip bus– Configurable logic – Memory – Other system logic
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Triscend E5 System Highlights
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Triscend A7 System Highlights
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Cypress MicroSystems - PSoCTM
Digital PSoC Blocks
Analog PSoC Blocks
ProgrammableInterconnect
PSoC Blocks
Acronym - PSoC: Programmable System-on-Chip
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PSoC Blocks• Eight 8-bit digital PSoC blocks
– Four Digital Basic Type A blocks:• Timer/Counter/Shifter/CRC/PRS/Deadband functions
– Four Digital Communications Type A blocks:• Timer/Counter/Shifter/CRC/PRS/Deadband functions• Full-duplex UARTs and SPI master or slave functions
• Twelve analog PSoC blocks– Three types: ContinuousTime (CT) blocks, and type 1 and type 2
Switch Capacitor (SC) blocks that support– 14 bit Multi-Slope and 12 bit Delta-Sigma ADC, successive
approximation ADCs up to 9 bits, DACs up to 9 bits, programmable gain stages, sample and hold circuits, programmable filters, differential comparators, and temperature sensor.
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Altera - ExcaliburTM Embedded Processors
• Processors– ARM, MIPS
ARM/MIPSCPU
Embedded processor core
Cache
On-Chip RAM
ExternalBus Interface
UARTSerial Port
External Device
JTAG/Debug APEXTM
Architecture
Programmable logic core
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ARM-Based System Architecture
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Wipro’s SOC-RaPtorTM Architecture
SOC-RaPtor: SoC Rapid Prototyper Architecture Platform
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Palmchip’s PalmPakTM SoC Platform
CoreFrameTM
ArchitectureMbus and PalmBusPoint-to-point andbroadcast connections Star-shaped topologyCPU Subsystem
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Tality’s ARM/OAK-based SoC Platform
• Used as the development vehicle for multiple application-specific Integration Platforms. – for Bluetooth, xDSL and Cable Modems.– “Socketizes” the IP to make it AMBA 2.0-compliant.
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Example of Tality’s Derived Design - Bluetooth
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Summary
• Platform-based design– From board design to SoC design– From executable spec., i.e., C/C++, to SystemC
• Modeling– Performance evaluation– Task mapping– Communication refinement