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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed
PRESENTATION ON
ANALOG TO DIGITAL CONVERTER
SUBMITEB BY VYOMESH UPADHYAYMOHIT BUWADESUBMITED TO :
ROHIT SHRIVASTAV
(DELD)
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DUAL SLOPE A/D CONVERTOR
SUCCESSIVE APPROXIMATION
A/D CONVERTOR
INTRODUCTION OF ANALOG TO
DIGITAL CONVERTER
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3
INTRODUTION
ADC = Analog-Digital-Converter
Conversion of audio signals (mobile
micro, digital music records, ...) Conversion of video signals (cameras,
frame grabber, ...)
Measured value acquisition(temperature, pressure, luminance, ...)
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4
Sample
& Hold
Quantizationfsample
AnalogDigital
ADC - Scheme
Analog input can be voltage or current (in
the following only voltage)
Analog input can be positive or negative (in the
following only positive)
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Why ADC ?
Digital Signal Processing is more popularEasy to implement, modify, Low cost
Data from real world are typically AnalogNeeds conversion system
from raw measurements to digital data
Consists ofAmplifier, FilterSample and Hold Circuit, Multiplexer
AD
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Flash ADCs:High speed, but large area and high power dissipation.
Suitable for low-medium resolution (6-10 bit).Sub-Ranging ADCs:Require exponentially fewer comparators thanFlash ADCs. Hence, they consume less silicon area and less power.
Pipelined ADCs: Medium-high resolution with good speed. Thetrade-offs are latency and power.
Successive Approximation ADCs:Moderate speed with medium-high resolution (8-14 bit). Compact implementation.
Integrating ADCs or Ramp ADCs:Low speed but high resolution.Simple circuitry.
Delta-Sigma based ADCs: Moderate bandwidth due tooversampling, but very high resolution thanks to oversampling and noiseshaping.
ADC Architectures
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed
DUAL-SLOPE A/D CONVERTOR
+
CLK
Controllogic
C
Latches
EN
D7 D6 D5 D4 D3 D2 D1 D0
R
+
Vin
VREF
SWR
C
A 1A
2
0 V
+
n
Counter
SW -V
V
0t = n counts
Fixed interval
Variablevoltage
Variableslope
I
HIGHHIGH
I
V
0
Variable time
Fixed-sloperamp
1. The dual-slope ADC integrates the input voltage for a fixed timewhile the counter counts to n.
2. Control logic switches to theVREFinput.
3. A fixed-slope ramp starts fromV as the counter counts. When itreaches 0 V, the counter output is latched.
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Operation
Integrate
Reset and
integrate
Thus
ApplicationsDPM(Digital Panel
Meter), DMM(Digital
Multimeter),
Low Speed
If T1 = 60Hz, converterthroughput rate < 30
samples/s
Excellent Noise Rejection
High frequency noise
cancelled out by
integration
Proper T1 eliminatesline noise
Easy to obtain good
resolution
1
0
T
iv dt 20
t
rV dt
1 ( ) 2i AVG r T v t V 2( )
1
i AVG r
tv V
T
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Input s ignal is
averagedGreater noise
immunity than
other ADC types
High accuracy
Slow
High precis ion
external
components
required to achieve
accuracy
ADVANTAGES DISADVANTAGES
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2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights ReservedFloyd, Digital Fundamentals, 10th ed
D
+
C
SAR
DACVout
Parallel
binary
output
CLK
D0
D1
D2
D3
Serialb
inary
output
Input
signal
Comparator
(MSB) (LSB)
SUCCESSIVE APPROXIMATIOIN A/D CONVERTOR
1. Starting with the MSB, each bit in the successive approximation
register (SAR) is activated and tested by the digital-to-analog
converter (DAC).
2. After each test, the DAC
produces an output voltage
that represents the bit.3. The comparator
compares this voltage with
the input signal. If the inputis larger, the bit is retained;
otherwise it is reset (0).
The method is fast and has a fixed conversion time for all inputs.
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Successive Approximation ADC Circuit
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A comparator anda DAC are used in
the process. Much faster than
the digital ramp
ADC because ituses digital logic toconverge on the
value closest to theinput voltage.
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Chap 0 15
Most Commonly used in medium to highspeed Converters
Based on approximating the input signal
with binary code and then successivelyrevising this approximation until best
approximation is achieved
SAR(Successive Approximation Register)holds the current binary value
O
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OUTPUT
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Capable of high speedand reliable
Medium accuracycompared to other ADCtypesGood tradeoff between
speed and cost
Capable of outputtingthe binary number in
serial (one bit at a time)
Higher resolutionsuccessive approximation
ADCs will be slower
Speed limited to ~5Msps
ADVANTAGES DISADV