Princess Sumaya Univ.Computer Engineering Dept.
Chapter 4:Chapter 4:
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
ADD R3, R1, R2
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
ADD R2, R1, +5
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
LD R2, M[R1 + 5]
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
ST M[R1 – 4], R2
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
JMP + 3
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MMUUXX
4
DataDataMemoryMemory
Addr
Data
SignSignExtendExtend
00MMUUXX11
Addr Data
Data
11
MMUUXX
00
InstructionInstructionMemoryMemory
Shift Shift Left 2Left 2
00
MMUUXX11A
dd
erA
dd
er
Ad
der
Ad
der
AL
UA
LU
Rs
Rt
Offset, Addr, Immediate
Rt
Rd
SelA
SelB
Sel C
DataA
DataB
Register FileRegister File
Data C
CPU Operation ReviewCPU Operation Review
JE R1, R2, + 3
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PipeliningPipelining
Non Pipelined Process
Fetch Instr. Get Operands Execute Store Result
Instr.1
Instr.1
Instr.1
Instr.1
ƮMem ƮReg ƮALU ƮMem
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALU
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PipeliningPipelining
Non Pipelined Process
Fetch Instr. Get Operands Execute Store Result
Instr.2
Instr.2
Instr.2
Instr.2
ƮMem ƮReg ƮALU ƮMem
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALU
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PipeliningPipelining
Non Pipelined Process
● Clock Period =
● CPI (Clocks per Instruction) =
ƮMem ƮReg ƮALU ƮMem
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALU
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Instr.1
Instr.1
Instr.1
Instr.1
PipeliningPipelining
Pipelined Process
Fetch Instr. Get Operands Execute Store Result
Instr.2
Instr.2
Instr.2
Instr.2
ƮMem ƮReg ƮALU ƮMem
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
Instr.3
Instr.3
Instr.3
Instr.4
Instr.4
Instr.5
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PipeliningPipelining
Pipelined Process
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
Time Stage 1 Stage 2 Stage 3 Stage 4
1 Fetch Instr. 1
2 Fetch Instr. 2 Get Operands 1
3 Fetch Instr. 3 Get Operands 2 Execute 1
4 Fetch Instr. 4 Get Operands 3 Execute 2 Store Result 1
5 Fetch Instr. 5 Get Operands 4 Execute 3 Store Result 2
6 Fetch Instr. 6 Get Operands 5 Execute 4 Store Result 3
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PipeliningPipelining
Pipelined Process
● Clock Period =
● CPI =
ƮMem ƮReg ƮALU ƮMem
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
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Pipelining HazardsPipelining Hazards
Structural Hazards
Hardware can’t support instruction combination at a certain time.
Example:
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
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Pipelining HazardsPipelining Hazards
Data Hazards
One instruction has to wait for another to complete.
Example:
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
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Pipelining HazardsPipelining Hazards
Data Hazards
One instruction has to wait for another to complete.
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
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Pipelining HazardsPipelining Hazards
Data Hazards
One instruction has to wait for another to complete.
Forwarding:
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
ADD R3, R1, R2
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Pipelining HazardsPipelining Hazards
Control Hazards
Decision depends on the result of unfinished instruction.
Example:
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
Time Stage 1 Stage 2 Stage 3 Stage 4
1 Fetch Instr. 24
2 Fetch Instr. 28 Get Operands 24
3 ? Get Operands 28 Execute 24
4 ? Execute 28 Store Result 24
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Pipelining HazardsPipelining Hazards
Control Hazards
Decision depends on the result of unfinished instruction.
● Stall
● Predict
● Delayed Branch
PCPC
Instr.Mem.Instr.Mem.
Register File
Register File
Data Mem.Data Mem.
ALU ALUIRIR
XX
YY
Result
Result
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Multiple IssueMultiple Issue
Multiple Instructions Execution (in single clock)
● CPI < 1 or IPC > 1.
● Static / Dynamic
● Speculation
Example:
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Static Multiple IssueStatic Multiple Issue
Compiler Assisted
Issue Packet
● Set of instructions issued in a given clock cycle.
● Simply, one large instruction with multiple operations. Very Long Instruction Word (VLIW)
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Single-Issue DatapathSingle-Issue Datapath
PCPC
Instr.Mem.Instr.Mem. Data
Mem.Data Mem.
A L U
A L UI
FIF
0
1
2
0
1
2
0
1
0
1
SignExtendSign
Extend
+ +4
Sel A
Sel B
Sel C
DataA
DataB
DataC
IDID
+ +ShiftLeft
2
ShiftLeft
2
EXEX
Exception Address
ADDR
Data
Data
STST
Register Register FileFile
0
1
0
1
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Two-Issue DatapathTwo-Issue Datapath
PCPC
Instr.Mem.Instr.Mem.
Data Mem.Data Mem.
A L U
A L U
IFIF
0
1
2
0
1
2
0101
SignExtendSign
Extend
+ +4
Sel A1Sel B1
Sel C1
DataA1
DataB1
Data C1
IDID
+ +
EXEX
Exception Address
ADDR
Data
STST
Sel A2Sel B2
DataA2
DataB2
Sel C2
Data C2
SignExtendSign
Extend
0
10
1
+ +
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Two-Issue Datapath ExampleTwo-Issue Datapath Example
Two 32-bit instructions
ALU/JMP LD/ST
NOP Replacement
Example:
ALU/JMP LD/ST
Loop: LD R1, M[R2]
ADI R2, R2, – 4
ADD R1, R1, R3
JNE R2, 0, Loop ST M[R2+4], R1
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Single-Issue Datapath ExampleSingle-Issue Datapath Example
Loop: LD R1, M[R2]
ADD R1, R1, R3
ST M[R2], R1
ADI R2, R2, – 4
JNE R2, 0, Loop
Clock Fetch Decode Execute Memory Store1 LD R1, M[R2]2345 ADD R1, R1, R3
PCPC
Instr.Mem.Instr.Mem. Data
Mem.Data Mem.
A L U
A L U
IFIF
0
1
2
0
1
2
0
1
0
1
SignExtendSign
Extend
+ +
4
SelA
SelB
Sel C
DataA
DataB
Data C
IDID
+ +
EXEX
Exception Address
ADDRData
Data
STST 0
1
0
1
Register Register FileFile
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Single-Issue Datapath ExampleSingle-Issue Datapath Example
Loop: LD R1, M[R2]
ADD R1, R1, R3
ST M[R2], R1
ADI R2, R2, – 4
JNE R2, 0, Loop
Clock Fetch Decode Execute Memory Store1 LD2 R23 R2 + 04 M[R2]5 ADD R16789 ST
10 ADI11121314 JNE1516
Original Code:
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Single-Issue Datapath ExampleSingle-Issue Datapath Example
Clock Fetch Decode Execute Memory Store1 LD2 ADI R23 R2 + 04 M[R2]5 ADD R16789 ST
10 JNE1112
Loop: LD R1, M[R2]
ADI R2, R2, – 4
ADD R1, R1, R3
ST M[R2+4], R1
JNE R2, 0, Loop
Optimized Code:
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Two-Issue Datapath ExampleTwo-Issue Datapath Example
PCPC
Instr.Mem.Instr.Mem.
Data Mem.Data Mem.
A L U
A L U
IFIF
0
1
2
0
1
2
0101
SignExtendSign
Extend
+ +4
Sel A1Sel B1
Sel C1
DataA1
DataB1
Data C1
IDID
+ +
EXEX
Exception Address
ADDR
Data
STST
Sel A2Sel B2
DataA2
DataB2
Sel C2
Data C2
SignExtendSign
Extend
0
1
0
1
+ +
ALU/JMP LD/STLoop: LD R1, M[R2]
ADI R2, R2, – 4ADD R1, R1, R3JNE R2, 0, Loop ST M[R2+4], R1
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Two-Issue Datapath ExampleTwo-Issue Datapath Example
ALU/JMP LD/STLoop: LD R1, M[R2]
ADI R2, R2, – 4ADD R1, R1, R3JNE R2, 0, Loop ST M[R2+4], R1
Clock Fetch Decode Execute Memory Store1 LD2 ADI345 ADD6789 JNE ST
101112
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Dynamic Multiple IssueDynamic Multiple Issue
Compiler Assisted (to move dependencies apart)
Hardware Decided
● 0, 1 or more instructions issued in a given clock cycle. Superscalar Processors.
● Compiled code runs correctly independent of the issue rate or pipeline structure.
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Dynamic Pipeline SchedulingDynamic Pipeline Scheduling
Extension to Dynamic Multiple Issue
Hardware Decided
● Choose which instruction to execute in a given clock cycle.
● Compiled code runs correctly independent of the issue rate or pipeline structure
Example:
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Dynamic Pipeline SchedulingDynamic Pipeline Scheduling
Instruction Fetch, Decode & Issue Unit
Multiple Functional Units
Commit Unit InstructionFetch & Decode
InstructionFetch & Decode
IntegerFunctional Unit
IntegerFunctional Unit
Floating Point Functional UnitFloating Point
Functional Unit
Commit UnitCommit Unit
Floating Point Functional UnitFloating Point
Functional UnitInteger
Functional UnitInteger
Functional Unit
ReservationStation
ReservationStation
ReservationStation
ReservationStation
ReservationStation
ReservationStation
ReservationStation
ReservationStation
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Dynamic Pipeline SchedulingDynamic Pipeline Scheduling
Out-of-Order (O-o-O) Execution
An operand may be in a register, reorder buffer or yet to be produced by a functional unit.
In-Order Issue
In-Order Commit
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Speculative ExecutionSpeculative Execution
Hardware-Based
● Branch Predictions
● Load Addresses
In-Order Commit
● Assures correctness in case of wrong prediction
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Out-of-Order Scheduling ScoreboardOut-of-Order Scheduling Scoreboard
Scoreboarding (CDC 6600)
Pipeline:
●IF
●IS
●RD
●EX
●WB
Floating Point MultiplyFloating Point Multiply
RegisterFile
RegisterFile
Floating Point MultiplyFloating Point Multiply
Floating Point DivideFloating Point Divide
Floating Point AddFloating Point Add
Integer UnitInteger Unit
ScoreboardScoreboard
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Out-of-Order Scheduling ScoreboardOut-of-Order Scheduling Scoreboard
Scoreboarding (CDC 6600)
Pipeline:
●IF
●IS
●RD
●EX
●WB
Instruction Issue:
If the functional unit is available.
If no other active instruction has the same destination register.
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Out-of-Order Scheduling ScoreboardOut-of-Order Scheduling Scoreboard
Scoreboarding (CDC 6600)
Pipeline:
●IF
●IS
●RD
●EX
●WB
Read Operands:
No previously issued instruction has my operand as its destination.
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Out-of-Order Scheduling ScoreboardOut-of-Order Scheduling Scoreboard
Scoreboarding (CDC 6600)
Pipeline:
●IF
●IS
●RD
●EX
●WB Write Back Results:
Stalls instructions which write results to registers pending reads.
Example:
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U.
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. AddAdd
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. AddAdd AddAdd Mul 1Mul 1
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. AddAdd AddAdd Mul 1Mul 1 DivDiv
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. AddAdd Mul 1Mul 1 DivDiv
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. Mul 1Mul 1 AddAdd DivDiv
IFIF ISIS RDRD EXEX WBWB
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4747 / 50 / 50
Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. Mul 1Mul 1 AddAdd DivDiv
IFIF ISIS RDRD EXEX WBWB
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4848 / 50 / 50
Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. Mul 1Mul 1
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. Mul 1Mul 1
IFIF ISIS RDRD EXEX WBWB
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Out-of-Order Scheduling ExampleOut-of-Order Scheduling Example
Example:
Register Result StatusRegister Result Status
F1 F2 F3 F4 F5 F6 • • •
F.U. Mul 1Mul 1
IFIF ISIS RDRD EXEX WBWB
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Register RenamingRegister Renaming
Tomasulo’s Algorithm (IBM 360/91)
● Architectural Registers
● Physical (Hardware) Registers
● Dynamic Remap
Example:
Princess Sumaya University 22540 – Computer Arch. & Org (2) Computer Engineering Dept.Princess Sumaya University 22540 – Computer Arch. & Org (2) Computer Engineering Dept.
Chapter 4Chapter 4
Princess Sumaya University 22540 – Computer Arch. & Org (2) Computer Engineering Dept.Princess Sumaya University 22540 – Computer Arch. & Org (2) Computer Engineering Dept.
Exercise 4.12Exercise 4.13Exercise 4.14Exercise 4.16Exercise 4.17Exercise 4.20Exercise 4.21Exercise 4.22Exercise 4.23
Exercise 4.25Exercise 4.28Exercise 4.29Exercise 4.30Exercise 4.31Exercise 4.32Exercise 4.33Exercise 4.35Exercise 4.39