Programmable Logic: Introduction
Digital electronics: a few reminders to basic ideas and conceptsCombinational logicSequential logicSynchronous vs. Asynchronous designs
Programmable logic devices (PLD)Hardware oveview
Field-programmable gate arrays (FPGA)BasicsDesign flow
Course Material at http://pcweb.physik.uni-giessen.de/fpgaprak/
Basic Logic Gates
Example
Designing with NAND and NOR Gates
Implementation of NAND and NOR gates is easier than that of AND and OR gates (e.g., CMOS)
Combinational Logic
Has no memory =>present state depends only on the present input
))t(X(F)t(Z =
x1x2
xn
z1z2
zm
X = x1 x2... xn
Z = z1 z2... zm
Combinational-Circuit Building Blocks
MultiplexersDecodersEncodersCode ConvertersComparatorsAdders/SubtractorsMultipliersShifters
Example: Multiplexers: 2-to-1 Multiplexer
Have number of data inputs, one or more select inputs, and one outputIt passes the signal value on one of data inputs to the output
(a) Graphical symbol
f
s
w0
w1
0
1 fs
w0
w1
(c) Sum-of-products circuit
(b) Truth table
01
fs
w0
w110 sww'sf +=
Example: Full AdderModule Truth table
XYCin'Cin'XY'YCin'XCin'Y'XSum +++=XYCin'XYCinCin'XYYCin'XCout +++=
Sequential Circuits
Circuits with FeedbackOutputs = f(inputs, past inputs, past outputs)Basis for building "memory" into logic circuits
Door combination lock is an example of a sequential circuit
State => memoryState is can be "output" and "input" to combinational logic or to other sequential logic
"remember"
"load""data" "stored value"
"0"
"1"
"stored value"
Simplest Circuits with Feedback
Two inverters form a static memory cellWill hold value as long as it has power applied
How to get a new value into the memory cell?Selectively break feedback pathLoad new value into cell
period
duty cycle (in this case, 50%)
Clocks
Used to keep timeWait long enough for inputs to settleThen allow to have effect on value stored
Clocks are regular periodic signalsPeriod (time between ticks)Duty-cycle (time clock is high between ticks - expressed as % of period)
positive edge-triggered FF
negative edge-triggered FF
DCLK
QposQpos'QnegQneg'
100
Edge-Triggered Flip-Flops
Positive edge-triggeredInputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flopsInputs sampled on falling edge; outputs change after falling edge
behavior is the same unless input changeswhile the clock is high
D Q
CLK
positiveedge-triggered
flip-flop
D QG
CLK
transparent(level-sensitive)
latch
D
CLK
Qedge
Qlatch
Comparison of Latches and Flip-Flops
Timing Methodologies
Rules for interconnecting components and clocksGuarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elementsFocus on systems with edge-triggered flip-flops
Found in programmable logic devicesBasic rules for correct timing:
(1) Correct inputs, with respect to time, are provided to the flip-flops(2) No flip-flop changes state more than once per clocking event
there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized
clock
datachangingstable
input
clock
Tsu Th
clock
dataD Q D Q
Timing Methodologies (cont’d)
Definition of termsclock: periodic event, causes state of memory element to change;can be rising or falling edge, or high or low levelsetup time: minimum time before the clocking event by which the input must be stable (Tsu)hold time: minimum time after the clocking event until which theinput must remain stable (Th)
all measurements are made from the clocking event that is, the rising edge of the clock
Typical Timing Specifications
Positive edge-triggered D flip-flopSetup and hold timesMinimum clock widthPropagation delays (low to high, high to low, max and typical)
Th5ns
Tw 25ns
Tplh25ns13ns
Tphl40ns25ns
Tsu20ns
D
CLK
Q
Tsu20ns
Th5ns
Synchronous vs. Asynchronous Designs
Clocked synchronous circuitsInputs, state, and outputs sampled or changed in relation to acommon reference signal (the clock)
Asynchronous circuitsInputs, state, and outputs sampled or changed independently of acommon reference signal (glitches/hazards a major concern)
Stay away from asynchronous designs !Asynchronous inputs to synchronous circuits
Inputs can change at any time, will not meet setup/hold timesDangerous, synchronous inputs are greatly preferredCannot be avoided (e.g., reset signal, memory wait, user input)
Solution: synchronize with clock as early as possible !
Overview: IC Technology
In the early 80s :Generic logic circuits (Example TTL: SN7400)Complex applications assembled from basic building blocks: chipswith few ( < 10) hardwired logic functions
Many PCBs, interconnects, inflexibility, cost ...
90’s: VLSI Circuits + “glue logic”
Now three types of IC technologiesFull-custom ASICSemi-custom ASIC (gate array and standard cell)PLD (Programmable Logic Device)
NRE and unit cost metrics
Unit costthe monetary cost of manufacturing each copy of the system, excluding NRE cost
NRE cost (Non-Recurring Engineering cost)The one-time monetary cost of designing the system
total cost = NRE cost + unit cost * # of unitsper-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
General-purpose processors
Programmable device used in a variety of applications
Also known as “microprocessor”Features
Program memoryGeneral datapath with large register file and general ALU
User benefitsLow time-to-market and NRE costsHigh flexibility
Example: Pentium, ARM, …
IR PC
Registerfile
GeneralALU
DatapathController
Program memory
Assembly code for:
total = 0for i =1 to …
Control logic and
State register
Datamemory
Application-specific processors
Programmable processor optimized for a particular class of applications having common characteristicsFeatures
Program memoryOptimized datapathSpecial functional units
BenefitsSome flexibility, good performance, size and power
Example: DSP, Media Processor
IR PC
Registers
CustomALU
DatapathController
Program memory
Assembly code for:
total = 0for i =1 to …
Control logic and
State register
Datamemory
Single-purpose hardware
Digital circuit designed to execute exactly one program
coprocessor, accelerator Features
Contains components needed to execute a single programNo program memory
BenefitsFastLow powerSmall size
DatapathController
Control logic
State register
Datamemory
index
total
+
Full-custom/VLSI
All layers are optimized for an embedded system’s particular digital implementation
Placing transistorsSizing transistorsRouting wires
BenefitsExcellent performance, small size, low power
DrawbacksHigh NRE cost (e.g., $300k), long time-to-market
Semi-custom
Lower layers are fully or partially builtDesigners are left with routing of wires and maybe placing some blocks
BenefitsGood performance, good size, less NRE cost than a full-custom implementation (perhaps $10k to $100k)
DrawbacksStill require weeks to months to develop
PLD (Programmable Logic Device)
All layers already existDesigners can purchase an ICConnections on the IC are either created or destroyed to implement desired functionalityField-Programmable Gate Array (FPGA) very popular
BenefitsLow NRE costs, almost instant IC availability
DrawbacksBigger, expensive (perhaps $30 per unit), power hungry, slower
Comparison of different technologies
MediumLongMediumMediumFPGA
Very ShortNot Attainable
VeryShort
Low-MediumGeneric
LongLongLongHighASIP/DSP
ImpossibleVery LongVery LongVery HighASIC
Time to change code functionality
Time to high performance
Time untilrunning
Performance/Cost
Technology
Spee
d
Flex
ibili
ty
Roadmap for Programmable Logic
PROMPLAPALCPLDFPGA
PLD Definition
Programmable Logic Device (PLD):An integrated circuit chip that can be configured by end use to implement different digital hardware Also known as “Field Programmable Logic Device (FPLD) “
PLD Advantages
Short design timeLess expensive at low volume
Volume
Cost
Nonrecurring engineering cost
PLD
ASIC
PLD Categorization
PLD
SPLD HCPLD
FPGACPLD
PLA PAL
Simple PLD High Capacity PLD
Programmable Logic Array Programmable Array Logic
Complex PLD Field Programmable Gate Array
Programmable ROM (PROM)
2 N x M ROM
N input M output
Address: N bits; Output word: M bits
ROM contains 2 N words of M bits each
The input bits decide the particular word that becomes available on output lines
Logic Diagram of 8x3 PROM
Combinational Circuit Implementation using PROM
010111
001011
100101
010001
001110
110010
010100
001000
I0 I1 I2 F0 F1 F2
F0 F1 F2
PROM Types
Programmable PROM Break links through current pulsesWrite once, Read multiple times
Erasable PROM (EPROM)Program with ultraviolet light Write multiple times, Read multiple times
Electrically Erasable PROM (EEPROM)/ Flash MemoryProgram with electrical signalWrite multiple times, Read multiple times