Prototyping & Functional Verification Prototyping & Functional Verification for Radiation Tolerantfor Radiation Tolerant Space-Flight Space-Flight Systems DesignsSystems Designs
PresentersPresenters
Minal Sawant, Actel™Minal Sawant, Actel™
Manager, High Reliability Product MarketingManager, High Reliability Product Marketing
Jaroslaw (Jerry) Kaczynski, Aldec®, Inc.Jaroslaw (Jerry) Kaczynski, Aldec®, Inc.
Technical Marketing EngineerTechnical Marketing Engineer
1 © 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
AgendaAgenda
Introduction Today’s Prototyping of RTAX-S/SL and RTSX-SU FPGAs Aldec/Actel Innovative Prototyping Solution Customer Case Study ROI & Benefits Actel RTAX-S/SL and RTSX-SU Device Family Overview Actel ProASIC® FPGA Technology Overview Aldec RTAX-S/SL prototyping adaptors Aldec RTSX-SU prototyping adaptors Aldec RTAX2A3P EDIF Netlist and PDC File Conversion Summary Question and Answer
2 © 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Today’s Prototyping SolutionToday’s Prototyping Solution
Socket + AX/SX-A Approach
Good solution, but several design iterations could require several of the OTP (One Time Programmable) or Actel AX/SX-A commercial chips to complete the design.
Weak Point
The potential risk for using several of these OTP or AX/SX-A devices could add to the overall project cost and impact the budget.
3© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Today’s Prototyping Design FlowToday’s Prototyping Design Flow
4© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Create and Verify Design Code
Create and Verify Design Code
Synthesize and Implement for OTP chip
Synthesize and Implement for OTP chip
Test in Hardware:Results OK?
Throw AwayOTP Chip!
Throw AwayOTP Chip!
Synthesize and Implement for target technology
Synthesize and Implement for target technology
Final Hardware Tests
Y
N
Modify and Verify Design Code
Modify and Verify Design Code
www.aldec.comwww.aldec.com
Aldec Re-programmable SolutionAldec Re-programmable Solution
Ability to prototype RTAX-S/SL and RTSX-SU designs using re-programmable Actel Flash ProASIC®3E FPGA family chips
Adaptor board is footprint-compatible with the final RTAX-S/SL and RTSX-SU device
Programming connector (JTAG) allows on-the-fly reprogramming of the device without detaching the adaptor from the target PCB
EDIF netlist converter allows to migrate from RTAX-S/SL and RTSX-SU to ProASIC®3E FPGA easily
Design efficiency is achieved, saving Development Time and Costs
5© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Aldec Complimentary Design Flow 1Aldec Complimentary Design Flow 1
6© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Create and Verify Design Code
Create and Verify Design Code
Synthesize and Implement for ProASIC® FPGA
Synthesize and Implement for ProASIC® FPGA
Test in Hardware:Results OK?
Modify and Verify Design Code
Modify and Verify Design Code
Synthesize and Implement for target technology
Synthesize and Implement for target technology
Final Hardware Tests
Y
N
Preferred flow for PURE HDL Designs
www.aldec.comwww.aldec.com7© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Aldec Complimentary Design Flow 2Aldec Complimentary Design Flow 2Generate netlist for target technology
Generate netlist for target technology
Netlist ConversionNetlist Conversion
Test in Hardware:Results OK?
Modify and Verify Design Code
Modify and Verify Design Code
Implement for target technology
Implement for target technology
Final Hardware Tests
Y
N
Flow for schematic and legacy designs
Implement for ProASIC® FPGAImplement for
ProASIC® FPGA
www.aldec.comwww.aldec.com
Customer Case StudyCustomer Case Study
8© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Space Industry Customer
Undisclosed due to company policy
Target Device RTAX2000S CQ256 in 3 distinct designs
Size 20% in smallest design, 85% in largest
Design Description Three distinctly different designs in the same project
Project NeedMultiple test boards
Meet schedule
Stay within Budget
Key Benefits of Using Aldec Solution
Allowed for verification of the flight design with no changes to flight net-list. Saved thousands of dollars for material and many man hours..
www.aldec.comwww.aldec.com
Customer Case StudyCustomer Case Study
9© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Key Development Bottlenecks RESOLVED
1 Eliminated uncertainty between flight and prototype designs
2 Allowed for verification of the flight design with no changes to flight net-list
3 Significantly fewer number of simulations
4 Reduce System-Level Bugs before Programming OTP
5Allowed the creation of multiple prototypes without the need for extensive simulation time
6 Multiple bug fixes early in the design cycle with less engineering time
7 Eased component integration with multiple vendors
9 Proved conceptual designs without using OTP parts
10 Much Faster Project Completion at significantly less cost
www.aldec.comwww.aldec.com
ROIROI
10© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Three Concurrent Projects
Engineer Resources 9
ROI – Using Aldec Prototyping Solution
Development Time Saved Months
OTP Devices Saved 20
Cost Savings material only >$100,000
Development Issues Resolved >20
www.aldec.com
Minal Sawant, Actel™Minal Sawant, Actel™Manager, High Reliability Product MarketingManager, High Reliability Product Marketing
Actel RTAX-S/SL and RTSX-SU Device Family Overview
Actel ProASIC®3 FPGA Technology Overview
11© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Actel RTAX-S/SL Devices • Radiation-tolerant FPGA alternative to RH ASICs
Up to 4 million system gates (approximately 500,000 ASIC gates)
Up to 540 kbits embedded block RAM
Designed for space with Single Event Upset (SEU) enhancements 0.15µm, 7-layer metal CMOS with Antifuse, manufactured at UMC
Live at Power-up (LAPU)
Single chip
Low power consumption
In flight today
Cosmo-Skymed 1, 2, 3
Mars Phoenix
Chandrayaan1
Sicral 1B
www.aldec.comwww.aldec.com
RTAX-S/SL FPGA Family
• New devices RTAX250S/SL in CG/LG624 package Dash-1 and SL versions of RTAX4000S
624-CCGA/LGA
RTAX250S/SL RTAX1000S/SL RTAX2000S/SL RTAX4000S/SLDedicated Registers 1,408 6,048 10,752 20,160I/O Registers 744 1,548 2,052 2,520Total Modules 4,224 18,144 32,256 60,480RAM Blocks 12 36 64 120Total RAM Bits 54K 162K 288K 540KMax User I/Os 248 516 684 840
208-CQFP256-CQFP
352-CQFP 352-CQFP 352-CQFP 352-CQFP624-CCGA/LGA 624-CCGA/LGA 624-CCGA/LGA
1152-CCGA/LGA1272-CCGA/LGA
Status QUALIFIED SILICON NOW SHIPPING!
Packages
QUALIFIED SILICON NOW SHIPPING!
www.aldec.comwww.aldec.com
RTAX-S/SL Device Architecture
CoreTile
RAM Block
• Built using Core Tiles RTAX1000S/SL – 3x3 Core Tiles
RTAX2000S/SL – 4x4 Core TilesRTAX4000S/SL – 6x5 Core Tiles
Each Core Tile has: 336 SuperClusters 4 Blocks of RAM
RTAX250S/SL – 2x2 Mini Core Tiles
Each Mini Core Tile has: 176 SuperClusters 3 Blocks of RAM
SCSCSCSCSCSC
SCSCSCSCSCSCRD
RD
C RRX
TX
RX
TX
RX
TX
RX
TX
BC CC R
SuperCluster
www.aldec.comwww.aldec.com
RTAX-S/SL SuperCluster
C RRX
TX
RX
TX
RX
TX
RX
TX
BC CC R
D Q
CLKCLKB
SEU Enhanced Flip-Flop in R Cell
Voter Gate
Two correct inputs outvote single incorrect (radiation upset) input
Self-corrects asynchronously
www.aldec.comwww.aldec.com
Actel RTSX-SU FamilyActel RTSX-SU Family• RTSX-SU Features
Designed specifically for Space Applications Up to 2,012 SEU Hardened Flip-Flops eliminate user-designed TMR Single Event Latch-up Immune Supports Hot-Swapping and Cold Sparing Configurable I/O support multiple 5.0V and 3.3V I/O standards Pin Compatible with commercial SX-A devices for easy prototyping
• QML Certified Devices QML Class Q available today
Mil Std 883 Class B Actel Extended flow
QML Class V submission planned for 2009
“EV” flow available today All process steps of QML-V 40-week lead time applies
(2000 Hr Group C)
RTSX32SU RTSX72SUDedicated Registers 1,080 2,012Total Modules 2,880 6,036Max User I/Os 227 360
84-CQFP208-CQFP 208-CQFP256-CQFP 256-CQFP256-CCLG
624-CCGA/LGA
Packages
Manufacturing Process Flows
QML-V coming soon
883BE-Flow
EV-Flow
www.aldec.comwww.aldec.com
ProASICProASIC®®3 FPGA Introduction3 FPGA Introduction Portfolio includes ProASIC3 and ProASIC3E families Device Features
Devices range from 15,000 to 3 million system gates Up to 504 Kbits of true Dual-Port SRAM Up to 620 user I/Os Up to 6 PLLs 1 Kb User Flash memory (FlashRom) Secure ISP using on chip 128 bit AES
encryption/decryption Industry-standard ARM® Cortex-M1 support for the family Support for wide range of packages including
PQ, VQ, TQ, QN, FG RoHS compliant packages available
Offers pin compatibility across families for easy migration Support for various IO standards
Standard IO: LVTTL, LVCMOS, PCI Differential IO: LVPECL, LVDS…. Advanced IO: (ProASIC3E) : GTL, GTL+, HSTL, SSTL2, SSTL3….
17© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
The Advantages of FlashThe Advantages of Flash
Word Select / Bias
Output
InputBit Select 1Bit Select 2
SWITCH
Floating Gate
Flash
MEMORY•Erase•Program•Sense
VCC
A B
Word line
BitLine
SRAMBitLine
VCC
Smaller size: more switches for greater routing flexibility Low power: less capacitance and resistance Reprogrammable and non-volatile
18© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Device ArchitectureDevice Architecture Built using VersaTiles Up to 75,264 VersaTiles
Each VersaTile Can Be 3-input Combinatorial Gate Latch D-Flip-flop with Enable
Register-intensive Applications Handled Easily
All Input Signals Can Be Inverted Easier Technology Mapping and
Netlist Optimizations
Any 3-Input Any 3-Input Combinatorial Combinatorial
FunctionFunctionAABBCC
D Flip-Flop With Enable D Flip-Flop With Enable and Set or Resetand Set or Reset
DD
CLKCLK
Set or ResetSet or Reset
EnableEnable
VersaTile
© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
ProASIC3 FPGA Product Line-UpProASIC3 FPGA Product Line-Up
© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.com
Jaroslaw (Jerry) Kaczynski, Aldec®, Inc.Jaroslaw (Jerry) Kaczynski, Aldec®, Inc.Technical Marketing EngineerTechnical Marketing Engineer
Aldec Prototyping AdaptorsEDIF Netlist Converter
21© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
A3PE1500/3000-CQ256 AdaptorA3PE1500/3000-CQ256 Adaptor
Description Adaptor size: 43.07mm x 43.07mm
The following elements reside on the top part of the adaptor
Actel ProASIC3E device A3PE1500-FGG484 or A3PE3000-FGG484
JTAG connector
Capacitors, resistors
The following elements reside on the bottom part of the adaptor
Leads that mimic CQ256 package
Capacitors A3PE1500-FGG484
orA3PE3000-
FGG484
JTAG Connector
Leads that mimic CQ256 package
© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
A3PE1500/3000-CQ352 AdaptorA3PE1500/3000-CQ352 Adaptor
Description Adaptor size: 55mm x 55mm
The following elements reside on the top part of the adaptor
Actel ProASIC3E FPGA device A3PE1500-FGG484 or A3PE3000-FGG484
JTAG connector
Power connector
Capacitors, resistors
The following elements reside on the bottom part of the adaptor
Leads that mimic CQ352 package
CapacitorsA3PE1500-FGG484or
A3PE3000-FGG484
JTAG Connector
Power Connector
Leads that mimic CQ352 package
23© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
A3PE3000-CG624 AdaptorA3PE3000-CG624 Adaptor
Description Adaptor size: 32.5mm x 34mm
The following elements reside on the top part of the adaptor
Actel ProASIC3E FPGA device, A3PE3000-FGG896
JTAG connector
Capacitors, resistors
The following elements reside on the bottom part of the adaptor
Leads that mimic CG624 package
Capacitors
A3PE3000-FGG896
JTAG Connector
Ball grid array that mimics CG624 package
24© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
RTAX4000S/SL-CQ352 AdaptorRTAX4000S/SL-CQ352 Adaptor
25© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Description Adaptor size: 55mm x 55mm
The following elements reside on the top part of the Daughter Board AND Mother Board
Actel ProASIC3E FPGA device A3PE3000-FGG896
JTAG connector
Capacitors, resistors
The following elements reside on the Bottom part of the adaptor
Leads that mimic CQ352 package
www.aldec.comwww.aldec.com
RTAX4000S/SL-CQ352 RTAX4000S/SL-CQ352
IO/Clocks
IO/Clocks
IO/Clocks
IO/ClocksIO/Clocks
IOIO
FP GA 1 M other B oard
FP GA 2D a u g h te r Bo a rd
C Q352RTA X-4000S
leads
I OI O
1 0 ( s i n g l e e n d e d )
1 4 7 ( s i n g l e e n d e d )
1 6 ( L V D S s u p p o r t e d )
1 5 0 ( L V D S s u p p o r t e d )
1 0 ( s i n g l e e n d e d )I O / C l o c k s H
igh
Sp
ee
d C
on
ne
cto
rsIO/Clocks
8x MMCX 8x MMCX
8 (s ingle ended) 8 (s ingle ended)
DescriptionCQ352 leads connected to FPGA1 on Mother Board (166 I/Os, 1:1 mapping), single ended and LVDS transmissions supported
FPGA2 on Daughter Board is connected to FPGA1 (on Mother Board) only
167 interconnections between FPGA1 and FPGA2 (single ended)
Additional 8 micro-coax connectors for each FPGA
External clocks can be delivered
Can be used as additional interconnections between FPGA1 and FPGA2
Adaptor Block Diagram
26© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Configuration TableConfiguration Table
* The adaptor can be used to prototype the specified RTAX-S/SL device only if the customer design does not exceed the capacity of the flash device on top of the adaptor.
•**RTAX2000S–CG624
•*RTAX4000S–CQ352
•**•*RTAX2000S–CQ352
•*RTAX2000S–CQ256
•RTAX1000S–CG624
••RTAX1000S–CQ352
••RTAX250S–CQ352
A3PE3000-CG624A3PE3000-CQ352A3PE1500-CQ352A3PE1500-CQ256
ADAPTOR BOARD TO BE USED FOR PROTOTYPINGRTAX-S DEVICE
TO PROTOTYPE
** Industrial configurations available for CQ352 and CG624 adaptors
27© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
RTSX-RTSX-SU PrototypingSU Prototyping NEW Adaptors
28 © 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
Description Stacked Architecture
Mother Board with Actel ProASIC3 FPGA and RTSX-SU compatible leads
Daughter Board with Power components and JTAG connector
Packages supported CQ208 CQ256 CG624
1:1 I/O and bank mapping Powered from the target board
(through RTSX-SU pins)
www.aldec.comwww.aldec.com
RTSX-SU DEVICE
TO PROTOTYPE
ADAPTOR BOARD TO BE USED FOR PROTOTYPING
Configuration TableConfiguration Table
*The adaptor is available in ACT-RTSX-CG624-3V3 and ACT-RTSX-CG624-5V option
RT54SX72SU-CG624
RT54SX72SU-CQ256
•RT54SX72SU-CQ208
•RT54SX32SU–CQ256
ACT-RTSX-CG624ACT-RTSX-CQ256ACT-RTSX-CQ208
••
•*
RT54SX32SU–CQ208 •
Available Today, six week shipping lead time
29© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
RTAX2A3P EDIF Netlist ConverterRTAX2A3P EDIF Netlist Converter
RTAX2A3P EDIF Netlist Converterperforms automatic conversion ofthe RTAX-S/SL and RTSX-SUEDIF netlist to ProASIC3E FPGAEDIF netlist
Features
Conversion of combinatorial primitives
Conversion of sequential primitives
Conversion of I/O macros
Memory conversion
Replacement of sequential primitives to TMR primitives
30© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
RTAX2A3P EDIF Netlist ConverterRTAX2A3P EDIF Netlist Converter
Input RTAX-S/SL or RTSX-SU EDIF netlist RTAX-S/SL or RTSX-SU PDC file
Output ProASIC3E FPGA EDIF netlist ProASIC3E FPGA PDC file for
selected adaptor board
RTAX and RTSX to ProASIC3E FPGA
Converter
PrimitivesLibrary
Implementation for ProASIC3E FPGA in Actel Designer
RTAX-S/SLRTSX-SU
EDIF netlist
Pin LocationLibrary
RTAX-S/SL RTSX-SU PDC file
ProASIC3E FPGA EDIF
netlist
ProASIC3E FPGA PDC
file
31© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
RTAX2A3P EDIF Netlist ConverterRTAX2A3P EDIF Netlist Converter
Primitives Mapping
Number of RTAX-S
primitives
Number of ProASIC3E
FPGA primitives
Best Case mapping 1 1
Worst Case mapping 1 2.5
Average mapping 1 1.5
32© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
SummarySummary
Reduce chip costs Save Development Time – “Re-Programmability” ProASIC®3 FPGA “flash-based” technology Wide Device & Package Support: CQ208, CQ256, CQ352
& CG624 packages Footprint compatible adaptors Automatic translation of netlist, memories and constraints Customer proven with over 100 units shipped worldwide
33© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Aldec Prototyping CustomersAldec Prototyping Customers
34© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.
www.aldec.comwww.aldec.com
Q&A and Contact InfoQ&A and Contact Info
ALDEC®ALDEC®
Website: http://www.aldec.com
Tel. USA: +1-702-990-4400Tel. Canada: +1-613-867-8600Fax USA/Can: +1-702-990-4414E-mail: [email protected]. Europe: +33-6-80-32-60-56Fax Europe: +33-1-46-34-85-91E-mail Europe: [email protected]
ALDEC®ALDEC®
Website: http://www.aldec.com
Tel. USA: +1-702-990-4400Tel. Canada: +1-613-867-8600Fax USA/Can: +1-702-990-4414E-mail: [email protected]. Europe: +33-6-80-32-60-56Fax Europe: +33-1-46-34-85-91E-mail Europe: [email protected]
• To download Aldec Simulator Evaluation, go to To download Aldec Simulator Evaluation, go to http://www.aldec.com/downloads• To attend additional ALDEC events, go to To attend additional ALDEC events, go to www.aldec.com/events/ • To download more about To download more about Actel Products Actel Products go to go to
http://www.actel.com/products/solutions/milaero/default.aspx http://www.actel.com/products/solutions/milaero/default.aspx • To learn more about To learn more about Actel Events go Actel Events go to to
http://www.actel.com/company/events/default.aspxhttp://www.actel.com/company/events/default.aspx
Actel™Actel™
Website: http://www.actel.com/ Tel. USA: +1-650-318-4200Tel. Canada: +1-613-726-7575Fax USA/Can: +1-650-318-4600E-mail: [email protected]. Europe: +44 (0) 1276.609300Fax Europe: +44 (0) 1276.607540E-mail Europe: [email protected]
Actel™Actel™
Website: http://www.actel.com/ Tel. USA: +1-650-318-4200Tel. Canada: +1-613-726-7575Fax USA/Can: +1-650-318-4600E-mail: [email protected]. Europe: +44 (0) 1276.609300Fax Europe: +44 (0) 1276.607540E-mail Europe: [email protected]
35© 2009 Aldec, Inc. Active-HDL , Riviera-PRO, ALINT, HES, CoVer and Aldec are trademarks of Aldec, Inc. All other trademarks or registered trademarks are property of their respective owners.