Runjie Zhang
Mike Gibson
ECE 6332 Final Presentation
Dec 1, 2009
FPGA Overview
Project Overview
Leakage Reduction Analysis
Concluding Remarks
Future Work
Logic, switch, I/O blocks, interconnect
Advantages
Flexible, widely applicable, reconfigurable
Low non-recurring engineering costs
Disadvantages
Increased complexity vs. ASICs
Increased Complexity = Increased Energy
Sub-threshold operation = Reduced energy
Leakage major factor in sub-threshold
What reduction methods most effective?
Focused on SRAM-based CLB architecture
16 programmed muxes per CLB
4 BLEs per CLB
1 DFF, 4-input LUT, 2-input mux per BLE
In total: 328 SRAM cells 400 Transmission Gates 172 Inverters
2 configurations: 2, 4 series inverters
Base characteristics at 300mV: Total Delay: 156 ns Total Energy: 46.9 pJ Leakage Energy: 38.5 pJ Leakage Current: -771nA
Four leakage methods tested
Stacking
Dual-Vt architecture
Sub-threshold-specific body biasing
MTCMOS architecture
Reduce Leakage current for 3 reasons:
1. Decrease VGS
2. Body biasing3. DIBL
Stacking every inverter
in the FPGA 0.00E+00
1.00E-06
2.00E-06
3.00E-06
4.00E-06
5.00E-06
6.00E-06
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Leakage Current
Pure
Pure_Stack
-14.5
-14
-13.5
-13
-12.5
-12
-11.5
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Energy
Pure_totE
Pure_Stack_totE
Pure_lkgE
Pure_Stack_lkgE
-14
-13.5
-13
-12.5
-12
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Total Energy
Pure_totE
Pure_Stack_totE
-14.5
-14
-13.5
-13
-12.5
-12
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Leakage Energy
Pure_lkgE
Pure_Stack_lkgE 0.00E+00
5.00E-07
1.00E-06
1.50E-06
2.00E-06
Delay
Pure
Pure_Stack
Which path is critical in a FPGA?
Basic Idea:
Low Vt in critical path --- maintain speedHigh Vt in other part –--- reduce leakage
0.00E+00
1.00E-06
2.00E-06
3.00E-06
4.00E-06
5.00E-06
6.00E-06
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Leakage Current
Pure
HVt_BX
0.00E+00
2.00E-07
4.00E-07
6.00E-07
8.00E-07
1.00E-06
1.20E-06
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Delay
Pure
HVt_BX
0.00E+00
5.00E-14
1.00E-13
1.50E-13
2.00E-13
2.50E-13
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Total Energy
Pure
HVt_BX0.00E+00
5.00E-14
1.00E-13
1.50E-13
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Leakage Energy
Pure
HVt_BX
Basic Idea:
Put blocks in sleep mode when not in use
Which transistors can be turned off?
FPGANormal Circuit
0.00E+00
1.00E-06
2.00E-06
3.00E-06
4.00E-06
5.00E-06
6.00E-06
7.00E-06
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Leakage Current
Pure
MT_BX&Inv
0.00E+00
1.00E-07
2.00E-07
3.00E-07
4.00E-07
5.00E-07
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Delay
Pure
MT_BX&Inv
0.00E+00
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Leakage Energy
Pure
MT_BX&Inv
0.00E+00
5.00E-14
1.00E-13
1.50E-13
2.00E-13
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Total Energy
Pure
MT_BX&Inv
0.00E+00
1.00E-06
2.00E-06
3.00E-06
4.00E-06
5.00E-06
6.00E-06
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Leakage Current
Pure
HVt_BX
HVt_BX_Stack0.00E+00
5.00E-07
1.00E-06
1.50E-06
2.00E-06
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Delay
Pure
HVt_BX
HVt_BX_Stack
0.00E+00
2.00E-14
4.00E-14
6.00E-14
8.00E-14
1.00E-13
1.20E-13
1.40E-13
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Leakage Energy
Pure
HVt_BX
HVt_BX_Stack 0.00E+00
5.00E-14
1.00E-13
1.50E-13
2.00E-13
2.50E-13
3.00E-13
1000m
V
900m
V
800m
V
700m
V
600m
V
450m
V
400m
V
350m
V
300m
V
250m
V
200m
V
Total Energy
Pure
HVt_BX
HVt_BX_Stack
0.00E+00
1.00E-06
2.00E-06
3.00E-06
4.00E-06
5.00E-06
6.00E-06
7.00E-06
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Leakage Current
Pure
MT_BX&Inv
HVt_BX, MT_Inv0.00E+00
1.00E-07
2.00E-07
3.00E-07
4.00E-07
5.00E-07
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Delay
Pure
MT_BX&Inv
HVt_BX, MT_Inv
0.00E+00
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Leakage Energy
Pure
MT_BX&Inv
HVt_BX, MT_Inv
0.00E+00
5.00E-14
1.00E-13
1.50E-13
2.00E-13
1V
900m
V
800m
V
700m
V
600m
V
500m
V
400m
V
350m
V
300m
V
250m
V
Total Energy
Pure
MT_BX&Inv
HVt_BX, MT_Inv
Connect body to opposite rail
Advantages:
Reduces delay
No added area cost
Easy to integrate with other methods
Disadvantages:
Increased leakage
Could destroy device in super-threshold
No significant improvement observed
Energy limits FPGA applications
Leakage comprises most sub-Vt energy
Not all methods worthwhile in FPGA
MTCMOS, Dual-Vt SRAM most effective
Configuration vs. Runtime considerations
Optimize other FPGA components
Interconnect
Clock networks
Optimize overall FPGA architecture
Optimize for both configuration, runtime
Analyze other FPGA configurations