Sahand University of Technology
The three major operations done on biological signals using Op-Amp:
1) Amplifications and Attenuations
2) DC offsetting: add or subtract a DC
3) Shape its frequency content: Filtering
2
Ideal Op-Amp
Figure 3.1 Op-amp equivalent circuit.
The two inputs are 1 and 2. A differential voltage between them
causes current flow through the differential resistance Rd. The
differential voltage is multiplied by A, the gain of the op amp, to
generate the output-voltage source. Any current flowing to the output
terminal vo must pass through the output resistance Ro.
Most bioelectric signals are small and require amplifications
3
20 transistors
11 resistors
1 capacitor
Inside the Op-Amp (IC-chip)
4
Ideal Characteristics
1- A = (gain is infinity)
2- Vo = 0, when v1 = v2 (no offset voltage)
3- Rd = (input impedance is infinity)
4- R0 = 0 (output impedance is zero)
5- Bandwidth = (no frequency response limitations) and no phase shift
5
Two Basic Rules
Rule 1
When the op-amp output is in its linear range, the two input terminals
are at the same voltage.
Rule 2
No current flows into or out of either input terminal of the op amp. 6
Inverting Amplifier
i
f
i
oi
i
f
oR
R
v
vGv
R
Rv
Figure 3.3 (a) An inverting amplified. Current flowing through the
input resistor Ri also flows through the feedback resistor Rf . (b) The
input-output plot shows a slope of -Rf / Ri in the central portion, but the
output saturates at about ±13 V.
Ri i
o
i
Rf
i
+
(a)
10 V
10 V
(b)
i
o
Slope = -Rf / Ri
-10 V
-10 V
7
Summing Amplifier
2
2
1
1
R
v
R
vRv fo
1
o
+
R2
R1 Rf
2
8
Example 3.1: The output of a
biopotential preamplifier that measures
the electro-oculogram is an undesired dc
voltage of ±5 V due to electrode half-cell
potentials, with a desired signal of ±5 V superimposed. Design a circuit that will
balance the dc voltage to zero and
provide a gain of -10 for the desired
signal without saturating the op amp.
i
o
o
+10
0 Time
i + b /2
-10
Volt
age,
V
i
o
o
+10
0 Time
i + b /2
-10
Vo
ltag
e, V
The output of a biopotential preamplifier that measures the electro-
oculogram is an undesired dc voltage of ±5 V due to electrode half-
cell potentials, with a desired signal of ±5 V superimposed. Design a
circuit that will balance the dc voltage to zero and provide a gain of -
10 for the desired signal without saturating the op amp.
9
Follower ( buffer)
1 Gvv io
Used as a buffer, to prevent a high source resistance from being
loaded down by a low-resistance load. An another word it prevent
drawing current from the source.
o i +
10
Noninverting Amplifier
i
f
i
if
i
i
if
oR
R
R
RRGv
R
RRv 1
o
10 V
10 V
i
Slope = (Rf + Ri )/ Ri
-10 V
-10 V
Rf
o i
i
+
-
i
Ri
11
Differential Amplifiers
)( 34
3
4 vvR
Rvo
3
4
34 R
R
vv
vG o
d
c
d
G
GCMRR
R4
R4
R3
R3 v3
v4 vo
Differential Gain Gd
Common-mode rejection ratio CMMR
Common Mode Gain Gc
For ideal op amp if the inputs are equal then the
output = 0, and the Gc =0. No differential
amplifier perfectly rejects the common-mode
voltage.
Typical values range from 100 to 10,000
Disadvantage of one-op-amp differential amplifier is its low input resistance 12
Instrumentation Amplifiers
1
12
21
43
121
21243
2
)(
R
RR
vv
vvG
iRvv
RRRivv
d
12
3
4
1
122vv
R
R
R
RRvo
Advantages: High input impedance, High CMRR, Variable gain
Differential Mode Gain
13
Comparator – No Hysteresis
o
i ref
10 V
-10 V
-10 V
v2
+15
-15
i
o
+
R1
R1
R2
ref
If (vi+vref) > 0 then vo = -13 V else vo = +13 V
R1 will prevent overdriving the op-amp
v1 > v2, vo = -13 V
v1 < v2, vo = +13 V
14
Comparator – With Hysteresis
i
o
+
R1
R1
R2
R3
ref
o
i - ref
10 V
-10 V
With hysteresis
-10 V 10 V
Width of the Hysteresis = 4 x VR3
Reduces multiple transitions due to mV noise levels by moving the
threshold value after each transition.
15
Rectifier
10 V
(b)
-10 V
o
i
-10 V 10 V
(c)
D
v o i
+
Ri = 2 kW Rf = 1 kW
RL = 3 kW
(a) Full-wave precision rectifier. For i > 0, the noninverting amplifier
at the top is active (D2 and D3 are on), making o > 0. For i < 0, the
inverting amplifier at the bottom is active, making o > 0. Circuit gain
may be adjusted with a single pot. (b) Input-output characteristics show
saturation when o > +13 V. (c) One-op-amp full-wave rectifier. For i
< 0, the circuit behaves like the inverting amplifier rectifier with a gain
of +0.5. For i > 0, the op amp disconnects and the passive resistor
chain yields a gain of +0.5.
+
(a)
D3
R
R
o=
i
+
D2 D1
D4
xR (1-x)R
i
x
16
Rectifier
(a)
D
v o
i
+
xRi (1-x)R
a) For i > 0, D2 and D3 conduct, whereas D1 and D4 are reverse-
biased.
b) For i < 0, D1 and D4 conduct, whereas D2 and D3 are reverse-
biased.
+
D3
R
R
o=
i
+
D2 D1
D4
xR (1-x)R
i
x
R
17
Figure 3.8 (a) A logarithmic amplifier makes use of the fact that a
transistor's VBE is related to the logarithm of its collector current. With
the switch thrown in the alternate position, the circuit gain is increased
by 10. (b) Input-output characteristics show that the logarithmic relation
is obtained for only one polarity; 1 and 10 gains are indicated.
(a)
Rf
Ic
Rf /9
o
Ri i
+
(b)
10 V
-10 V
v o
i
-10 V
1
10
10 V
Logarithmic Amplifiers
1310log06.0
i
io
R
vv at 27 oC
S
CBE
I
IV log06.0
18
Logarithmic Amplifiers
Antilog (exponential) circuits are made by interchanging the resistor
and semiconductor.
Uses of Log Amplifier
1. Multiply variable
2. Divide variable
3. Raise variable to a power
4. Compress large dynamic range into small ones
5. Linearize the output of devices
19
Integrators
jR
R
jV
jV
i
f
i
o
1
1
ff
c
i
f
i
o
CRf
R
R
v
v
2
1
for f < fc
i
f
i
o
t
ici
fi
o
Z
Z
jV
jV
vdtvCR
v
)(
)(
1 1
0
A large resistor Rf is used to prevent saturation 20
Integrators
Figure 3.9 A three-mode integrator With S1 open and S2 closed, the
dc circuit behaves as an inverting amplifier. Thus o = ic and o can
be set to any desired initial conduction. With S1 closed and S2 open,
the circuit integrates. With both switches open, the circuit holds o
constant, making possible a leisurely readout. 21
R
+ FET
Piezo-electric
sensor
o
C
is
isR isC
dqs/ dt = is = K dx/dt
Long cables may be used without changing sensor sensitivity or time
constant.
Example 3.2 The output of the piezoelectric sensor may be fed directly into the
negative input of the integrator as shown below. Analyze the circuit
of this charge amplifier and discuss its advantages.
isC = isR = 0
vo = -vc
C
Kxdt
dt
Kdx
Cv
t
o 1
0
1
22
Differentiators
Figure 3.11 A differentiator The dashed lines indicate that a small
capacitor must usually be added across the feedback resistor to
prevent oscillation.
RCjZ
Z
jV
jV
dt
dvRCv
i
f
i
o
io
)(
)(
23
Active Filters- Low-Pass Filter
+
Ri
Rf
(a)
Cf
i
o
Active filters (a) A low-pass filter attenuates high frequencies
ffi
f
i
o
CRjR
R
jV
jV
1
1Gain = G =
|G|
freq fc = 1/2RiCf
Rf/Ri
0.707 Rf/Ri
24
Active Filters (High-Pass Filter)
Ci
+
Ri
i o
(b)
Rf
Active filters (b) A high-pass filter attenuates low frequencies and blocks dc.
ii
ii
i
f
i
o
CRj
CRj
R
R
jV
jV
1Gain = G =
|G|
freq fc = 1/2RiCf
Rf/Ri
0.707 Rf/Ri
25
Active Filters (Band-Pass Filter)
+
i
o
(c)
Rf Ci Ri
Active filters (c) A bandpass filter attenuates both low and high frequencies.
iiff
if
i
o
CRjCRj
CRj
jV
jV
11
|G|
freq fcL = 1/2RiCi
Rf/Ri
0.707 Rf/Ri
fcH = 1/2RfCf
Cf
26
Frequency Response of op-amp and Amplifier
Open-Loop Gain
Compensation
Closed-Loop Gain
Loop Gain
Gain Bandwidth Product
Slew Rate
27
Input and Output Resistance
d
i
iai RA
i
vR )1(
+
Rd ii
Ro
RL CL
io Ad
d o
i
+
1
A
R
i
vR o
o
oao
Typical value of Rd = 2 to 20 MW Typical value of Ro = 40 W 28
Phase-Sensitive Demodulator
Used in many medical instruments for signal detection, averaging, and Noise rejection
29
The Ring Demodulator
vc 2vi
If vc is positive then D1 and D2 are forward-biased and vA = vB. So vo = vDB
If vc is negative then D3 and D4 are forward-biased and vA = vc. So vo = vDC
30