IPC-THAG
EUROPEAN SPACE TECHNOLOGY HARMONISATION ROADMAP MEETING
Industrial Policy Committee
Technology Harmonisation Advisory Group
MICROELECTRONICS: ASIC AND FPGA
Issue 4 rev. 2Draft
A. Fernandez-Leon, TEC-EDM
IPC-THAG
Slide 2 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Contents
1.Technology Overview
2.Mission Needs and Market Perspectives
3.Proposed Development Approach
a. Focus on deep-submicron (65nm and smaller) microchips
4.Closing Remarks
IPC-THAG
Slide 3 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Technology Overview
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Slide 4 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Technology Overview: Areas covered in “Microelectronics: ASIC & FPGA dossier”
Silicon Wafer ASIC foundry
FPGA Programming
Space specific design requirements (radiation hardening &
reliability techniques)
IC Design Methodology (from specs to prototype/ FM tests)
Evaluation and Qualification test houses (electrical, mechanical, thermal,
radiation, life time)
IC Design House
(ASIC , FPGA)
ASIC Assembly & Test House
PCB technology
Memories
IC power supply Space specific quality
test requirements (ESCC)
CAD tools
IP Cores
Rad Hard ASIC Libraries & Design Kits
or
Covered in this dossier
Covered in other dossiers
ESA Technology Tree domain :
TD:1 On-Board Data Systems TSD: C , TG: I and II
Also NOT COVERED Optoelectronics Sensors and actuators MEMS discrete components MMIC, power and RF
Packaging technology
ADC and
DACs
Standard ASICs
Proprietary ASICs
Programmed FPGAs
DSP
Micro processors
Micro controllers
IPC-THAG
Slide 5 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Technology Overview: Synergies among the three Data Systems Dossiers
FPGA evaluation
ASICs (digital and mixed-signal)
European FPGA
Microprocessors
Systems-on-Chips
Standard
ASICs
Micro- Controller Devices DSOBC IP cores
Generic IP Cores
IC develop. methods and tools
Rad Effects Mitigation in Ics
IC Test tools
DSP Devices OBDP IP Cores Special ASICs
OBC reference architectures
RIU/RTU C&C Data Comm’ Wireless For platforms
Data compression P/L support software
SpaceWire, SpaceFibre networks
Wireless For P/Ls
MICROELECTRONICS: ASIC & FPGA Dossier
Data Systems and On-Board Computers Dossier
On-Board Payload Data Processing Dossier
Mass mem COTS OBC & P/L computers
Note: text colors indicate leadership by DSOBC, ME, OBPDP, or joint
IPC-THAG
Slide 6 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
availability of European space ASIC and FPGA technology in general, at competitive prices
miniaturisation and speed/power optimization make advances in the performances and functional capabilities of our satellites (e.g.
DSM ASIC for next generation Telecom payloads)
maintain and increase competitiveness of European satellite equipment manufactures
minimize the dependency on export restrictions and overhead (e.g. US ITAR parts)
trend: manufacturing in Asia, with cheaper labour costs and national incentives for foreign capital investment facilitates a better and more sustainable business model
European strategic interest that all ASIC/FPGA capabilities (design houses,
manufacturing and test) remain secured and sustainable in Europe.
While in parallel there is a European strategy to work with Asian Fabs
MISSION NEEDS/MARKET PERSPECTIVES European strategic interest
IPC-THAG
Slide 7 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
steady increase in the use of FPGAs versus more or less constant use rate of new and existing catalogue ASICs and ASSPs.
IP Core-based SOC design is also experimenting an increase
FPGAs used in space is dominated by US one-time-programmable technologies
Rad hard reprogrammable FPGAs received a slow uptake by the space community.
Reasonable parts costs shall be a major requirement in the European FPGA development
The upcoming family of European BRAVE FPGAs offers potential for a much wider acceptance, as well as the new Microsemi FLASH-based reprogrammable parts.
MISSION NEEDS/MARKET PERSPECTIVES FPGA
IPC-THAG
Slide 8 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Reference for Prioritization
According to the implementation of the previous (2011) roadmap : 33 ESA activities are “funded” or “partially funded” for a budget of about 24M€.
* 37 additional ESA activities that were not part of the 2011 Roadmap,
amounted to ~ 24.5 M€. Total of 70 ESA activities approved since 2011 for a budget of 48.5 M€ So, the yearly reference (total budget of all relevant activities approved since the previous Roadmap divided by the number of years (6 years, as of December 2015):
Yearly reference budget = 8M€
IPC-THAG
Slide 9 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Aim A: Digital ASIC technologies European deep submicron technologies 65nm and 28nm or beyond, evaluation
of radiation effects in these technologies. Aim B: ASIC/FPGA Design methodology and IP Cores fault injection tools, HW-SW SoC co-design, various digital and A/MS new IP
Cores, tools to optimise design of systems combining FPGA and Microprocessors, multi-core multithreading , timing predictability, fast simulation with Virtual Platforms and ESL, etc.
Aim C: Analogue and mixed-signal ASICs, ADC/DAC multiple ADC and DAC ASSP developments and standard standalone devices;
A/MS design kits and ASIC platforms like IMEC-DARE, Atmel-ATMX150RHA, or IMST/XFAB
Aim D: FPGA new European reprogrammable BRAVE FPGA family (65nm, 28nm or beyond),
tools to optimise radiation behaviour reprogrammable FPGAs
ROADMAP Aims (1/2)
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Slide 10 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Aim E: Microprocessors, Standard and proprietary ASICs
Maintaining, improving, developing , evaluating or qualifying Microprocessors , “Standard ASICs” (or ASSPs) and other proprietary ASICs (with potential for reuse)
Aim F: ASIC/FPGA Evaluation , Qualification, packaging, memories
Aim G: Read-Out ASICs for Imagers and Radiation Sensors
new AIM in the 2016 dossier. activities for maintaining, improving, developing , evaluating or qualifying microelectronic technologies needed for imagers, radiation sensors, namely read-out ASICs.
ROADMAP Aims (2/2)
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Slide 11 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
ROADMAP Proposed development approach: Resource Distribution
IPC-THAG
Overview of 2016 Roadmap ASIC & FPGA activities 1- Standard ASICs & processors (DIGITAL and Mixed-Signal)
21 running activities
2 - ASIC technology 6 running activities 3 - IP Cores, FPGA, IC design and test tools & methodology 14 running activities
46 new activities being proposed in “Microelectronics: ASIC & FPGA” harmonization dossier 2016 (many in synch with “CTB/ECI5” roadmaps). There are also many ASIC/FPGA/IP Core/uC/DSP activities in OBPayloadDS and DSOBComputer dossiers
IPC-THAG
Slide 13 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
European DSM processes & libraries for space microchips: 65nm and below
Atmel Customer Interface / Design / packaging services
IMEC libraries
ST libraries
2000 2005 2010 2015 2020
350nm
180nm
150nm SOI
65 nm
180nm
350nm
65 nm
28 nm FDSOI
500nm
VT65 ASIC
DARE65 mixed-signal ASIC
HPDP C28SPACE ASIC
GR740 EM GR740 FM NG Microprocessor EM
BRAVE-M
(Atmel / Lfoundry Rousset fab)
ON Semi fab Belgium
UMC fab Taiwan
ST fab Crolles
ST fab Crolles
Atmel Rousset fab
UMC fab Taiwan
TSMC fab Taiwan
UMC fab Taiwan
Atmel Nantes fab
Xfab fab Malaysia
UMC fab Taiwan
IPC-THAG
Slide 14 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
recent examples of European DSM chips
brains processing the DATA inside our satellites
“VT65” Telecom payload processor 200 mm2
1752 pins TAS/ST/Atmel/E2V/CNES
“NGMP/GR740” General Purpose Microprocessor 70 mm2
625 pins Cobham Gaisler/ST/E2V/ESA
“BRAVE FPGA” General Purpose Reprogrammable 170 mm2
625 pins NanoXplore/ST/ESA/CNES
All manufactured with 65nm rad-hard microchip technology provided by STMicroelectronics & partners
2015 2016 2015
ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
IPC-THAG
Slide 15 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
European DSM processes & libraries for space microchips: 65nm and below
ASICs
Next Support Needed !
C65SPACE ESCC* Qualification (wire bonding and flip chip)
1.5M€
Development and evaluation of C28SPACE (28nm)
1M€
DARE65 Analogue IPs (GSTP+TRP)
3.5M€
On-going
Space Flip-Chip packaging 1.8M€
HPDP ASIC 480K€
DDR IP 900K€
IMEC development of mixed-signal DARE65
3M€
2016-2019
Accomplished
STMicroelectronics mature design kit/libraries (C65SPACE)
7M€ ESA & CNES
8 yrs
first users and products (VT65, NGMP, BRAVE-M)
* European Space Components Coordination, https://spacecomponents.org/
IPC-THAG
Slide 16 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
European DSM processes & libraries for space microchips: 65nm and below
Micro-processors
Next Support Needed !
GR740 Flight Model & ESCC Qualification
2M€
High Performance Space Microprocessor: GR740-HP (Eng. Model)
1.5M€
Qualification of new/complementary GR740 SW tools & Operating System
1M€
On-going
Finish GR740 validation
HW optimisation for performance, time-predictability
SW environment tools optimisation for performance, time-predictability, debugging
Accomplished
GR740 Engineering Model (4xLEON4 + peripherals) component manufactured end 2015 with ST C65SPACE
2.6M€
11 yrs
Software benchmarks, multi-thread, time-predictability
1.4M€ 5 yrs
IPC-THAG
Slide 17 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
European DSM processes & libraries for space microchips: 65nm and below
GR740 4xLEON4 Micro-processor
GR740 SEE tests June 2016
GR740 Evaluation boards
IPC-THAG
BRAVE NG-MEDIUM Bring Up
NG-MEDIUM bring up software environment
NG-MEDIUM first assembled samples in LGA 625 used for bring up
NG-MEDIUM bring up board
ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
IPC-THAG
Slide 19 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
CONCLUSIONS on European space DSM
- Deep Submicron (65nm and smaller) ASICs, FPGAs and Microprocessors enable higher performance, miniaturization and less power consumption than older microchip technologies
- First microchips have been manufactured: VT65, GR740, BRAVE-M…
- Urgent new investments needed to finish and qualify 1st products and tools, to develop next generations and more mixed-signal DSM ASIC capability
Accomplished & on-going (M€)
Next (M€)
ASIC 13.2 6.0 Microprocessors 4.0 4.5
FPGA 9.8 13.5 DSM Total 26.8 24.0
IPC-THAG
Slide 20 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Closing remarks on ASIC & FPGA Roadmaps
ASICs and FPGAs are key for all missions ME dossier has been updated to reflect inputs from industry and delegations,
and better coordination between dossiers New roadmap has been compiled and consolidated More FPGAs and fewer ASICs, as gate capacity and performance increases and
because differences in price (NREs and per part) and development time European space ASICs vendors with European rad-hard libraries and IP, some
manufacturing in Asia (fabless) , but Many silicon fabs still in Europe, strong in niche, specialized, mixed-signal huge dependence on US (ITAR) space FPGAs (all manufactured in Asia). Many European ASIC/FPGA design groups and test houses with space know-
how European supply chain fragmented and international ownership makes space
quality control difficult Technology changes call for updates and tailoring of old quality standards Space complex general use ICs difficult/expensive to develop and maintain,
market sustainable only by parallel commercial (non-space) high volumes, and institutional (Agencies and EC ) support
-> important to coordinate and harmonise efforts and priorities
IPC-THAG
Slide 21 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
ESA Microelectronics section activity: http://www.esa.int/TEC/Microelectronics
Technology harmonisation dossiers will be available here: http://www.esa.int/Our_Activities/Space_Engineering_Technology/About_strategy_and_harmonisation https://tec-polaris.esa.int/pls/adm/webloginext.login
More info
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Slide 22 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
BACK UP SLIDES
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Slide 23 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
Microprocessors: better performance thanks to DSM technology
500 nm
1250 nm
180 nm
65 nm
IPC-THAG
Slide 24 ESA UNCLASSIFIED – For Official Use | ADCSS 2016 | 18-10-20016 | Microelectronics roadmap | A. Fernandez Leon
FPGAs: better performance and functional capacity thanks to DSM technology
IPC-THAG
STM BCD6 350nm
Xfab CMOS 180nm
UMC CMOS 180nm
UMC CMOS 150nm SOI
IHP BiCMOS 250, 130nm
STM CMOS 65nm
STM BiCMOS 130nm
ON-Semi CMOS 350nm
Tower CMOS180nm
Austriamicrosystems CMOS 350nm
ISD(G)
IMSE(E)
Space ASIC Technology Observatory ( draft 2 – Jan 13th 2016)
RUAG (S,A)
ISD(G)
NanoXplore(F)
RamonChips (Israel)
RedCat(I)
Ideas (N)
IMSE(E)
ESA
CNES (F)
DLR (D)
Atmel(F)
ESA
CNES (F)
STM (F)
CNES (F)
Atmel(F)
Arquimea(E)
E2V(F) STM (F)
IMST(D)
IHP(D)
OHB-KT(D) SpaceASICs(G) Saphyrion(CH)
ESA STM (F)
Cobham Gaisler(S) Thales(F) Airbus(D)
CNM(E)
Arquimea(E)
AirbusDS(G) Thales(F) RUAG(S)
Thales(F)
Saphyrion(CH) Thales(I)
Cobham Gaisler(S)
SODERN(F) Colibri(CH)
IC-Sense(B) IMSE(E)
ESA
CNM(E)
Arquimea(E)
IMEC(B)
Xfab CMOS 350nm
IMEC(B)
ESA
AirbusDS(G) Thales(F) RUAG(S)
Atmel(F)
CMOSIS(B) Caeleste(B) EASICS(B) Alter (E) TESAT(D) SRON(NL) Thales (B) AirbusDS(E,UK) Cobham Gaisler(S)
Roskosmos(Ru)
DIGITAL
Thales(B)
ESA IMEC(B)
Sitael(I)
DLR (D)
IMST(D)
TESAT(D)
IDMOS(B)
CNES (F)
RedCat(I)
Thales(F)