8/2/2019 Thesis Presentation - Terence Zarb
1/27
Terence ZarbB.Sc. (Hons.) ICT in CCE
Supervisor: Dr. Ivan Grech
8/2/2019 Thesis Presentation - Terence Zarb
2/27
Design of various digital signal processing andcommunication blocks which form an integralpart of a typical L1-band C/A-code GPS receiver Using synthesisable VHDL code
Design of a GPS satellite signal modulation model
Noise performance analysis of the designedbaseband processor
2
8/2/2019 Thesis Presentation - Terence Zarb
3/27
The digital baseband modules are implementedon an FPGA
Benefits of an FPGA over the ASIC approach: Re-programmability
Increased flexibility in the implementation by updatingfunctionality of the system after manufacturing
Prototyping the implementation of system with minimumcosts
Low NRE costs
3
8/2/2019 Thesis Presentation - Terence Zarb
4/27
GPS main segments
4
8/2/2019 Thesis Presentation - Terence Zarb
5/27
GPS uses spread-spectrum communication(CDMA) for communication between space anduser segments
Satellites transmit on the same frequency two separate RF carriers are used (L1 and L2)
Each satellite is assigned a unique PRN code three different codes: C/A-code, P-code, Y-code
Each satellites navigation message is modulatedby the satellites PRN code and the resultingdigital signal BPSK modulates the carrier wave
5
8/2/2019 Thesis Presentation - Terence Zarb
6/27
A GPS receiver is made up of 3 main parts: Analogue front-end chip
Digital baseband processor
Dedicated CPU
6
8/2/2019 Thesis Presentation - Terence Zarb
7/27
The baseband processor is responsible fordemodulation of navigation data coming fromdifferent satellites Demodulation involves acquisition and tracking
Acquisition: Generate local replica of incoming signal:
carrier replica + C/A-code replica
Synchronise the local and incoming signals
determine the code phase and carrier Doppler frequency
Down convert the incoming signal to baseband andcross-correlate the result with the local C/A-codes
7
8/2/2019 Thesis Presentation - Terence Zarb
8/27
Tracking phase starts after a satellite signal isacquired Responsible for maintaining lock between local and
incoming signals
Carrier tracking loop using a Phase-Locked Loop (PLL)
Code tracking loop using a Delay-Locked Loop (DLL)
8
Baseband Processing
8/2/2019 Thesis Presentation - Terence Zarb
9/27
Assumptions: Perfect carrier phase recovery
GPS signals are not affected by Doppler Effect
The baseband processor hardware modules aredesigned using synthesisable VHDL code
The GPS satellite signal modulation model isdesigned using MATLAB Simulink
9
System Design
8/2/2019 Thesis Presentation - Terence Zarb
10/27
Carrier Generator: Front-end chip used is the GP2015 which down converts
the L1 frequency to 4.309 MHz IF
IF bandwidth = 2.046 MHz; fS = 5.102 MHz
Aliasing occurs and the IF frequency is further down
converted to 793 kHz Local carrier = 2.4 sin (2(793k)t)
10
Carrier Quantisation
8/2/2019 Thesis Presentation - Terence Zarb
11/2711
Carrier Samples:
8/2/2019 Thesis Presentation - Terence Zarb
12/27
Baseband Mixer: Mixes incoming 2-bit digitised IF signal with local carrier
Each baseband sample requires 3-bit to be represented
12
2-bit combinations of
digitised IF
3-bit combinations ofbaseband mixed signal
8/2/2019 Thesis Presentation - Terence Zarb
13/27
C/A-Code Generator: Generates the C/A-codes of all 24 satellites in parallel at
a rate of 1.023 MHz
13
8/2/2019 Thesis Presentation - Terence Zarb
14/27
Four-channel Parallel Correlator: Correlates the baseband signal with the local C/A-codes
of four satellites simultaneously
Corr() =b(n)c(n ); 01022
14
Baseband
Signal
1023-bit shift register
1.023 MHz
clock
D QD Q D Q D Q D QC/A-Code
Generator
S0 S1 S2 S3 S1022
One-Channel Parallel
Correlator
8/2/2019 Thesis Presentation - Terence Zarb
15/27
Comparator: Selects four satellites for data demodulation and
determines their correct code phase delays
Controls which four satellites are processedsimultaneously by the correlator
Accumulation interval = 2 ms
Navigation Data Demodulator:
15
Determination of
navigation data bits
8/2/2019 Thesis Presentation - Terence Zarb
16/27
Satellite Signal Modulation Model
16
8/2/2019 Thesis Presentation - Terence Zarb
17/27
The correct functionality of each module wasverified through various simulations VHDL modules were tested using ModelSim
Satellite signal modulation model was tested usingMATLAB Simulink Simulation tool
Evaluation setup: Bottom-up approach
Tests for one satellite transmission
Tests for multiple satellite transmissions
Analyse noise performance of baseband processor
17
8/2/2019 Thesis Presentation - Terence Zarb
18/27
BPSK IF Signal generation for one satellite:
18
8/2/2019 Thesis Presentation - Terence Zarb
19/27
Correlation results for one satellite (SV 0)transmission:
19
-1000
0
1000
2000
3000
4000
5000
138
75
112
149
186
223
260
297
334
371
408
445
482
519
556
593
630
667
704
741
778
815
852
889
926
963
1000
CorrelationValue
Code Phase Delay (in Chips)
Auto-Correlation of SV 0 C/A-Code
8/2/2019 Thesis Presentation - Terence Zarb
20/27
Correlation results for one satellite (SV 0)transmission:
20
-1000
0
1000
2000
3000
4000
5000
137
73
109
145
181
217
253
289
325
361
397
433
469
505
541
577
613
649
685
721
757
793
829
865
901
937
973
1009
CorrelationValue
Code Phase Delay (in Chips)
Cross-Correlation for the Baseband Samplesand SV 2 C/A-Code
8/2/2019 Thesis Presentation - Terence Zarb
21/27
Results for multiple satellite transmissions:
21
8/2/2019 Thesis Presentation - Terence Zarb
22/27
Noise Performance:
22
8/2/2019 Thesis Presentation - Terence Zarb
23/27
Noise Performance:
23
8/2/2019 Thesis Presentation - Terence Zarb
24/27
FPGA used: Xilinx Spartan-3E X3S500E Modules are synthesised using Xilinx ISE v. 11.1
24
Module Inferred HardwareBaseband Mixerand CarrierGenerator
1 13-bit up counter 1 13-bitComparator
51022 bits LUT
C/A-codeGenerator5 registers(21 D-type flip-flops)
1 2-input XORgate1 6-input XORgate
Correlator 4,093adders/subtractors
8,188comparators
4,105 registers(61,403 D-typeflip-flops)
Comparator 8 adders /subtractors 62comparators
1,062 registers(14,759 D-typeflip-flops)
1 10-bitup counter
5multiplexors
Navigation DataDemodulator1 6-bit register(6 flip-flops)
8/2/2019 Thesis Presentation - Terence Zarb
25/27
Correlation between incoming and local codes isreduced when: Number of parallel transmissions is increased
SNR is reduced
Minimum SNR value that processor can tolerate is-10 dB when gain control is adopted
The front-end AGC is crucial in the performanceof the baseband processor
If no gain control is adopted, minimum SNR thatthe receiver can tolerate is greater than -10 dB
25
8/2/2019 Thesis Presentation - Terence Zarb
26/27
Carrier Synchronisation Doppler Shift Compensation
In-phase and quadrature components of the localreplica to preserve phase information
Clock signals generation
Additional functionalities: Low-power modes
Re-acquisition techniques
Interfacing the FPGA-based processor with theanalogue front-end module
26
8/2/2019 Thesis Presentation - Terence Zarb
27/27
27