LATHA MATHAVAN ENGINEERING COLLGEG
LATHA MATHAVAN ENGINEERING COLLEGEAlagarkovil, Madurai - 625301
Department of ECE
EC 6601 – VLSI DESIGN
TWO MARK WITH ANSWERS&
BIG QUESTIONS KEY POINTS
S.JANARTHANAN AP/ECE
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2 MARK QUESTIONS & ANSWERS1. What are four generations of Integration Circuits?
SSI (Small Scale Integration) MSI (Medium Scale Integration) LSI (Large Scale Integration) VLSI (Very Large Scale Integration)
2. Give the advantages of IC? Size is less High Speed Less Power Dissipation
3. Give the variety of Integrated Circuits? More Specialized Circuits Application Specific Integrated Circuits(ASICs) Systems-On-Chips
4. Give the basic process for IC fabrication
Silicon wafer Preparation Epitaxial Growth Oxidation Photolithography Diffusion Ion Implantation Isolation technique Metallization Assembly processing & Packaging
5. What are the various Silicon wafer Preparation? Crystal growth & doping Ingot trimming & grinding Ingot slicing Wafer polishing & etching Wafer cleaning.
6.Different types of oxidation? Dry & Wet Oxidation
7.What is the transistors CMOS technology provides? n-type transistors & p-type transistors.
8.What are the different layers in MOS transistors?
Drain , Source & Gate
9.What is Enhancement mode transistor?The device that is normally cut-off with zero gate bias.
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10. What is Depletion mode Device?The Device that conduct with zero gate bias.
11.When the channel is said to be pinched –off?If a large Vds is applied this voltage with deplete the Inversion layer
.This Voltage effectively pinches off the channel near the drain.
12.Give the different types of CMOS process? p-well process n-well process Silicon-On-Insulator Process Twin- tub Process
13.What are the steps involved in twin-tub process? Tub Formation Thin-oxide Construction Source & Drain Implantation Contact cut definition Metallization.
14.What are the advantages of Silicon-on-Insulator process? No Latch-up Due to absence of bulks transistor structures are denser than bulk
silicon.
15.What is BiCMOS Technology?It is the combination of Bipolar technology & CMOS technology.
16.What are the basic processing steps involved in BiCMOS process? Additional masks defining P base region N Collector area Buried Sub collector (SCCD) Processing steps in CMOS process
17. What are the advantages of CMOS process? Low power Dissipation
High Packing density Bi directional capability
18. What are the advantages of CMOS process? Low Input Impedance Low delay Sensitivity to load.
19. What is the fundamental goal in Device modeling?To obtain the functional relationship among the terminal
electrical variables of the device that is to be modeled.
20. Define Short Channel devices?
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Transistors with Channel length less than 3- 5 microns are termed as Short channel devices. With short channel devices the ratio between the lateral & vertical dimensions are reduced.
21. What is Pull down device?A device connected so as to pull the output voltage to the lower
supply voltage usually 0V is called pull down device.
22. What is Pull up device?A device connected so as to pull the output voltage to the upper
supply voltage usually VDD is called pull up device.
23. Why NMOS technology is preferred more than PMOS technology?N- Channel transistors has greater switching speed when compared tp
PMOS transistors.
24.What is the different operating regions foe an MOS transistor?
Cutoff region Non- Saturated Region Saturated Region
25.What are the different MOS layers?
n-diffusion p-diffusion Polysilicon Metal
26.What is Stick Diagram?It is used to convey information through the use of color code. Also it is
the cartoon of a chip layout.
27.What are the uses of Stick diagram? It can be drawn much easier and faster than a complex layout. These are especially important tools for layout built from large
cells.
28.Give the various color coding used in stick diagram?
Green – n-diffusion Red- polysilicon Blue –metal Yellow- implant Black-contact areas.
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29. Compare between CMOS and bipolar technologies.
CMOS Technology Bipolar technologyLow static power dissipation High power dissipation
High input impedance (low driveLow input impedance (high drive
current) current)Scalable threshold voltage
Low voltage swing logicHigh noise marginHigh packing density Low packing density
High delay sensitivity to load (fan- Low delay sensitivity to load
out limitations)High output drive currentLow output drive current
Low gm (gm Vin) High gm (gm eVin)High ft at low current
Bidirectional capability Essentially unidirectional
A near ideal switching device
30. Define Threshold voltage in CMOS?The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to Source current, IDS effectively drops to zero.
31. What is Body effect?The threshold voltage VT is not a constant w. r. to the voltage
difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.
32. What is Channel-length modulation?The current between drain and source terminals is constant and
independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.
33. What is Latch – up?Latch up is a condition in which the parasitic components give rise
to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.
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34. Give the basic inverter circuit.
35. Give the CMOS inverter DC transfer characteristics and operating regions
36. Define Rise timeRise time, r is the time taken for a waveform to rise from 10% to
90% of its steady-state value.
37. Define Fall timeFall time, f is the time taken for a waveform to fall from 90% to
10% of its steady-state value.
38. Define Delay timeDelay time, d is the time difference between input transition
(50%) and the 50% output level. This is the time taken for a logic transition to pass from input to output.
39. What are two components of Power dissipation?There are two components that establish the amount of power dissipated in a CMOS circuit. These are:
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i) Static dissipation due to leakage current or other current drawn continuously from the power supply.
ii) Dynamic dissipation due to- Switching transient current- Charging and discharging of load capacitances.
40.Give some of the important CAD tools.Some of the important CAD tools are:
i) Layout editorsii) Design Rule checkers (DRC)iii) Circuit extraction
41. What is Verilog?Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C programming language. It can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level.
42.What are the various modeling used in Verilog?1. Gate-level modeling2. Data-flow modeling3. Switch-level modeling4. Behavioral modeling
43.What is the structural gate-level modeling?Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.
44. What is Switch-level modeling?Verilog allows switch-level modeling that is based on the behavior of MOSFETs. Digital circuits at the MOS-transistor level are described using the MOSFET switches.
45. What are identifiers?Identifiers are names of modules, variables and other objects that we can reference in the design. Identifiers consists of upper and lower case letters, digits 0 through 9, the underscore character(_) and the dollar sign($). It must be a single group of characters.Examples: A014, a ,b, in_o, s_out
46. What are the value sets in Verilog?Verilog supports four levels for the values needed to describe hardware referred to as value sets.
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Value levels
Condition in hardware circuits
0 Logic zero, false condition1 Logic one, true conditionX Unknown logic value
ZHigh impedance, floating state
47. What are the types of gate arrays in ASIC?1)Channeled gate arrays2)Channel less gate arrays3)Structured gate arrays
48. Give the classifications of timing control? Methods of timing control:1. Delay-based timing control2. Event-based timing control3. Level-sensitive timing control
Types of delay-based timing control:1. Regular delay control2. Intra-assignment delay control3. Zero delay control
Types of event-based timing control:1. Regular event control2. Named event control3. Event OR control4. Level-sensitive timing control
49 Give the different arithmetic operators?
Operator symbol Operation performedNumber of operands
* Multiply Two/ Divide Two+ Add Two- Subtract Two% Modulus Two** Power (exponent) Two
50. Give the different bitwise operators.
Operator symbol Operation performed
Number of operands
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~ Bitwise negation One& Bitwise and Two| Bitwise or Two^ Bitwise xor Two^~ or ~^ Bitwise xnor Two~& Bitwise nand Two~| Bitwise nor Two
51. What are gate primitives?Verilog supports basic logic gates as predefined primitives. Primitive logic function keyword provides the basics for structural modeling at gate level. These primitives are instantiated like modules except that they are predefined in verilog and do not need a module definition. The important operations are and, nand, or, xor, xnor, and buf(non-inverting drive buffer).
52. Give the two blocks in behavioral modeling.
1. An initial blockexecutes once in the simulation and is used to set upinitial conditions and step-by-step data flow
2. An always blockexecutes in a loop and repeats during the simulation.
53. What are the types of conditional statements?1. No else statement
Syntax : if ( [expression] ) true – statement;2. One else statement
Syntax : if ( [expression] ) true –
statement; else false-statement;
3. Nested if-else-ifSyntax : if ( [expression1] ) true statement
1; else if ( [expression2] ) true-statement 2; else if ( [expression3] ) true-statement 3; else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is executed. If it is false (zero) or ambiguous (x), the false-statement is executed.
54. Name the types of ports in VerilogTypes of port Keyword
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Input port InputOutput port OutputBidirectional port inout
55. What are the types of procedural assignments?
1. Blocking assignment2. Non-blocking assignment
56. Give the different symbols for transmission gate.
57. Give the different types of ASIC. 1. Full custom ASICs2. Semi-custom ASICs
* standard cell based ASICs* gate-array based ASICs
3. Programmable ASICs
* Programmable Logic Device (PLD)* Field Programmable Gate Array (FPGA).
58. What is the full custom ASIC design?In a full custom ASIC, an engineer designs some or all of the logic cells, circuits or layout specifically for one ASIC. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design.
59. What is the standard cell-based ASIC design?A cell-based ASIC (CBIC) USES PREDESIGNED LOGIC CELLS KNOWN AS STANDARD CELL. The standard cell areas also called fle4xible blocks in a CBIC are built of rows of standard cells. The ASIC designer defines only the placement of standard cells and the interconnect in a CBIC. All the mask layers of a CBIC are customized and are unique to a particular customer.
60. What is a FPGA?A field programmable gate array (FPGA) is a programmable logic device that supports implementation of relatively large logic circuits. FPGAs can be used to implement a logic circuit with more than 20,000 gates whereas a CPLD can implement circuits of upto about 20,000 equivalent gates.
61. Channeled gate array?1. Only the interconnect is customized2. The interconnect uses predefined spaces between rows of base cells.
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3. Routing is done using the spaces4. Logic density is less62. channel less gate array?1. Only the top few mask layers customized.2. No predefined areas are set aside for routi between cells.3. Routing is done using the area of transist unused. 4. Logic density is higher.
63. What are the different methods of programming of PALs?The programming of PALs is done in three main ways:
Fusible linksUV – erasable EPROM
EEPROM (E2PROM) – Electrically Erasable Programmable ROM
64.What is an antifuse?An antifuse is normally high resistance (>100M ). On application of appropriate programming voltages, the antifuse is changed permanently to a low-resistance structure (200-500 ).
65. What are the different levels of design abstraction at physical design? Architectural or functional levelRegister Transfer-
level (RTL) Logic level Circuit level66.What are macros?
The logic cells in a gate-array library are often called macros.
67. What are Programmable Interconnects ?In a PAL, the device is programmed by changing the characteristics
if the switching element. An alternative would be to program the routing.
68. Give the steps inASIC design flow.a. Design entryb. Logic synthesisSystem partitioningc. Prelayout simulation.d. Floorplanninge. Placementf. Routingg. Extraction1. Postlayout simulation
69. Give the XILINX Configurable Logic Block .
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70. Give the XILINX FPGA architecture
71.Mention the levels at which testing of a chip can be done?a)At the wafer levelb)At the packaged-chip levelc)At the board leveld)At the system levele)In the field
72.What are the categories of testing?a) Functionality testsb) Manufacturing tests
73. Write notes on functionality tests?Functionality tests verify that the chip performs its intended
function. These tests assert that all the gates in the chip, acting in concert, achieve a desired function. These tests are usually used early in the design cycle to verify the functionality of the circuit.
74. Write notes on manufacturing tests?Manufacturing tests verify that every gate and register in the chip
functions correctly. These tests are used after the chip is manufactured to verify that the silicon is intact.
75. Mention the defects that occur in a chip?a)layer-to-layer shortsb)discontinuous wiresc)thin-oxide shorts to substrate or well
76.Give some circuit maladies to overcome the defects?a. nodes shorted to power or ground
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b. nodes shorted to each otherc. inputs floating/outputs disconnected
77.What are the tests for I/O integrity?a. I/O level testb. Speed testc. IDD test78. What is meant by fault models?
Fault model is a model for how faults occur and their impact on circuits.
79. Give some examples of fault models?a. Stuck-At Faultsb. Short-Circuit and Open-Circuit Faults
80. What is stuck – at fault?With this model, a faulty gate input is modeled as a “stuck at zero” or
“stuck at one”. These faults most frequently occur due to thin-oxide shorts or metal-to-metal shorts.
81. What is meant by observability?The observability of a particular internal circuit node is the
degree to which one can observe that node at the outputs of an integrated circuit.
82. What is meant by controllability?The controllability of an internal circuit node within a chip is a
measure of the ease of setting the node to a 1 or 0 state.
83. What is known as percentage-fault coverage?The total number of nodes that, when set to 1 or 0, do result in the
detection of the fault, divided by the total number of nodes in the circuit, is called the percentage-fault coverage.
84. What is fault grading?Fault grading consists of two steps. First, the node to be faulted is
selected. A simulation is run with no faults inserted, and the results of this simulation are saved. Each node or line to be faulted is set to 0 and then 1 and the test vector set is applied. If and when a discrepancy is detected between the faulted circuit response and the good circuit response, the fault is said to be detected and the simulation is stopped.
85.Mention the ideas to increase the speed of fault simulation?a. parallel simulationb. concurrent simulation
86.What is fault sampling?An approach to fault analysis is known as fault sampling. This is
used in circuits where it is impossible to fault every node in the circuit. Nodes are randomly selected and faulted. The resulting fault detection
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rate may be statistically inferred from the number of faults that are detected in the fault set and the size of the set. The randomly selected faults are unbiased. It will determine whether the fault coverage exceeds a desired level.
87.What are the approaches in design for testability?a. ad hoc testingb. scan-based approachesc. self-test and built-in testing
88.Mention the common techniques involved in ad hoc testing?a. partitioning large sequential circuitsb. adding test pointsc. adding multiplexersd. providing for easy state reset
89.What are the scan-based test techniques?a)Level sensitive scan designb)Serial scanc)Partial serial scand)Parallel scan
90.What are the two tenets in LSSD?The circuit is level-sensitive. Each register may be converted
to a serial shift register.
91.What are the self-test techniques?a. Signature analysis and BILBOb. Memory self-testc. Iterative logic array testing
92.What is known as BILBO?Signature analysis can be merged with the scan technique to
create a structure known as BILBO- for Built In Logic Block Observation.93.What is known as IDDQ testing?
A popular method of testing for bridging faults is called IDDQ or current-supply monitoring. This relies on the fact that when a complementary CMOS logic gate is not switching, it draws no DC current. When a bridging fault occurs, for some combination of input conditions a measurable DC IDD will flow.
94.What are the applications of chip level test techniques?a. Regular logic arraysb. Memoriesc. Random logic
95.What is boundary scan?The increasing complexity of boards and the movement to technologies
like multichip modules and surface-mount technologies resulted in system
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designers agreeing on a unified scan-based methodology for testing chips at the board. This is called boundary scan.
96.What is the test access port?The Test Access Port (TAP) is a definition of the interface that needs to
be included in an IC to make it capable of being included in boundary-scan architecture. The port has four or five single bit connections, as follows:TCK (The Test Clock Input) TMS (The Test Mode Select) TDI (The Test Data Input)TDO(The Test Data Output)
It also has an optional signal TRST*(The Test Reset Signal)
97.What are the contents of the test architecture?The test architecture consists of:The TAP interface pinsA set of test-data registers An instruction registerA TAP controller
98.What is the TAP controller?The TAP controller is a 16-state FSM that proceeds from state to state
based on the TCK and TMS signals. It provides signals that control the test data registers, and the instruction register. These include serial-shift clocks and update clocks.
99. What is known as test data register?The test-data registers are used to set the inputs of modules
to be tested, and to collect the results of running tests.
100. What is known as boundary scan register?The boundary scan register is a special case of a data
register. It allows circuit-board interconnections to be tested, external components tested, and the state of chip digital I/Os to be sampled.
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BIG QUESTIONS & ANSWERS
1. Derive the CMOS inverter DC characteristics and obtain the relationship for output voltage at different region in the transfer characteristics.
Explanation (2)Diagram (2)CMOS inverter (2)DC characteristics (5)Transfer characteristics (5)
2. Explain with neat diagrams the various CMOS fabrication technology P-well process (4)N-well process (4) Silicon-On-I
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nsulator Process (4) Twin- tub Process (4)
3. Explain the latch up prevention techniques.
Definition (2)Explanation (2)Diagram (2)4. Explain the operation of PMOS Enhancement transistor
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Explanation (2)Diagram (2) Operation (4)
5. Explain the threshold voltage equation
Definition (2)Explanation (2)Derivation (4)
6. Explain the silicon semiconductor fabrication process. Silicon wafer Preparation (2)Epitaxia
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l Growth (2) Oxidation (2) Photolithography (2) Diffusi
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on(2)Ion Implantation (2) Isolation technique (2) Metal
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lization (1)Assembly processing & Packaging (1)
7. Explain various CAD tool sets.Layout editors (4)Design Rule checkers (DRC) (4)Circuit extraction (4)
8. Explain the operation of NMOS Enhancement transistor. Explanation (2)Diagram (2) Operation (4)
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9. Explain the Transmission gate and the tristate inverter briefly. Explanation (2)Diagram (2) Operation (4)
10.Explain about the various non ideal conditions in MOS device model. Explanation (2)Diagram (2) Opera
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tion (4)
11. Explain the design hierarchies.Explanation (2)Diagram (2)Concept (2)
12.Explain the concept involved in Timing control in VERILOG. Explanation (2)Diagram (2)Delay-based timing control (4) Even
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t-based timing control(4) Level-sensitive timing contro
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l(4)
13.Explain with neat diagrams the Multiplexer and latches using transmission Gate.
Explanation (2) Diagram (2) Multiplexer (4) l
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atches(4)
14.Explain the concept of gate delay in VERILOG with example Explanation (2)Diagram (2) Concept (2)
15.Explain the concept of MOSFET as switches and also bring the various logic
Gates using the switching concept. Expla
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nation (2)Diagram (2)Gate Concepts (4)
16.Explain the concept involved in structural gate level modeling and also give the description for half adder and Full adder.
Explanation (2)Diagram (2)Gate Concepts (6)Half adder (3)Full adder (3)
17.What is ASIC? Explain the types of ASIC. Definition (2)Types (2)Full custom ASICs (4) S
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emi-custom ASICs(4) Programmable ASICs(4)
18.Explain the VLSI design flow with a neat diagram Explanation (2)Flow
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Diagram (2) Concepts (4)
19.Explain the concept of MOSFET as switches Explanation (2)Diagram (2) Conc
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epts (4)
20.Explain the ASIC design flow with a neat diagramh. Design entry(2)i. Logic synthesis System
partitioning(2)j. Prelayout simulation. (2)k. Floor planning(2)l. Placement(2)m. Routing(2)n. Extraction (2)2. Post layout simulation(2)
21.a) Explain fault models.
Stuck-At FaultsDefinition (2)Diagram (2)
Short-circuit and Open-circuit faults
Definition (2)Diagram (2)
b)Explain ATPG. Definition (
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2) Truth tables (2)Five valued logic (2) Testability measures (2)
22.Briefly explaina)Fault grading
& fault simulation Fault grading (2)Fault simulation (2)
b)Delay fault testing Dia
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gram (2) Description (2)
c)Statistical fault analysis Definition (1) Statistics (3)
d)Fault sampling (4)
23.Explain scan-based test techniques. Level sensitive scan design (4) Serial scan (4)Partial serial
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scan (4) Parallel scan (4)
24.Explain Ad-Hoc testing and chip level test techniques. Ad-Hoc testing
Parallel-load feature (2) Test signal block (2) Use of the bus (2)Use of
multiplexer (2) Chip level test techniques
Definition (2)Regular logic arrays (2) Memories (2)Random logic (2)
25.Explain self-test techniques and IDDQ testing. Signature analysis and BILBO (6) Memory-self test (4)Iterative logic array testing (3) IDDQ testing (3)
26. Explain system-level test techniques. Boundary scan – definition (2) The Test Access Port (2)The Test Architecture (2)The TAP Controller (3)
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The Instruction Register (2) Test-Data Registers (2)Boundary Scan Registers (3)
LATHA MATHAVAN ENGINEERING COLLEGE
MADURAIB.E. ELECTRONICS AND
COMMUNICATION ENGINEERING
R 2013 VI SEMESTER
EC6601 VLSI DESIGNUNIVERSITY POSSIBLE TWO MARK AND BIG QUESTION
UNIT – IPart – A
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1) list the various issues in
technology CAD (May / June
2013)
2) define the lambda layout rules
(May / June 2013)
3) What are non ideal I-V effects
(May / June 2014)
4) Discuss any two layout design
rules (May / June 2014)
5) Determine whether an NMOS
transistor with a threshold
voltage of 0.7V is operating in
the saturation region if VGS =
2V and VDS = 3v (Nov / Dec
2011)
6) Write down the equation for
describing the channel length
modulation effect in NMOS
transistor (Nov / Dec 2011)
7) Compare CMOS and BICMOS
technology (Nov / Dec 2013)
8) Draw the DC transfer
characteristics of CMOS
inverter (Nov / Dec 2013)
9) Why the tunneling current is
higher for NMOS transistor
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than PMOS transistor with
silica gate (Nov / Dec 2012)
10) What is the objective of
layout rules (Nov / Dec 2012)
PART - B
1) Explain in details about the
ideal I-V characteristics and
non ideal I-V characteristics of
NMOS and PMOS devices.
(16) (May / June 2013)
2) Explain in details about the
body effect and its effect in
NMOS and PMOS devices(8)
(May / June 2013)
3) Derive the expression for DC
transfer characteristic of
CMOS inverter (8) (May /
June 2013)
4) Discuss the CV characteristics
and DC transfer characteristics
of the CMOS (16) (May / June
2014)
5) Briefly discuss about the
CMOS process enhancement
and layout design rules (16)
(May / June 2014)
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6) Draw and explain the dc and
transfer characteristics of a
CMOS inverter with necessary
for the different regions of
operation (8) (Nov / Dec
2011)
7) Explain the gate , source /
drain formation and isolation
steps of CMOS fabrication
process with neat diagram (8)
(Nov / Dec 2011)
8) Give a brief notes on the
different process techniques to
enhance the performance(Nov
/ Dec 2011)
9) Explain the electrical
properties of MOS transistor in
details (16) (Nov / Dec 2013)
10) Derive an expression for
vin of a CMOS inverter to
achieve the condition vin- vout
what should be the relation for
Bn = Bp(16) (Nov / Dec
2013)
11) Explain the different
steps involved in n- well
CMOS fabrication process
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with neat diagrams (10)
(Nov / Dec 2012)
12) Draw the CMOS
inverter and discuss its DC
characteristics. Write the
conditions for the different
regions of operation (6) (Nov /
Dec 2012)
13) Explain the principle of
SOI technology with neat
diagrams discuss its
advantages and disadvantages
(8) (Nov / Dec 2012)
UNIT – II
Part – A
1. what is meant by design
margin (May / June 2013)
2. how do you define the term
device modeling (May / June
2013)
3. Define transistor sizing
problem (May / June 2014)
4. What do you mean by design
margin (May / June 2014)
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5. Write the expression for
logical effort and parasitic
delay of n input NOR gate
(Nov / Dec 2011)
6. Why does interconnect
increase the circuits delay(Nov
/ Dec 2011)
7. Define power dissipation (Nov
/ Dec 2013)
8. Define scaling mention the
types of scaling (Nov / Dec
2013)
9. Give the effect of supply
voltage and temperature
variation on the CMOS system
performance
(Nov / Dec 2012)
10.What are the factors that cause
static power dissipation in
CMOS circuits (Nov / Dec
2012)
PART - B
1) Explain in details about the
scaling concept and reliability
concept (8) (May / June 2013)
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2) Describe in details about the
transistor sizing for the
performance in combinational
networks (8) (May / June
2013)
3) Discuss in details about the
resistive and capacitive delay
estimation of a CMOS inverter
circuit(16) (May / June 2013)
4) Explain the Device models and
device characterizations (10)
(May / June 2014)
5) Explain the Power dissipation
in CMOS circuits (6) (May /
June 2014)
6) Describe the simulation of
circuit interconnects (8) (May /
June 2014)
7) Write about SPICE based
circuit simulation (8) (May /
June 2014)
8) Explain the static and dynamic
power dissipation in COMS
circuit with necessary diagram
and expressions (10) (Nov /
Dec 2011)
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9) Discuss the principle of
constant field scaling and also
write its effect on device
characteristics (6) (Nov / Dec
2011)
10) Explain the different
reliability problems related to
the design of reliable CMOS
chips (8) (Nov / Dec 2011)
11) Give a brief account on
design margin (8) (Nov / Dec
2011)
12) Derive an expression for
the rise time , fall time and
propagation delay of a CMOS
inverter (16) (Nov / Dec 2013)
13) Explain the various
ways to minimize the static
and dynamic power dissipation
(16) (Nov / Dec 2013)
14) Explain the different
factors that’s affects the
reliability of CMOS chips (8)
(Nov / Dec 2012)
15) Discuss the principle of
constant field and lateral
scaling. write the effects of the
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above scaling methods on the
device character tics (8) (Nov
/ Dec 2012)
16) Discuss the
mathematical equations that
can be used to model the drain
current and diffusion
capacitance of MOS transistor
(8) (Nov / Dec 2012)
17) Give a brief notes on
logical effort and transistor
sizing (8) (Nov / Dec 2012)
UNIT – III
Part – A
1. list the various power in
CMOS Circuits (May / June
2013)
2. enumerate the features of
synchronizers (May / June
2013)
3. What are synchronizers(May /
June 2014)
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4. State any two criteria follow
power logic design (May /
June 2014)
5. Draw a pseudo NMOS inverter
(Nov / Dec 2011)
6. What are the advantages of
differential flip-flops(Nov /
Dec 2011)
7. Implement a 2:1 multiplexer
using pass transistor (Nov /
Dec 2013)
8. Design a 1 bit dynamic register
using pass transistor (Nov /
Dec 2013)
9. State the reasons for the speed
advantages of CVSL family
(Nov / Dec 2012)
10.Mention the qualities of an
ideal sequencing method (Nov
/ Dec 2012)
Part - B
1) Explain in details about the
pipeline concepts used in
sequential circuits(16) (May /
June 2013)
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2) Discuss the design techniques
to reduce switching activity in
a static and dynamic CMOS
circuits(16) (May / June 2013)
3) Explain the methodology of
sequential circuit design of
latches and flip-flops (16)
(May / June 2014)
4) Briefly discuss about the
classification of circuit
families and comparison of the
circuit families (16) (May /
June 2014)
5) Describe the basic principle of
operation of dynamic domino
and NP domino logic with neat
diagram (12) (Nov / Dec
2011)
6) Write the basic principle of
low power logic design (4)
(Nov / Dec 2011)
7) Compare the sequencing in
traditional domino and skew
tolerant domino circuits with
neat diagrams (8) (Nov / Dec
2011)
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8) Explain the problem of
metastability with neat
diagrams and expressions (8)
(Nov / Dec 2011)
9) Implement y= (A+B)(C+D)
using the standard CMOS
logic (8) (Nov / Dec 2013)
10) Implement NAND gate
using pseudo NMOS logic (8)
(Nov / Dec 2013)
11) Implement D-flip-flop
using transmission gate (8)
(Nov / Dec 2013)
12) Implement a 2 –bit non
inverting dynamic shift
register using pass transistor
logic (8) (Nov / Dec 2013)
13) Describe the different
methods of reducing static and
dynamic power dissipation in
CMOS circuits (8) (Nov / Dec
2012)
14) Explain the domino and
dual rail domino logic families
with neat diagram (8) (Nov /
Dec 2012)
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15) Draw and explain the
operation of conventional
CMOS, pulsed and resettable
latches (8) (Nov / Dec 2012)
16) Write a brief note on
sequencing dynamic circuits
(8) (Nov / Dec 2012)
UNIT – IV
Part – A
1. list the basic types of CMOS
testing (May / June 2013)
2. What is meant by Logic
verification (May / June 2013)
3. What is the need for
testing(May / June 2014)
4. What do you mean by text
fixtures (May / June 2014)
5. State the objective of
functional test (Nov / Dec
2011)
6. What are the test fixtures
required to test a chip(Nov /
Dec 2011)
7. What is the need for testing
(Nov / Dec 2013)
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8. What is the principle behind
logic verification (Nov / Dec
2013)
9. Distinguish testers and test
fixtures (Nov / Dec 2012)
10.What are the stages at which a
chip can be tested(Nov / Dec
2012)
Part – B
1) Explain the design for
testability DFT concepts(16)
(May / June 2013)
2) Explain the Silicon debug
principles (8) (May / June
2013)
3) Explain the Boundary scan
technique (8) (May / June
2013)
4) Discuss the need foe testing
and explain about the silicon
debugging principles (16)
(May / June 2014)
5) Explain the method of
boundary scan test in detail
(16) (May / June 2014)
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6) Explain the manufacturing test
principles in details (16) (Nov
/ Dec 2011)
7) Describe the ADHOC testing
and scan based approaches to
design for testability in details
(16) (Nov / Dec 2011)
8) Describe in detail the various
manufacturing test in CMOS
testing (16) (Nov / Dec 2013)
9) Explain in detail boundary
scan testing (16) (Nov / Dec
2013)
10) Explain the silicon
debug principles (8) (Nov /
Dec 2012)
11) Explain the fault models
(8) (Nov / Dec 2012)
12) Describe the principle
and application of built – in –
self test (8) (Nov / Dec 2012)
13) Explain how to detect a
stuck at fault with example (8)
(Nov / Dec 2012)
UNIT – V
Part – A
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1. Give the comparison between
structural and switch level
modeling (May / June 2013)
2. What are gate primitives
(May / June 2013)
3. What are procedural
assignment in verilog (May /
June 2014)
4. What is a switch level
modeling (May / June 2014)
5. Write the verilog module for
an half adder (Nov / Dec
2011)
6. What are the delay
specification available in
verilog HDL for modeling a
logic gate (Nov / Dec 2011)
7. Differentiate blocking and non
blocking assignments (Nov /
Dec 2013)
8. Mention the possible values
which are allowed in verilog
HDL(Nov / Dec 2013)
9. Write the verilog module for a
1 bit full adder (Nov / Dec
2012)
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10.Give an example for implicit
continuous assignment (Nov /
Dec 2012)
Part - B
1) Design and develop the HDL
project to realize the function
of a priority encoder using
structural model (16) (May /
June 2013)
2) write a data floe model verilog
HDL program for the two
input comparator circuit (8)
(May / June 2013)
3) write a behavioral level
verilog HDL program for the 1
* 8 multiplexer circuits(8)
(May / June 2013
4) Explain the Timing controls
and conditional statements(8)
(May / June 2014)
5) Explain the Behavioral and
gate level modeling (8) (May /
June 2014)
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6) Write the verilog code for
Priority encoder (8) (May /
June 2014)
7) Write the verilog code for
Equality detector (8) (May /
June 2014)
8) Draw the three input CMOS
NOR and NAND gates and
write the verilog switch level
modeling for both (10) (Nov /
Dec 2011)
9) Explain the continuous and
implicit continuous assignment
with two suitable examples for
each(6) (Nov / Dec 2011)
10) Draw the logic diagram
of 4 to 1 MUX using NAND
gates write the gate level
modeling using Verilog
HDL(8) (Nov / Dec 2011)
11) Give a brief note on the
looping statements available in
HDL and write a verilog code
for D Latch(8) (Nov / Dec
2011)
12) Write a verilog HDL for
an 8 bit ripple carry adder
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using structural model (16)
(Nov / Dec 2013)
13) Write a verilog HDL for
a positive edge triggered D
flip-flop using that implements
an 8- bit shift register in
structural model (16) (Nov /
Dec 2013)
14) Draw an action high 2/4
decoder using NOR gates and
write the verilog gate level
description (8) (Nov / Dec
2012)
15) Describe the three ways
of specifying delays in
continuous assignment
statement (8) (Nov / Dec
2012)
16) Write the data flow
modeling for a 4 to 1 MUX
using verilog HDL(8) (Nov /
Dec 2012)17) Explai
n the different timing controls available in verilog HDL(8) (Nov / Dec 2012)
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