Virtex-II™ V2MB1000 Development Board
User’s Guide
Version 3.0
December 2002
PN# DS-MANUAL-V2MB1000
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Table of Contents
1 OVERVIEW ....................................................................................................................1 2 THE VIRTEX-II SYSTEM BOARD ...................................................................................1
2.1 VIRTEX -II SYSTEM BOARD DESCRIPTION ......................................................................2 2.2 VIRTEX -II DEVICE .....................................................................................................2 2.3 DDR MEMORY .........................................................................................................3
2.4 CLOCK GENERATION .................................................................................................4 2.5 RESET CIRCUIT ........................................................................................................5 2.6 USER 7-SEGMENT DISPLAY........................................................................................5
2.6.1 7-Segment Display Signal Description..................................................................6 2.7 USER LED...............................................................................................................6 2.8 USER PUSH BUTTON SWITCHES (SW5, AND SW6) ........................................................6
2.8.1 User Push Button Switch Signal Assignments.......................................................6 2.9 USER DIP SWITCH (SW2) .........................................................................................6
2.9.1 User DIP Switch Interface ...................................................................................6 2.9.2 User DIP Switch Signal Assignments ...................................................................7
2.10 RS232 PORT...........................................................................................................7 2.10.1 RS232 Interface..............................................................................................7 2.10.2 RS232 Signal Descriptions ..............................................................................8
2.11 JTAG PORT ............................................................................................................8 2.11.1 Standard JTAG Connector ..............................................................................8 2.11.2 Parallel Cable IV Port ......................................................................................8 2.11.3 JTAG Chain ...................................................................................................9 2.11.4 JTAG Chain Jumper Settings ..........................................................................9
2.12 SELECTMA P/SLAVE SERIAL PORT ...............................................................................9 2.12.1 Slave SelectMap...........................................................................................10 2.12.2 Master SelectMap.........................................................................................10
2.13 SLAVE SERIAL PORT ...............................................................................................11 2.14 BANK I/O VOLTAGE.................................................................................................11
2.14.1 Bank I/O Voltage Jumper Settings .................................................................11
2.15 VIRTEX -II POWER DOWN MODE ................................................................................12 2.16 VIRTEX -II VBAT.....................................................................................................13 2.17 ISP PROM ...........................................................................................................13
2.18 LVDS PORT ..........................................................................................................14
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2.18.1 LVDS Interface .............................................................................................14 2.18.2 LVDS Port Signal Descriptions ......................................................................17 2.18.3 Packet Over SONET Level 4 (PL4) application ...............................................19
2.19 PROGRAM SWITCH (SW2) .......................................................................................20 2.20 VOLTAGE REGULATORS ...........................................................................................20
2.20.1 Voltage Regulators Jumper Settings ..............................................................21
2.21 VIRTEX -II CONFIGURATION MODE SELECT..................................................................22 2.22 P160 EXPANSION MODULE S IGNAL ASSIGNMENTS.......................................................23
3 DESIGN DOWNLOAD..................................................................................................25
3.1 JTAG INTERFACE...................................................................................................25 3.1.1 Configuring the Virtex-II FPGA...........................................................................25 3.1.2 Programming the XC18V04 ISP PROM..............................................................25
3.2 SLAVE SERIAL INTERFACE........................................................................................26 3.3 MASTER SELECTMAP INTERFACE ..............................................................................26 3.4 SLAVE SELECTMAP INTERFACE.................................................................................26
REVISION HISTORY............................................................................................................27 APPENDIX A – VIRTEX-II SYSTEM BOARD SCHEMATICS ..................................................28
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Figures
FIGURE 1 – V IRTEX -II SYSTEM BOARD .........................................................................................1 FIGURE 2 – VIRTEX-II SYSTEM BOARD BLOCK DIAGRAM.................................................................2 FIGURE 3 – DDR INTERFACE......................................................................................................3 FIGURE 4 – RESET CIRCUIT........................................................................................................5 FIGURE 5 - 7-SEGMENT LED DISPLAY INTERFACE .........................................................................5 FIGURE 6 – USER DIP SWITCH INTERFACE...................................................................................7 FIGURE 7 – RS232 INTERFACE ..................................................................................................7 FIGURE 8 – J2 JTAG CONNECTOR .............................................................................................8 FIGURE 9 – JP29 PARALLEL IV PORT..........................................................................................8 FIGURE 10 – V IRTEX -II SYSTEM BOARD JTAG CHAIN ....................................................................9 FIGURE 11 – SELECTMAP/SLAVE SERIAL CONNECTOR.................................................................10 FIGURE 12 – SLAVE SELECTMAP MODE CONFIGURATION .............................................................10 FIGURE 13 – MASTER SELECTMAP MODE CONFIGURATION...........................................................11 FIGURE 14 – SLAVE SERIAL MODE CONFIGURATION.....................................................................11 FIGURE 15 – V IRTEX -II POWER DOWN MODE..............................................................................13 FIGURE 16 – ISP PROM INTERFACE.........................................................................................14 FIGURE 17 – LVDS TRANSMIT PORT.........................................................................................15 FIGURE 18– LVDS RECEIVE PORT ...........................................................................................16 FIGURE 19– LVDS TRANSMIT AND RECEIVE CONTROL PORTS ......................................................16 FIGURE 20 – PACKET OVER SONET LEVEL 4 (PL4) INTERFACE ...................................................20 FIGURE 21 – V IRTEX -II DEVELOPMENT BOARD VOLTAGE REGULATORS ..........................................21 FIGURE 22 – DOWNLOAD SETUP...............................................................................................25
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Tables
TABLE 1 - DDR MEMORY INTERFACE S IGNAL DESCRIPTIONS ..........................................................3 TABLE 2 – V IRTEX-II DEVELOPMENT BOARD MASTER CLOCKS.........................................................4 TABLE 3 - 7-SEGMENT DISPLAY SIGNAL DESCRIPTIONS ..................................................................6 TABLE 4 - USER PUSH BUTTON SWITCH S IGNAL ASSIGNMENTS .......................................................6 TABLE 5 - USER DIP SWITCH S IGNAL ASSIGNMENTS......................................................................7 TABLE 6 - RS232 S IGNAL DESCRIPTIONS .....................................................................................8 TABLE 7 - JTAG CHAIN JUMPER SETTINGS ..................................................................................9 TABLE 8 - BANK I/O VOLTAGE JUMPER SETTINGS ........................................................................12 TABLE 9 - LVDS TRANSMIT PORT S IGNAL DESCRIPTIONS .............................................................17 TABLE 10 - LVDS RECEIVE PORT S IGNAL DESCRIPTIONS .............................................................18 TABLE 11- LVDS TRANSMIT CONTROL PORT SIGNAL DESCRIPTIONS ..............................................19 TABLE 12- LVDS RECEIVE CONTROL PORT S IGNAL DESCRIPTIONS ...............................................19 TABLE 13 - VOLTAGE REGULATORS JUMPER SETTINGS ................................................................21 TABLE 14 - V IRTEX -II CONFIGURATION MODE SELECT..................................................................22 TABLE 15 – JX1 USER I/O CONNECTOR ....................................................................................23 TABLE 16 – JX2 USER I/O CONNECTOR ....................................................................................24
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1 Overview
The Virtex-II V2MB1000 Development Kit provides a complete solution for developing designs and applications based on the Xilinx Virtex-II FPGA family. The kit bundles an expandable Virtex-II based system board with a power supply, user guide and reference designs. Also available from Memec Design, optional P160 expansion modules enable further application specific prototyping and testing. Xilinx ISE software and a JTAG cable are available as kit options. The Virtex-II system board utilizes the 1-million gate Xilinx Virtex-II device (XC2V1000-4FG456C) in the 456 fine-pitch ball grid array package. The high gate density and large number of user I/Os allows complete system solutions to be implemented in the advanced platform FPGA. The system board includes a 16M x 16 DDR memory, two clock sources, RS-232 port, and additional support circuits. An LVDS interface is provided with a 16-bit transmit and 16-bit receive port plus clock, status, and control signals for each. The board also supports the Memec Design P160 expansion module standard, allowing application specific expansion modules to be easily added. The Virtex-II FPGA family has the advanced features needed to fit demanding, high-performance applications. The Virtex-II Development Kit provides an excellent platform to explore these features so that you can quickly and effectively meet your time-to-market requirements.
2 The Virtex-II System Board
The Memec Design Virtex-II System Board provides the FPGA, support circuits and the P160 expansion slot for application specific add-on cards. Figure 1 shows a picture of the board and its features.
Figure 1 – Virtex-II System Board
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2.1 Virtex-II System Board Description A high-level block diagram of the Virtex-II development board is shown in Figure 2 followed by a brief description of each sub-section.
3.3VRegulator
2.5VRegulator
User7-SegmentDisplay (2)
RS232Port
JTAG Port
ISP PROM(XC18V04)
UserSwitches
UserLEDs
SlaveSerial/SelectMap
Clock Generator(100 & 24Mhz)
Virtex-II FPGAXC2V1000
(FG456)
ResetCircuit
80
-Pin
Co
nn
ec
tor
80
-Pin
Co
nn
ec
tor
P160 Module
32MBDDR SDRAM
16-bitLVDS Interface
1.5VRegulator
Vol tageRegulators
Figure 2 – Virtex-II System Board Block Diagram
2.2 Virtex-II Device
The Virtex-II board utilizes the Xilinx Virtex-II XC2V1000-4FG456C. The Virtex -II family is a platform FPGA developed for high performance, low to high-density designs utilizing IP cores and customized modules. The Virtex-II family delivers complete solutions for telecommunication, wireless, networking, video, and DSP applications. The performance and density of the Virtex-II family along with its supported I/O standards such as LVDS, PCI, and DDR enables FPGA designers to meet the design requirements of the next generation Networking and telecommunication applications. The Xilinx Virtex-II FPGA along with its supporting I/O devices on this development board, will assist FPGA designers to prototype high-performance memory and I/O interfaces such as complete high-performance Packet Over SONET Level 4 (PL4) over a 16-bit LVDS bus, high speed DDR memory interface, and a variety of other I/O interfaces via the on-board I/O module.
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2.3 DDR Memory The Virtex-II development board provides 32MB of DDR memory on the system board. This memory is implemented using the Micron MT46V16M16TG -75 16Mx16 DDR device. A high-level block diagram of the DDR interface is shown below followed by a table describing the DDR memory interface signals.
Virtex-IIFPGA
16M x 16 DDR(MT46V16M16TG-75)
Addr[12:0]
Data[15:0]
BS[1:0]
LDM
UDM
L D Q S
U D Q S
CSn
RASn
CASn
W E n
CLK
C L K n
C L K E
OSC100Mhz
clk_in
clk_fb
reset
Figure 3 – DDR Interface
Table 1 - DDR Memory Interface Signal Descriptions
Signal Name Description FPGA Pin # DDR Pin # A0 Address 0 B18 29 A1 Address 1 A18 30 A2 Address 2 B17 31 A3 Address 3 A17 32 A4 Address 4 N17 35 A5 Address 5 P18 36 A6 Address 6 P17 37 A7 Address 7 M18 38 A8 Address 8 M19 39 A9 Address 9 M20 40 A10 Address 10 A19 28 A11 Address 11 N18 41
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A12 Address 12 N20 42 DQ0 Data 0 Y21 2 DQ1 Data 1 Y22 4 DQ2 Data 2 W21 5 DQ3 Data 3 V21 7 DQ4 Data 4 V22 8 DQ5 Data 5 U21 10 DQ6 Data 6 U22 11 DQ7 Data 7 T21 13 DQ8 Data 8 R20 54 DQ9 Data 9 R19 56 DQ10 Data 10 T20 57 DQ11 Data 11 T19 59 DQ12 Data 12 U19 60 DQ13 Data 13 V20 62 DQ14 Data 14 V19 63 DQ15 Data 15 W20 65 BS0 Bank Select 0 M21 26 BS1 Bank Select 1 B19 27 LDM Low Write Mask R21 20 UDM High Write Mask T22 47 LDQS Low Write/Read Data Strobe P20 16 UDQS High Write/Read Data Strobe P19 51 CSn Chip Select N22 24 RASn Row Address Strobe N21 23 CASn Column Address Strobe P21 22 WEn Write Enable R22 21 CLK Clock D12 45 CLKn Clock E12 46 CKE Clock Enable N19 44
2.4 Clock Generation The Virtex-II system board provides two on-board oscillators running at 100Mhz (CLK.CAN2) and 24Mhz (CLK.CAN1). The 100Mhz oscillator is enabled when the JP24 jumper is open and disabled when JP24 is closed. JP23 controls the 24MHz oscillator, enabling it when open and disabling it when closed. A third user clock socket is provided for addition of a user specified oscillator device. The following table provides a brief description of these clock signals.
Table 2 – Virtex-II Development Board Master Clocks Signal Name Virtex-II Pin # Direction Description CLK.CAN2 B11 Input On-board 100 MHz Oscillator CLK.CAN1 A11 Input On-board 24 MHz Oscillator CLK.CAN3 F12 Input User clock socket (2.5V supply)
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2.5 Reset Circuit The Virtex-II system board uses the TI TPS3125 voltage supervisory device to monitor the Virtex-II FPGA core voltage (1.5V). This circuit asserts a reset signal (FPGA_RESETn) to the Virtex-II device when the 1.5V core voltage falls below its minimum specifications (1.425V). The reset signal to the FPGA is a fixed 100ms active low pulse. In addition to monitoring the core voltage, this circuit can be used to generate a reset pulse by activating the Master Reset (MRn) signal to the TPS3125 device via the on-board push-button switch (SW3). The following figure shows the reset circuit on the Virtex-II development board.
S W 3
RESETn
M R n
V D D
TPS3125
FPGA_RESETn
1.5V
B 6
FPGA
Figure 4 – Reset Circuit
2.6 User 7-Segment Display
The Virtex-II system board utilizes two common-cathode 7-segment LED displays that can be used during the test and debugging phase of a design. The user can turn a given segment on by driving the associated signal high. The following figure shows the user 7-segment display interface to the Virtex-II FPGA.
A 1
B1
C 1D1
E1
F1G1
A 2
B2
C 2D2
E2
F2G2
DISPLAY.1F
DISPLAY.1G
DISPLAY.1E
DISPLAY.1D
DISPLAY.1C
DISPLAY.1B
DISPLAY.1A
DISPLAY.2F
DISPLAY.2G
DISPLAY.2E
DISPLAY.2D
DISPLAY.2C
DISPLAY.2B
DISPLAY.2A
Figure 5 - 7-Segment LED Display Interface
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2.6.1 7-Segment Display Signal Description The following table shows the 7-Segment LED display pin descriptions.
Table 3 - 7-Segment Display Signal Descriptions
Signal Name Virtex-II Pin # Description DISPLAY.1A D9 7-Segment LED Display1, Segment A DISPLAY.1B C9 7-Segment LED Display1, Segment B DISPLAY.1C F11 7-Segment LED Display1, Segment C DISPLAY.1D F9 7-Segment LED Display1, Segment D DISPLAY.1E F10 7-Segment LED Display1, Segment E DISPLAY.1F D10 7-Segment LED Display1, Segment F DISPLAY.1G C10 7-Segment LED Display1, Segment G DISPLAY.2A B9 7-Segment LED Display2, Segment A DISPLAY.2B A8 7-Segment LED Display2, Segment B DISPLAY.2C B8 7-Segment LED Display2, Segment C DISPLAY.2D E7 7-Segment LED Display2, Segment D DISPLAY.2E E8 7-Segment LED Display2, Segment E DISPLAY.2F E10 7-Segment LED Display2, Segment F DISPLAY.2G E9 7-Segment LED Display2, Segment G
2.7 User LED
The Virtex-II system board provides a single user LED. Pin A9 of the Virtex -II FPGA is used to drive this active high signal.
2.8 User Push Button Switches (SW5, and SW6) The Virtex-II system board provides two user push button switch inputs to the Virtex-II FPGA. Each push button switch can be used to generate an active low signal.
2.8.1 User Push Button Switch Signal Assignments The following table shows the pin assignments for the user push button switches.
Table 4 - User Push Button Switch Signal Assignments Signal Name Virtex-II Pin # Description FPGA.PUSH1 D7 User Push Button Switch Input 1 (SW5) FPGA.PUSH2 A6 User Push Button Switch Input 2 (SW6)
2.9 User DIP Switch (SW2) The Virtex-II system board provides 8 user switch inputs. These switches can be statically set to a low or high logic level.
2.9.1 User DIP Switch Interface The following figure shows the user DIP switch interface to the Virtex-II FPGA.
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54321
678
1213141516
1110
9
S W 4Swi tch
DIP8
DIP7
DIP6
DIP5
DIP4
DIP3
DIP2
DIP1
Figure 6 – User DIP Switch Interface
2.9.2 User DIP Switch Signal Assignments The following table shows the user switch pin assignments.
Table 5 - User DIP Switch Signal Assignments
Signal Name Virtex-II Pin # Description DIP8 C6 User Switch Input 8 DIP7 D6 User Switch Input 7 DIP6 A5 User Switch Input 6 DIP5 B5 User Switch Input 5 DIP4 C5 User Switch Input 4 DIP3 C4 User Switch Input 3 DIP2 A4 User Switch Input 2 DIP1 B4 User Switch Input 1
2.10 RS232 Port The Virtex-II system board provides an RS232 port that can be driven by the Virtex-II FPGA. A subset of the RS232 signals is used on the Virtex-II development board to implement this simple interface (RD and TD signals).
2.10.1 RS232 Interface The Virtex-II system board provides a DB-9 connection for a simple RS232 port. The board utilizes the TI MAX3221 RS232 driver for driving the RD and TD signals. The user provides the RS232 UART code, which resides in the Virtex-II FPGA.
RS232Drivers
MAX3221
RXD
T X D
R D
TD
2
3
JDR1Connector
Rout
Din
Rin
Dout
Figure 7 – RS232 Interface
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2.10.2 RS232 Signal Descriptions The following table shows the RS232 signals and their pin assignments to the Virtex-II FPGA.
Table 6 - RS232 Signal Descriptions
Signal Name Virtex-II Pin # Description RXD A7 Received Data, RD to DB9 TXD B7 Transmit Data, TD from DB9
2.11 JTAG Port
The Virtex-II development board provides a JTAG connector that can be used to program the on-board ISP PROM and configure the Virtex-II FPGA. Two connector options are provided, J2 is a 1 x 7 header used to connect standard JTAG cable fly leads, and JP29 is used for connection of the Xilinx Parallel IV JTAG cable.
2.11.1 Standard JTAG Connector The following figure shows the pin assignments for the J2 JTAG connector on the Virtex-II development board.
12
4
67
3
5
J2JTAG
Connector
3.3VG N D
TCKT D OTDI
T M S
Figure 8 – J2 JTAG Connector
2.11.2 Parallel Cable IV Port The following figure shows the pin assignments for the Parallel Cable IV connector. The Parallel Cable IV can also be used to configure the FPGA via Slave Serial configuration mode.
TCK/CCLKTDO/DONE
TDI/DIN
TMS/PROG
JP20ParallelCable IV
1 246
7
35
89 10
1214
1113
2.5V
Figure 9 – JP29 Parallel IV Port
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2.11.3 JTAG Chain The following figure shows the JTAG chain on the Virtex-II development board. Jumper JP22 provides the ability to remove the ISP PROM from the JTAG chain for direct connection to the FPGA.
XC18V04ISP
PROM
Virtex-IIFPGATDI T D O
TDI
TDI
T D O
T D O
T M S
TCK
T M S
TCK
T M S
TCK
JP221 2 3 4
Figure 10 – Virtex-II System Board JTAG Chain
2.11.4 JTAG Chain Jumper Settings The following table shows the JTAG chain jumper setting on the Virtex-II development board.
Table 7 - JTAG Chain Jumper Settings
Jumper Setting Description 1-2 Closed Disable PROM JP28 2-3 Closed Enable PROM (normal setting)
1-2, 3-4 PROM in chain (normal setting) JP22 2-3 Remove PROM from chain (FPGA only)
2.12 SelectMap/Slave Serial Port
In addition to the JTAG mode, the Virtex-II FPGA on the development board can be configured using the Slave Serial or the SelectMap mode of configuration. The following figure shows the connector pin assignments for the Slave Serial/SelectMap port.
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C C L K
DONE
CSn
INITn
J3Se lec tMap/S lave Ser ia l
C o n n e c t o r
1 2
4
6
7
9
3
5
8
11
13
15
10
12
14
16
P R O G R A M n
RD/Wn
DOUT/BUSY
D0
D1
D2
D3
D4
D5
D6
D7
Figure 11 – SelectMap/Slave Serial Connector
2.12.1 Slave SelectMap In the Slave SelectMAP configuration mode, a byte of configuration data is loaded into the Virtex-II FPGA during each CCLK clock cycle. In this mode, an external source drives the CCLK clock and the data bus containing the configuration data. The following figure shows the Slave SelectMap configuration mode interface to the Virtex-II FPGA.
Vir tex- I IFPGA
C C L K
DONE
CSn
INITn
P R O G R A M n
RD/Wn
DOUT/BUSY
D[0:7]D[0:7]
DONE
C C L K
INIT_B
PROG_B
RDWR_B
BUSY
CS_B
Figure 12 – Slave SelectMap Mode Configuration
2.12.2 Master SelectMap In the Master SelectMAP configuration mode, a byte of configuration data is loaded into the Virtex-II FPGA during each CCLK clock cycle. In this mode, the Virtex-II FPGA drives the CCLK clock while receiving configuration data from the PROM. The following figure shows the Master SelectMap configuration mode interface to the Virtex-II FPGA. The JP27 jumper must be installed when configuring the Virtex-II FPGA in the Master SelectMap mode.
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Vir tex- I IFPGA
C C L K
DONE
CS_B
INIT_B
PROG_B
RDWR_B
D[0:7]
XC18V04C F
C E
RESET/OE
C C L K
D[0:7]
JP27J u m p e r
Figure 13 – Master SelectMap Mode Configuration
2.13 Slave Serial Port
In the Slave Serial configuration mode, a bit of configuration data is loaded into the FPGA during each CCLK clock cycle. In this mode, an external source places the most significant bit of each byte on the DIN pin first and then drives the CCLK clock to store data into the FPGA. The following figure shows the Slave Serial configuration mode interface to the Virtex-II FPGA.
Vir tex- I IFPGA
C C L K
DONE
INITn
P R O G R A M n
D0DIN
DONE
C C L K
INIT_B
PROG_B
Figure 14 – Slave Serial Mode Configuration
2.14 Bank I/O Voltage The Virtex-II development board allows the Virtex-II I/O pins to be configured for 2.5V or 3.3V operation. All Virtex-II user I/O pins are grouped in 8 different banks. Each bank of I/O pins on the board can be configured to operate in the 2.5V or the 3.3V mode.
2.14.1 Bank I/O Voltage Jumper Settings The following table shows the jumper settings for the Virtex-II bank I/O voltage (VCCO) selection. Each bank can be set to 2.5V or 3.3V.
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Table 8 - Bank I/O Voltage Jumper Settings
Bank # Virtex-II VCCO
Pin # Jumper
JP18 1-2 2-3
I/O Voltage
Closed Open 3.3V
0
Open Closed 2.5V 1 FIXED 2.5V
JP26 1-2 2-3
Closed Open 3.3V
2
Open Closed 2.5V 3 FIXED 2.5V
J19 1-2 2-3
Closed Open 3.3V
4
Open Closed 2.5V J20
1-2 2-3
Closed Open 3.3V
5
Open Closed 2.5V J21
1-2 2-3
Closed Open 3.3V
6
Open Closed 2.5V J21
1-2 2-3
Closed Open 3.3V
7
Open Closed 2.5V
2.15 Virtex-II Power Down Mode
The Virtex-II FPGA family utilizes a dedicated pin called PWRDWN_B that can be used to place the Virtex-II FPGA into a low-power and inactive state. In the normal operating mode, the PWRDWN_B pin would be pulled up. Forcing the PWRDWN_B pin to logic 0 would place the Virtex-II FPGA in power-down mode. The following figure shows the Virtex-II Power Down on the Virtex-II development board.
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3.3V
Virtex-II FPGA
PWRDWN_B
JP
16
Jum
per
Figure 15 – Virtex-II Power Down Mode As shown in the above figure, the Virtex -II FPGA can be placed in the power-down mode on the Virtex-II system board by closing the JP16 jumper (permanently placing it in the power-down mode until the jumper is removed), or by forcing the pin 2 of the JP16 to a logic 0 under user control. The Virtex-II board users can use this pin to place the Virtex -II FPGA in the power-down mode momentarily. The Virtex-II FPGA provides Power-Down status information via the DONE pin if the PWRDWN_STAT option is selected using BitGen. The DONE pin is asserted upon entry to the power-down mode. After a successful wake-up, the DONE status pin is de-asserted (The wake-up sequence is the reverse of the power-down sequence). While in power-down mode, the only active pins are the PWRDWN_B and DONE. All inputs are off and all outputs are 3-stated. While in the Power-Down state, the Power On Reset (POR) circuit is still active, but it does not reset the device if VCCINT, VCCO, or VCCAUX falls below its minimum value. The POR circuit waits until the PWRDWN_B pin is released before resetting the device. Also, the PROG_B pin is not sampled while the device is in the Power-Down state. The PROG_B pin becomes active when the PWRDWN_B pin is released. Therefore, the device cannot be reset while in the Power-Down state.
2.16 Virtex-II VBAT
The Virtex-II VBAT input pin (pin A21) is connected to the 3.3V supply on the Virtex-II development board through the JP15 jumper.
2.17 ISP PROM The Virtex-II system board utilizes the Xilinx XC18V04 ISP PROM, allowing FPGA designers to quickly download revisions of a design and verify the design changes in order to meet the final system-level design requirements. The XC18V04 ISP PROM uses two interfaces to accomplish the configuration of the Virtex-II FPGA.
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The JTAG port on the XC18V04 device is used to program the PROM with the design bit file. Once the XC18V04 has been programmed, the user can configure the Virtex-II device in Master Serial or Master SelectMap mode. The configuration of the Virtex-II device is initiated by asserting the PROGn signal. Upon activation of the PROGn signal (by pressing the SW2 switch), the XC18V04 device will use its FPGA Configuration Port to configure the Virtex-II FPGA. If the Virtex-II configuration mode is set to Master Serial, the PROM D0, CE, CCLK, RESET/OE, and the CF signals are used to configure the Virtex-II FPGA. In the Master SelectMap mode, in addition to the above signals, the Virtex-II FPGA will use the PROM D1-7 to obtain a byte of configuration data during each CCLK clock cycle. The following figure shows the ISP PROM interface to the JTAG port and the Virtex-II FPGA configuration port.
C C L K
DONE
CS_B
INIT_B
PROG_B
RDWR_B
D[0:7]
C F
C E
RESET/OE
C C L K
D[0:7]
Vir tex- I I FPGAXC18V04 ISP PROM
TDI
T M S
T C K
TDO
J T A GPor t
Figure 16 – ISP PROM Interface
2.18 LVDS Port The Virtex-II development board provides a complete high-performance differential signaling (LVDS) interface, enabling the designers to prototype high-speed serial communication links. The Virtex-II I/Os are designed to comply with the IEEE electrical specifications for LVDS to make system and board design easier. With the addition of an LVDS current-mode driver in the IOBs, which eliminates the need for external source termination in point -to-point applications, and with the choice of two different voltage modes and an extended mode, Virtex-II devices provide the most flexible solution for doing an LVDS design in an FPGA.
2.18.1 LVDS Interface The Virtex-II development board provides a 16-bit LVDS port (Transmit and Receive) with 6 additional control signals that can be used to implement a high-speed Packet Over SONET Level 4 (PL4) interface. The following figure shows the LVDS interface on the Virtex-II development board. LVDS termination networks are provided between the Virtex-II FPGA and the LVDS user connectors. It should be noted that no LVDS source terminations are needed when using the Virtex-II FPGA family in point-to-point applications.
December 2, 2002 15
LV
DS
Tra
ns
mit
Co
nn
ec
tor
8
2
4
J4
6
1
3
5
7
LVDSOUT3N
LVDSOUT3P
LVDSOUT4N
LVDSOUT4P
LVDSOUT1N
LVDSOUT1P
LVDSOUT2N
LVDSOUT2P
18
12
14
16
11
13
15
17
LVDSOUT7N
LVDSOUT7P
LVDSOUT8N
LVDSOUT8P
LVDSOUT5N
LVDSOUT5P
LVDSOUT6N
LVDSOUT6P
28
22
24
26
21
23
25
27
LVDSOUT11N
LVDSOUT11P
LVDSOUT12N
LVDSOUT12P
LVDSOUT9N
LVDSOUT9P
LVDSOUT10N
LVDSOUT10P
38
32
34
36
31
33
35
37
LVDSOUT15N
LVDSOUT15P
LVDSOUT16N
LVDSOUT16P
LVDSOUT13N
LVDSOUT13P
LVDSOUT14N
LVDSOUT14P
Figure 17 – LVDS Transmit Port
December 2, 2002 16
SourceTermination
Resistors
LV
DS
Re
ce
ive
Co
nn
ec
tor
10
4
6
J6
8
3
5
7
9
LVDSIN3P
LVDSIN3N
LVDSIN4P
LVDSIN4N
LVDSIN1P
LVDSIN1N
LVDSIN2P
LVDSIN2N
20
14
16
18
13
15
17
19
LVDSIN7P
LVDSIN7N
LVDSIN8P
LVDSIN8N
LVDSIN5P
LVDSIN5N
LVDSIN6P
LVDSIN6N
30
24
26
28
23
25
27
29
LVDSIN11P
LVDSIN11N
LVDSIN12P
LVDSIN12N
LVDSIN9P
LVDSIN9N
LVDSIN10P
LVDSIN10N
40
34
36
38
33
35
37
39
LVDSIN15P
LVDSIN15N
LVDSIN16P
LVDSIN16N
LVDSIN13P
LVDSIN13N
LVDSIN14P
LVDSIN14N
Figure 18– LVDS Receive Port
LV
DS
Tra
ns
mit
Co
nn
ec
tor
(Co
ntr
ol
Sig
na
ls)
12
2
6
J7
10
1
5
9
11
LVDSOUTSTAT1P
LVDSOUTSTAT1N
LVDSOUTSTAT2P
LVDSOUTSTAT2N
LVDSOUTCLKP
LVDSOUTCLKN
LVDSOUTCTRLP
LVDSOUTCTRLN14
13
LVDSOUTSTATCLKP
LVDSOUTSTATCLKN
LV
DS
Re
ce
ive
Co
nn
ec
tor
(Co
ntr
ol
Sig
na
ls)
10
2
4
J8
6
1
3
5
9
LVDSINSTAT1P
LVDSINSTAT1N
LVDSINSTAT2P
LVDSINSTAT2N
LVDSINCLKP
LVDSINCLKN
LVDSINCTRLP
LVDSINCTRLN
14
13
LVDSINSTATCLKP
LVDSINSTATCLKN
SourceTermination
Resistors
Figure 19– LVDS Transmit and Receive Control Ports
December 2, 2002 17
2.18.2 LVDS Port Signal Descriptions The following table shows the LVDS port signal descriptions and the port signal assignments to the Virtex-II FPGA.
Table 9 - LVDS Transmit Port Signal Descriptions
Signal Name Virtex-II Pin # J4 Pin # Description LVDSOUT1N H2 1 Negative Data Transmit Bit 1 LVDSOUT1P H1 2 Positive Data Transmit Bit 1 LVDSOUT2N J2 3 Negative Data Transmit Bit 2 LVDSOUT2P J1 4 Positive Data Transmit Bit 2 LVDSOUT3N K2 5 Negative Data Transmit Bit 3 LVDSOUT3P K1 6 Positive Data Transmit Bit 3 LVDSOUT4N E4 7 Negative Data Transmit Bit 4 LVDSOUT4P E3 8 Positive Data Transmit Bit 4
GND NA 9 Ground GND NA 10 Ground
LVDSOUT5N F4 11 Negative Data Transmit Bit 5 LVDSOUT5P F3 12 Positive Data Transmit Bit 5 LVDSOUT6N G4 13 Negative Data Transmit Bit 6 LVDSOUT6P G3 14 Positive Data Transmit Bit 6 LVDSOUT7N H4 15 Negative Data Transmit Bit 7 LVDSOUT7P H3 16 Positive Data Transmit Bit 7 LVDSOUT8N J4 17 Negative Data Transmit Bit 8 LVDSOUT8P J3 18 Positive Data Transmit Bit 8
GND NA 19 Ground GND NA 20 Ground
LVDSOUT9N K4 21 Negative Data Transmit Bit 9 LVDSOUT9P K3 22 Positive Data Transmit Bit 9
LVDSOUT10N L3 23 Negative Data Transmit Bit 10 LVDSOUT10P L2 24 Positive Data Transmit Bit 10 LVDSOUT11N L5 25 Negative Data Transmit Bit 11 LVDSOUT11P L4 26 Positive Data Transmit Bit 11 LVDSOUT12N E6 27 Negative Data Transmit Bit 12 LVDSOUT12P E5 28 Positive Data Transmit Bit 12
GND NA 29 Ground GND NA 30 Ground
LVDSOUT13N F5 31 Negative Data Transmit Bit 13 LVDSOUT13P G5 32 Positive Data Transmit Bit 13 LVDSOUT14N H5 33 Negative Data Transmit Bit 14 LVDSOUT14P J6 34 Positive Data Transmit Bit 14 LVDSOUT15N J5 35 Negative Data Transmit Bit 15 LVDSOUT15P K5 36 Positive Data Transmit Bit 15 LVDSOUT16N K6 37 Negative Data Transmit Bit 16 LVDSOUT16P L6 38 Positive Data Transmit Bit 16
GND NA 39 Ground GND NA 40 Ground
December 2, 2002 18
Table 10 - LVDS Receive Port Signal Descriptions
Signal Name Virtex-II Pin # J6 Pin # Description GND NA 1 Ground GND NA 2 Ground
LVDSIN1P M2 3 Positive Data Receive Bit 1 LVDSIN1N M1 4 Negative Data Receive Bit 1 LVDSIN2P N2 5 Positive Data Receive Bit 2 LVDSIN2N N1 6 Negative Data Receive Bit 2 LVDSIN3P P2 7 Positive Data Receive Bit 3 LVDSIN3N P1 8 Negative Data Receive Bit 3 LVDSIN4P R2 9 Positive Data Receive Bit 4 LVDSIN4N R1 10 Negative Data Receive Bit 4
GND NA 11 Ground GND NA 12 Ground
LVDSIN5P T2 13 Positive Data Receive Bit 5 LVDSIN5N T1 14 Negative Data Receive Bit 5 LVDSIN6P U2 15 Positive Data Receive Bit 6 LVDSIN6N U1 16 Negative Data Receive Bit 6 LVDSIN7P V2 17 Positive Data Receive Bit 7 LVDSIN7N V1 18 Negative Data Receive Bit 7 LVDSIN8P W2 19 Positive Data Receive Bit 8 LVDSIN8N W1 20 Negative Data Receive Bit 8
GND NA 21 Ground GND NA 22 Ground
LVDSIN9P Y2 23 Positive Data Receive Bit 9 LVDSIN9N Y1 24 Negative Data Receive Bit 9 LVDSIN10P M6 25 Positive Data Receive Bit 10 LVDSIN10N M5 26 Negative Data Receive Bit 10 LVDSIN11P M4 27 Positive Data Receive Bit 11 LVDSIN11N M3 28 Negative Data Receive Bit 11 LVDSIN12P N4 29 Positive Data Receive Bit 12 LVDSIN12N N3 30 Negative Data Receive Bit 12
GND NA 31 Ground GND NA 32 Ground
LVDSIN13P P4 33 Positive Data Receive Bit 13 LVDSIN13N P3 34 Negative Data Receive Bit 13 LVDSIN14P R4 35 Positive Data Receive Bit 14 LVDSIN14N R3 36 Negative Data Receive Bit 14 LVDSIN15P T4 37 Positive Data Receive Bit 15 LVDSIN15N T3 38 Negative Data Receive Bit 15 LVDSIN16P U4 39 Positive Data Receive Bit 16 LVDSIN16N U3 40 Negative Data Receive Bit 16
December 2, 2002 19
Table 11- LVDS Transmit Control Port Signal Descriptions
Signal Name Virtex-II Pin # J7 Pin # Description LVDSOUTCLKP C1 1 Positive Transmit Clock LVDSOUTCLKN C2 2 Negative Transmit Clock
GND NA 3 Ground GND NA 4 Ground
LVDSOUTSTATCLKP D1 5 Positive Transmit Status Clock LVDSOUTSTATCLKN D2 6 Negative Transmit Status Clock
GND NA 7 Ground GND NA 8 Ground
LVDSOUTSTAT1P E1 9 Positive Transmit Status1 LVDSOUTSTAT1N E2 10 Negative Transmit Status1 LVDSOUTSTAT2P F1 11 Positive Transmit Status2 LVDSOUTSTAT2N F2 12 Negative Transmit Status2 LVDSOUTCTRLP G1 13 Positive Transmit Control LVDSOUCTRLN G2 14 Negative Transmit Control
Table 12- LVDS Receive Control Port Signal Descriptions
Signal Name Virtex-II Pin # J8 Pin # Description LVDSINCTRLN V3 1 Negative Receive Control LVDSINCTRLP V4 2 Positive Receive Control LVDSINSTAT2N N5 3 Negative Receive Status2 LVDSINSTAT2P N6 4 Positive Receive Status2 LVDSINSTAT1N P5 5 Negative Receive Status1 LVDSINSTAT1P P6 6 Positive Receive Status1
GND NA 7 Ground GND NA 8 Ground
LVDSINSTATCLKN W11 9 Negative Receive Status Clock LVDSINSTATCLKP V11 10 Positive Receive Status Clock
GND NA 11 Ground GND NA 12 Ground
LVDSINCLKN AA11 13 Negative Receive Clock LVDSINCLKP Y11 14 Positive Receive Clock
2.18.3 Packet Over SONET Level 4 (PL4) application One of the possible applications of the LVDS port on the Virtex-II development board is to prototype a high-speed Packet Over SONE T Level 4 (PL4) interface. PL4 is used in point-to-point applications supporting OC-192 (10 Gbit/s) aggregate bandwidth. The following figure shows how the Virtex-II along with the LVDS port on the Virtex -II development board can be used to implement the PL4 interface. This interface supports 16 bits of data and various miscellaneous signals to control the flow of the data transmission in each direction. Specifically, the status_data_tx[1:0] and status_clk_tx signals are used to control the transmit FIFO, while the status_data_rx[1:0] and status_clk_rx signals are used to control the receive FIFO.
December 2, 2002 20
data_tx[15:0]
clk_tx
control_tx
status_data_tx[1:0]
status_clk_tx
data_tx[15:0]
clk_tx
control_tx
status_data_tx[1:0]
status_clk_tx
TransmitLink
Layer
data_rx[15:0]
clk_rx
control_rx
status_data_rx[1:0]
status_clk_rx
data_rx[15:0]
clk_rx
control_rx
status_data_rx[1:0]
status_clk_rx
ReceiveLink
Layer
P H YDevice
Virtex-IIFPGA
Figure 20 – Packet Over SONET Level 4 (PL4) Interface
2.19 Program Switch (SW2) The Virtex-II system board provides a push button switch for initiating the configuration of the Virtex-II FPGA. This switch is used when the XC18V04 ISP PROM configures the Virtex-II FPGA. After programming of the XC18V04 ISP PROM, this switch can assert the PROGn signal. Upon activation of the PROGn signal, the XC18V04 ISP PROM initiates the configuration of the Virtex-II FPGA.
2.20 Voltage Regulators The following figure shows the voltage regulators that are used on the Virtex-II development board to provide various on-board voltage sources. As shown in the following figure, JP1 connector is used to provide the main 5.0V voltage to the board. This voltage source is provided to all on-board regulators to generate the 1.5V, 2.5V, and 3.3V voltages.
December 2, 2002 21
1.5VReg
JP12Jumper
JP9Jumper
JP6Jumper
3.3V 1.5V2.5V
JP131.5V
Connector
JP102.5V
Connector
JP73.3V
Connector
JP15.0V
Connector
3.3VReg
2.5VReg
Figure 21 – Virtex-II Development Board Voltage Regulators For any one of the on-board voltages (1.5V, 2.5V, and 3.3V), if the current provided by the on-board regulator is not sufficient for some applications, the user can directly drive the voltage source and bypass the on-board regulators. This can be accomplished by removing jumpers JP6, JP9, and JP12 for voltages 3.3V through 1.5V respectively.
2.20.1 Voltage Regulators Jumper Settings The following table shows the jumper setting for the 3.3V, 2.5V, and the 1.5V supply voltages on the Virtex-II development board.
Table 13 - Voltage Regulators Jumper Settings Jumper Jumper
Setting 3.3V Source 2.5V Source 1.5V Source
Open External 3.3V supply via JP7 connector
NA NA JP6
Closed On-board 3.3V regulator
NA NA
Open NA External 2.5V supply via JP10 connector
NA JP9
Closed NA On-board 2.5V regulator
NA
Open NA NA External 1.5V supply via JP13 connector
JP12
Closed NA NA On-board 1.5V regulator
December 2, 2002 22
2.21 Virtex-II Configuration Mode Select The following table shows the Virtex-II Configuration Mode Select jumper settings. The jumper position 7-8 (M3) is connected to the HSWAP_EN pin of the Virtex-II FPGA. When this jumper is closed, the Virtex-II internal I/O pull-ups are enabled during the configuration.
Table 14 - Virtex-II Configuration Mode Select
J1 Mode PC Pull-up 1-2 (M0) 3-4 (M1) 5-6 (M2) 7-8 (M3)
Master Serial No Closed Closed Closed Closed Master Serial Yes Closed Closed Closed Open Slave Serial No Open Open Open Closed Slave Serial Yes Open Open Open Open Master SelectMap No Closed Open Open Closed Master SelectMap Yes Closed Open Open Open Slave SelectMap No Open Open Closed Closed Slave SelectMap Yes Open Open Closed Open JTAG No Open Closed Open Closed JTAG Yes Open Closed Open Open
December 2, 2002 23
2.22 P160 Expansion Module Signal Assignments The following tables show the Virtex-II pin assignments to the P160 Expansion Module connectors (JX1 & JX2) located on the Virtex-II development board.
Table 15 – JX1 User I/O Connector
FPGA Pin #
I/O Connector
Signal Name
JX1 Pin #
I/O Connector
Signal Name
FPGA Pin #
NA NC A1 B1 NC NA NA GND A2 B2 NC NA NA NC A3 B3 NC NA NA Vin A4 B4 NC NA NA NC A5 B5 NC NA NA GND A6 B6 NC NA NA NC A7 B7 NC NA NA 3.3V A8 B8 LIOB8 L22 K22 LIOA9 A9 B9 LIOB9 L21 NA GND A10 B10 LIOB10 K21 J21 LIOA11 A11 B11 LIOB11 J22 NA 2.5V A12 B12 LIOB12 H22
G22 LIOA13 A13 B13 LIOB13 H21 NA GND A14 B14 LIOB14 G21 F21 LIOA15 A15 B15 LIOB15 F22 NA Vin A16 B16 LIOB16 E22
D22 LIOA17 A17 B17 LIOB17 E21 NA GND A18 B18 LIOB18 D21
C21 LIOA19 A19 B19 LIOB19 C22 NA 3.3V A20 B20 LIOB20 L18 L20 LIOA21 A21 B21 LIOB21 L19 NA GND A22 B22 LIOB22 K18 K19 LIOA23 A23 B23 LIOB23 K20 NA 2.5V A24 B24 LIOB24 J20
H20 LIOA25 A25 B25 LIOB25 J19 NA GND A26 B26 LIOB26 H19
G19 LIOA27 A27 B27 LIOB27 G20 NA Vin A28 B28 LIOB28 E19 F20 LIOA29 A29 B29 LIOB29 E20 NA GND A30 B30 LIOB30 L17 F19 LIOA31 A31 B31 LIOB31 K17 NA 3.3V A32 B32 LIOB32 J17
D11 LIOA33 A33 B33 LIOB33 J18 NA GND A34 B34 LIOB34 H18
C11 LIOA35 A35 B35 LIOB35 G18 NA 2.5V A36 B36 LIOB36 F18 C8 LIOA37 A37 B37 LIOB37 E18 NA GND A38 B38 LIOB38 E11 D8 LIOA39 A39 B39 LIOB39 A10 NA Vin A40 B40 LIOB40 B10
December 2, 2002 24
Table 16 – JX2 User I/O Connector
FPGA Pin #
I/O Connector
Signal Name
JX2 Pin #
I/O Connector Signal
Name
FPGA Pin #
AB18 RIOA1 A1 B1 GND NA AA16 RIOA2 A2 B2 RIOB2 Y15 AA17 RIOA3 A3 B3 Vin NA AB16 RIOA4 A4 B4 RIOB4 W14 AB17 RIOA5 A5 B5 GND NA AA15 RIOA6 A6 B6 RIOB6 Y14 W17 RIOA7 A7 B7 3.3V NA AB15 RIOA8 A8 B8 RIOB8 W13 Y17 RIOA9 A9 B9 GND NA
AA14 RIOA10 A10 B10 RIOB10 Y13 W16 RIOA11 A11 B11 2.5V NA AB14 RIOA12 A12 B12 RIOB12 V13 Y16 RIOA13 A13 B13 GND NA
AA13 RIOA14 A14 B14 RIOB14 Y12 V16 RIOA15 A15 B15 Vin NA
AB13 RIOA16 A16 B16 RIOB16 W12 W15 RIOA17 A17 B17 GND NA AA12 RIOA18 A18 B18 RIOB18 V12 V14 RIOA19 A19 B19 3.3V NA
AB12 RIOA20 A20 B20 RIOB20 V10 U14 RIOA21 A21 B21 GND NA AB9 RIOA22 A22 B22 RIOB22 Y10 U13 RIOA23 A23 B23 2.5V NA AA9 RIOA24 A24 B24 RIOB24 W10 U12 RIOA25 A25 B25 GND NA AB8 RIOA26 A26 B26 RIOB26 Y9 U11 RIOA27 A27 B27 Vin NA AA8 RIOA28 A28 B28 RIOB28 W9 U10 RIOA29 A29 B29 GND NA AB7 RIOA30 A30 B30 RIOB30 Y8 U9 RIOA31 A31 B31 3.3V NA AA7 RIOA32 A32 B32 RIOB32 W8 V9 RIOA33 A33 B33 GND NA
AB6 RIOA34 A34 B34 RIOB34 Y7 V8 RIOA35 A35 B35 2.5V NA
AA6 RIOA36 A36 B36 RIOB36 W7 V7 RIOA37 A37 B37 GND NA
AB5 RIOA38 A38 B38 RIOB38 Y6 V6 RIOA39 A39 B39 Vin NA
AA5 RIOA40 A40 B40 RIOB40 W6
December 2, 2002 25
3 Design Download
The Virtex-II development board supports multiple methods of configuring the Virtex-II FPGA. The JTAG port on the Virtex-II development board can be used to directly configure the Virtex-II FPGA, or to program the on-board XC18V04 ISP PROM. Once the ISP PROM is programmed, it can be used to configure the Virtex -II FPGA. The SelectMap/Slave Serial port on this development board can also be used to configure the Virtex-II FPGA. The following figure shows the setup for all Virtex-II FPGA configuration modes that are supported on the Virtex-II development board.
PC
JTAGCable
Virtex-IIDevelopment
Board
J2
JP
1
AC
/DC
Ad
ap
ter
ParallelPort
J3
Slave Serial/SelectMap
Figure 22 – Download Setup
3.1 JTAG Interface The J2 JTAG connector on the Virtex-II development board can be used to configure the Virtex -II or to program the on-board XC18V04 ISP PROM. The Memec Design JTAG cable is connected to the Virtex-II development board via J2 at one end and to the PC parallel port at the other end.
3.1.1 Configuring the Virtex-II FPGA When the JTAG port is used to configure the Virtex-II FPGA, the following steps must be taken:
• Using Table 14 set the Configuration Mode of the Virtex-II FPGA to JTAG Mode. • Use the Xilinx JTAG programmer utility (iMPACT) to load the design bit file into the
Virtex-II FPGA. You will need to associate the ISP PROM with either a dummy .mcs file, or a .bsd file to allow the JTAG programming software to pass data through the ISP PROM.
3.1.2 Programming the XC18V04 ISP PROM When the JTAG port is used to program the ISP PROM, the following steps must be taken:
• Using Table 14 set the Configuration Mode of the Virtex-II FPGA to Master Serial or Master SelectMap Mode.
• Use the Xilinx JTAG programmer utility (iMPACT) to load the design mcs file into the ISP PROM. You will need to associate the FPGA with either a dummy .bit file or a .bsd file to allow the JTAG programming software to pass data through the FPGA.
• Upon programming of the 18V04 ISP PROM, the on-board PROGn push button switch (SW2) is used to initiate the Virtex-II FPGA configuration.
December 2, 2002 26
3.2 Slave Serial Interface In this mode, an external source provides the configuration bit stream and the configuration clock (CCLK) to the Virtex-II FPGA. Refer to Table 14 for setting up the Configuration Mode pins.
3.3 Master SelectMap Interface In this mode, the following steps must be taken:
• Using Table 14 set the Configuration Mode of the Virtex-II FPGA to Master SelectMap Mode.
• Install the JP27 jumper • Use the Xilinx JTAG programmer utility to load the design mcs file into the ISP PROM.
You will need to associate the FPGA with either a dummy .bit file or a .bsd file to allow the JTAG programming software to pass data through the FPGA.
• Upon programming of the 18V04 ISP PROM, the on-board PROGn push button switch (SW2) is used to initiate the Virtex-II FPGA configuration.
3.4 Slave SelectMap Interface In this mode, an external source provides the configuration bit stream and the configuration clock (CCLK) to the Virtex-II FPGA. Refer to Table 14 for setting up the Configuration Mode pins.
December 2, 2002 27
Revision History
V1.0 Initial release 12/5/01 V1.1 Update 12/19/01
Section 2.1 heading changed Section 5 references to table 17 corrected to table 15 Figure 19 corrected
V1.2 Update 12/30/01
Figure 7 and table 6 corrected V1.3 Update 2/14/02
Figure 16-18 and table 10-11 corrected Table 15 corrected for PC Pull-up settings Removed P160 Module Documentation (Now as separate documents)
V1.4 Update 5/29/02 Corrected 24MHz/100MHz wording in section 2.4 Updated Memec Design logo
V3.0 Update 12/2/02
General updates, minor wording changes Updated section 2.3 to Micron DDR memory device Updated Figure 3 to Micron part number Updated Section 2.4 for user clock socket Updated Table 2 for user clock input Updated Section 2.11 for Parallel IV cable support Deleted Table 7 – JTAG Signals Added Figure 9 – Parallel IV Cable Update Table 15
December 2, 2002 28
Appendix A – Virtex-II System Board Schematics
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
VOLTAGE INPUT JACK REGULATION LED
VIN
3.3V 1X2Header
2.5V 1X2Header
1.5V 1X2Header
I = P/V = 3/(5-3.3) = 3/1.7 = 1765mA
TEST LOOP GROUND TEST LOOPS
LITTLE RUBBER FEET
Pmax = (Tj-Ta)/Rth = (125 - 50) / 25°C/W = 3W
I = P/V = 2.5/(5-2.5) = =2.5/2.5 = 1A
Pmax = (Tj-Ta)/Rth = (125 - 50) / 30°C/W = 2.5W
1X2Header
1.25V
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
1 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
POWER
Size Rev
Sheetof
Last Modified
Designer
HS2
VRAW
VIN
3.3V
2.5V
VIN
2.5V
1.5V
2.5V
VIN
3.3V
1.5V
VIN
3.3V
1.5V
3.3V
2.5V
3.3V
VRAW
1.5V
VIN
VRAW
3.3V
1.25V
VIN
JP4
1X2
12
JP7
1X2
12
JP10
1X2
12
U13TLV431ACDBV
35
4
NE10 Little Rubber Feet -Thick
JP6
1X2
1 2
C12.2u
JP13
1X2
12
R1750
5A
U1 TPS76633KTT
3
1
45
26GND
EN
OUTPUTFB/PG
INHS
JP3
Test Point Loop - Red
5A
U3 TPS75515KTT
3
1
45
26GND
EN
OUTPUTFB/PG
INHS
NE11 Little Rubber Feet -Thick
TP2
JP5
Test Point Loop - Black
JP1
PJ-002A-SMT
12
JP9
1X2
1 2
NE1 SHUNT-LO-CL
R2330
SW1
SPDT Slide 6A
1
2
3
NE12 Little Rubber Feet -Thick
NE3 SHUNT-LO-CL
JP14
Test Point Loop - Red
C62.2u
NE2 SHUNT-LO-CL
R1
R2
Q1
BCR133
3
1
2
JP8
Test Point Loop - Red
C79.1u
U2REG1117FA-2.5 DDPAK
1 2
3
4
VIN VOUT
GNDHS
C77.1u
NE9 Little Rubber Feet -Thick
R4330
R3130
+ C2150u
DS3LGT670-HK
DS1LGT670-HK
DS4
LGT670-HK
R65
10k
1%
JP12
1X2
1 2
+ C5150u
JP2
Test Point Loop - Black
DS2LGT670-HK
JP11
Test Point Loop - RedC32.2u
C42.2u
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
Slave SelectMAP
Boundary-scan
Slave Serial
1 2
1
Slave Serial
Master-serial
Indicates jumper installedIndicates jumper removed
Master-serial
20
Boundary-scan
Mode
CONFIGURATION BLOCK
0
BANK 0 - USER IO / EXPANSION BANK 1 - DDR / DDR CLOCK BANK 2 - EXPANSION BANK 3 - DDR
BANK 4 - EXPANSION / SELECTMAP BANK 6 - LVDS RECEIVEBANK 5 - LVDS CLOCKS / SELECTMAP / EXPANSION BANK 7 - LVDS TRANSMIT
POWER BLOCK
3
3Pull-ups
Yes
Yes
Yes
Yes
No
No
No
NoSlave SelectMAP
Master SelectMAPMaster SelectMAP
NoYes
clock feedback
P160 CLOCK TERMINATION
VALUES TBD
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
2 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
FPGA
Size Rev
Sheetof
Last Modified
Designer
PWRDWNM3
M1M2
M0
TDI.FPGATCK
TMSTDO.FPGA.to.TDO.PORT
FPGA.CCLKDONE
FPGA.BITSTREAM
PROGRAMn
FPGA.PWRDWN
LVDSIN1PLVDSIN1N
CLK.CAN1CLK.CAN2
DIP1DIP2DIP3DIP4
DIP8DIP7DIP6DIP5
MEM.CLKn
PUSH.USER.1
DISPLAY.1ADISPLAY.1BFPGA.RESETn
PUSH.USER.2
TXD
RXD
DISPLAY.2CDISPLAY.2B
DISPLAY.2A
DISPLAY.1C
DISPLAY.2FDISPLAY.1EDISPLAY.1FDISPLAY.1G
DISPLAY.1DDISPLAY.2G
DISPLAY.2ELED.USERDISPLAY.2D
LVDSINSTATCLKN
LVDSINCLKNLVDSINCLKP
LVDSINSTATCLKP
MEM.CLK
MEM.CLK
LVDSOUT16N LVDSOUT13N
LVDSOUT12P
LVDSOUT15N
LVDSOUT13P
LVDSOUT14N
LVDSOUT12NLVDSOUT14P
LVDSOUT16P
LVDSOUT15P LVDSOUTSTAT1P
LVDSOUTCLKN
LVDSOUTSTAT2P
LVDSOUTSTATCLKP
LVDSOUTSTAT1N
LVDSOUTSTAT2N
LVDSOUTSTATCLKNLVDSOUTCLKP
LVDSOUTCTRLPLVDSOUTCTRLN
LVDSOUT1PLVDSOUT1N
LVDSOUT2NLVDSOUT2P
LVDSOUT11PLVDSOUT11N
LVDSOUT3PLVDSOUT3N
LVDSOUT4PLVDSOUT4N
LVDSOUT5PLVDSOUT5N
LVDSOUT6NLVDSOUT6P
LVDSOUT7PLVDSOUT7N
LVDSOUT8NLVDSOUT8P
LVDSOUT9NLVDSOUT9P
LVDSOUT10NLVDSOUT10P
LVDSIN2PLVDSIN7NLVDSIN7P
LVDSIN3P
LVDSIN4N
LVDSINCTRLN
LVDSIN8N
LVDSIN4P
LVDSIN5N
LVDSIN2N
LVDSIN8P
LVDSINCTRLP
LVDSIN3N
LVDSIN6N
LVDSIN5P
LVDSIN6P
LVDSIN15N
LVDSINSTAT2PLVDSINSTAT2N
LVDSIN13P
LVDSIN14N
LVDSIN16P
LVDSINSTAT1P
LVDSIN13N
LVDSIN9N
LVDSIN15P
LVDSIN9P
LVDSIN16N
LVDSIN14P
LVDSINSTAT1N
LVDSIN12NLVDSIN12P
LVDSIN11NLVDSIN11P
LVDSIN10NLVDSIN10P
INITn
SM.CSnSM.RDWRn
SM.D5SM.D4
SM.D6SM.D7
SM.DOUT/BUSY
SM.D1SM.D2SM.D3
LIO.B39LIO.B40LIO.A33
LIO.A35
LIO.A37LIO.A39
RIO.A34
RIO.A30RIO.A32
RIO.A36
RIO.A40RIO.A38
RIO.B40RIO.A9
RIO.A23
RIO.A21
RIO.A13 RIO.A31
RIO.A33
RIO.A29 RIO.A35
RIO.A39RIO.A37
RIO.A27
RIO.A11
RIO.A19
RIO.A25
RIO.A15
RIO.A17
RIO.B18
RIO.B30
RIO.B28
RIO.A7
RIO.B24RIO.B20
RIO.B22 RIO.B34
RIO.B38
RIO.B36
RIO.B26
RIO.B32
RIO.A3
RIO.A1
RIO.A5RIO.B6RIO.B4
RIO.B8RIO.B10
RIO.B16
RIO.B2
RIO.B12
RIO.B14RIO.A18RIO.A20
RIO.A24RIO.A22
RIO.A26RIO.A28
RIO.A6
RIO.A12
RIO.A8
RIO.A2RIO.A4
RIO.A10
RIO.A16RIO.A14
MEM.D0MEM.D1
MEM.D3MEM.D4
MEM.CKE
MEM.LDM
MEM.RASnMEM.CSn
MEM.BS0
MEM.D6
MEM.D7
MEM.D5
MEM.WEn
MEM.A11MEM.A5
MEM.BS1MEM.A10/AP
MEM.A0
MEM.A3
MEM.A1
MEM.A2
MEM.D8
MEM.D10
MEM.D15
MEM.D11
MEM.D14
MEM.D9
MEM.D13
MEM.A9MEM.A8MEM.A7
MEM.A12
MEM.UDM
MEM.UDQSMEM.LDQS
MEM.A6
MEM.CASn
MEM.A4
MEM.D2
MEM.D12
LIO.A17
LIO.A13
LIO.B27
LIO.B25LIO.B24
LIO.B23
LIO.A27
LIO.B17
LIO.B8LIO.B9
LIO.A9LIO.B10
LIO.B11LIO.A11
LIO.B13LIO.B12
LIO.B14
LIO.A15LIO.B15
LIO.B16
LIO.B18
LIO.A19LIO.B19
LIO.A21LIO.B21
LIO.B20
LIO.A23LIO.B22
LIO.B26LIO.A25
LIO.B36
LIO.B35
LIO.B37
LIO.B34
LIO.B33
LIO.B30
LIO.B32
LIO.B28LIO.B29
LIO.B31
LIO.B38
LIO.A29LIO.A31
CLK.CAN3
LIO.A33LIO.A35
RIO.A18RIO.A20
RIO.B14RIO.B16
3.3V1.5V
VBANK0 2.5V 2.5V
VBANK4 VBANK.LVDS
3.3V
3.3V
VBANK5
3.3V
VBANK2
3.3V
VBANK.LVDS
1.25V 1.25V1.25V 1.25V
3.3V
VBANK4
VBANK0
R803.3k
R733.3k
R103.3k
JP15
1X2
1 2
NE6 SHUNT-LO-CL
C132.1u
Bank 1
*#* See Chart on Core Power Symbol.
U5B
A19B19
C18D18
A18B18
C17D17
A17B17
E16E17
C16
B12
E12D12
F12F13
D16
A16B16
F14E15
C15D15
A15B15
C14D14
A14B14
E13E14
C13D13
A13B13
C12
G14
G13
G12
F16
F15
IO_L01N_1IO_L01P_1
IO_L02N_1IO_L02P_1
IO_L03N_1/VRP_1IO_L03P_1/VRN_1
IO_L04N_1IO_L04P_1/VREF_1
IO_L05N_1IO_L05P_1
IO_L06N_1IO_L06P_1
*3*IO_L21N_1/VREF_1
IO_L94P_1/VREF_1
IO_L95N_1/GCLK1PIO_L95P_1/GCLK0S
IO_L96N_1/GCLK3PIO_L96P_1/GCLK2S
*2*IO_L21P_1
*2*IO_L22N_1*2*IO_L22P_1
*2*IO_L24N_1*2*IO_L24P_1
IO_L49N_1*1*IO_L49P_1*1*
IO_L51N_1/VREF_1*4*IO_L51P_1*1*
IO_L52N_1*1*IO_L52P_1*1*
IO_L54N_1*1*IO_L54P_1*1*
IO_L91N_1IO_L91P_1/VREF_1
IO_L92N_1IO_L92P_1
IO_L93N_1IO_L93P_1
IO_L94N_1
VC
CO
_1V
CC
O_1
VC
CO
_1V
CC
O_1
VC
CO
_1
J1
2X4
12
34
56
78
Bank 2
*#* See Chart on Core Power Symbol.
U5C
C21C22E18F18D21D22E19E20
E21E22F19F20F21F22G18H18
G19G20G21G22H19H20
H21H22J17J18J19J20J21J22
K17K18K19K20K21K22L17L18
L19L20L21L22
L16
K16
J16
H17
G17
IO_L01N_2IO_L01P_2IO_L02N_2/VRP_2IO_L02P_2/VRN_2IO_L03N_2IO_L03P_2/VREF_2IO_L04N_2IO_L04P_2
IO_L06N_2IO_L06P_2IO_L19N_2*2*IO_L19P_2*2*IO_L21N_2*2*IO_L21P_2/VREF_2*3*IO_L22N_2*2*IO_L22P_2*2*
IO_L24N_2*2*IO_L24P_2*2*IO_L43N_2IO_L43P_2IO_L45N_2IO_L45P_2/VREF_2
IO_L46N_2IO_L46P_2IO_L48N_2IO_L48P_2
*1*IO_L49N_2*1*IO_L49P_2*1*IO_L51N_2
*4*IO_L51P_2/VREF_2
*1*IO_L52N_2*1*IO_L52P_2*1*IO_L54N_2*1*IO_L54P_2
IO_L91N_2IO_L91P_2IO_L93N_2
IO_L93P_2/VREF_2
IO_L94N_2IO_L94P_2IO_L96N_2IO_L96P_2
VC
CO
_2V
CC
O_2
VC
CO
_2V
CC
O_2
VC
CO
_2
C131.1u
R723.3k
R703.3k
R813.3k
R763.3k
C130.1u
R83.3k Core Power
VCCINT = 1.5V
Notes:
1000 500 250
NCIOIO*1*
*2* IO NC NC
*3* VREF NC NC
NCVREFVREF*4*
U5J
A22A1
AB22AB1
AA21AA2Y20
Y3W19
W4P14P13
A21
AB
11A
A22
AA
1M
22L1 B
22B
1A
12
U17
U6
T16
T15
T8 T7 R16
R7
H16
H7
G16
G15
G8
G7
F17
F6
P12
P11
P10
P9
N14
N13
N12
N11
N10
N9
M14
M13
M12
M11
M10
M9
L14
L13
L12
L11
L10
L9 K14
K13
K12
K11
K10
K9
J14J13J12J11J10J9D19D4C20C3B21B2
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
VB
ATT
VC
CA
UX
VC
CA
UX
VC
CA
UX
VC
CA
UX
VC
CA
UX
VC
CA
UX
VC
CA
UX
VC
CA
UX
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
VC
CIN
TV
CC
INT
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GN
DG
ND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
R793.3k
R743.3k
Bank 5
*#* See Chart on Core Power Symbol.
U5F
Y4AA3
AB4AA4
Y5W5
AB5AA5
V7V6
Y6W6
AB6
U10
W11V11
AA11Y11
AA6
Y7W7
AB7AA7
U9V8
Y8W8
AB8AA8
Y9W9
AB9AA9
V10V9
Y10W10
AB10AA10
U11
U8
U7
T11
T10
T9
IO_L01N_5/RDWR_BIO_L01P_5/CS_B
IO_L02N_5/D6IO_L02P_5/D7
IO_L03N_5/D4/VRP_5IO_L03P_5/D5/VRN_5
IO_L04N_5IO_L04P_5/VREF_5
IO_L05N_5IO_L05P_5
IO_L06N_5IO_L06P_5
*2*IO_L19N_5
IO_L94P_5/VREF_5
IO_L95N_5/GCLK5SIO_L95P_5/GCLK4P
IO_L96N_5/GCLK7SIO_L96P_5/GCLK6P
*2*IO_L19P_5
*3*IO_L21N_5/VREF_5*2*IO_L21P_5
*2*IO_L22N_5*2*IO_L22P_5
*2*IO_L24N_5*2*IO_L24P_5
IO_L49N_5*1*IO_L49P_5*1*
IO_L51N_5/VREF_5*4*IO_L51P_5*1*
IO_L52N_5*1*IO_L52P_5*1*
IO_L54N_5*1*IO_L54P_5*1*
IO_L91N_5IO_L91P_5/VREF_5
IO_L92N_5IO_L92P_5
IO_L93N_5IO_L93P_5
IO_L94N_5
VC
CO
_5V
CC
O_5
VC
CO
_5V
CC
O_5
VC
CO
_5
Bank 3
*#* See Chart on Core Power Symbol.
U5D T17
R17
P16
N16
M16
W20AA20
Y22Y21
W22W21
V20V19
V22V21
T18U18
U20U19
U22U21
T20T19
T22T21
R18P17
R20R19
R22R21
P20P19
P22P21
N18P18
N20N19
N22N21
M17N17
M19M18
M21M20
VC
CO
_3V
CC
O_3
VC
CO
_3V
CC
O_3
VC
CO
_3
IO_L01N_3IO_L01P_3
IO_L02N_3/VRP_3IO_L02P_3/VRN_3
IO_L03N_3/VREF_3IO_L03P_3
IO_L04N_3IO_L04P_3
IO_L06N_3IO_L06P_3
*2*IO_L19N_3*2*IO_L19P_3
*3*IO_L21N_3/VREF_3*2*IO_L21P_3
*2*IO_L22N_3*2*IO_L22P_3
*2*IO_L24N_3*2*IO_L24P_3
IO_L43N_3IO_L43P_3
IO_L45N_3/VREF_3IO_L45P_3
IO_L46N_3IO_L46P_3
IO_L48N_3IO_L48P_3
IO_L49N_3*1*IO_L49P_3*1*
IO_L51N_3/VREF_3*4*IO_L51P_3*1*
IO_L52N_3*1*IO_L52P_3*1*
IO_L54N_3*1*IO_L54P_3*1*
IO_L91N_3IO_L91P_3
IO_L93N_3/VREF_3IO_L93P_3
IO_L94N_3IO_L94P_3
IO_L96N_3IO_L96P_3
Bank 0
*#* See Chart on Core Power Symbol.
U5A
B4A4C4C5B5A5D6C6
B6A6E7E8D7C7B7
D11C11B11A11
A7D8C8B8A8E9F9
D9C9B9A9E10F10D10C10
B10A10E11F11
F7F8G9
G10
G11
IO_L01N_0IO_L01P_0IO_L02N_0IO_L02P_0IO_L03N_0/VRP_0IO_L03P_0/VRN_0IO_L04N_0/VREF_0IO_L04P_0
IO_L05N_0IO_L05P_0IO_L06N_0IO_L06P_0IO_L21N_0*2*IO_L21P_0/VREF_0*3*IO_L22N_0*2*
IO_L95N_0/GCLK7PIO_L95P_0/GCLK6SIO_L96N_0/GCLK5PIO_L96P_0/GCLK4S
*2*IO_L22P_0*2*IO_L24N_0*2*IO_L24P_0*1*IO_L49N_0*1*IO_L49P_0*1*IO_L51N_0
*4*IO_L51P_0/VREF_0
*1*IO_L52N_0*1*IO_L52P_0*1*IO_L54N_0*1*IO_L54P_0
IO_L91N_0/VREF_0IO_L91P_0IO_L92N_0IO_L92P_0
IO_L93N_0IO_L93P_0
IO_L94N_0/VREF_0IO_L94P_0
VC
CO
_0V
CC
O_0
VC
CO
_0V
CC
O_0
VC
CO
_0
Bank 4
*#* See Chart on Core Power Symbol.
U5E U16
U15
T14
T13
T12
AB19AA19
V18V17
W18Y18
AA18AB18
W17Y17
AA17AB17
V16V15
W16
W12Y12
AA12AB12
Y16AA16AB16W15Y15AA15AB15
U14V14W14Y14AA14AB14U13V13
W13Y13AA13AB13U12V12
VC
CO
_4V
CC
O_4
VC
CO
_4V
CC
O_4
VC
CO
_4
IO_L01N_4/DOUTIO_L01P_4/INIT_BIO_L02N_4/D0IO_L02P_4/D1IO_L03N_4/D2/VRP_4IO_L03P_4/D3/VRN_4IO_L04N_4/VREF_4IO_L04P_4
IO_L05N_4IO_L05P_4IO_L06N_4IO_L06P_4IO_L19N_4*2*IO_L19P_4*2*IO_L21N_4*2*
IO_L95N_4/GCLK3SIO_L95P_4/GCLK2PIO_L96N_4/GCLK1SIO_L96P_4/GCLK0P
*3*IO_L21P_4/VREF_4*2*IO_L22N_4*2*IO_L22P_4*2*IO_L24N_4*2*IO_L24P_4*1*IO_L49N_4*1*IO_L49P_4
*1*IO_L51N_4*4*IO_L51P_4/VREF_4
*1*IO_L52N_4*1*IO_L52P_4*1*IO_L54N_4*1*IO_L54P_4
IO_L91N_4/VREF_4IO_L91P_4
IO_L92N_4IO_L92P_4IO_L93N_4IO_L93P_4
IO_L94N_4/VREF_4IO_L94P_4
R73301%
C129.1u
R773.3k
R113.3k
R753.3k
R93.3k
C134.1u
R713.3k
C133.1u
ConfigurationU5I
Y19AB20
D5A3
B3
AB2W3
AB3
A2
AB21A20
C19D3
D20B20
CCLKDONE
DXNDXP
HSWAP_EN
M0M1M2
PROG_B
PWRDWN_BRSVD
TCKTDITDOTMS
Bank 7
*#* See Chart on Core Power Symbol.
U5H
H4H3H2H1
J4J3J2J1J5K5K6L6
K4K3K2K1L5L4L3L2
L7 K7
J7 H6
G6
J6H5
G1
E6E5C2C1D2D1
E4E3E2E1F5G5F4F3
F2F1G4G3G2
IO_L46N_7IO_L46P_7IO_L48N_7IO_L48P_7
IO_L49N_7*1*IO_L49P_7*1*IO_L51N_7*1*IO_L51P_7/VREF_7*4*IO_L52N_7*1*IO_L52P_7*1*IO_L54N_7*1*IO_L54P_7*1*
IO_L91N_7IO_L91P_7IO_L93N_7IO_L93P_7/VREF_7IO_L94N_7IO_L94P_7IO_L96N_7IO_L96P_7
VC
CO
_7V
CC
O_7
VC
CO
_7V
CC
O_7
VC
CO
_7
IO_L45P_7/VREF_7IO_L45N_7
IO_L43P_7
IO_L01N_7IO_L01P_7
IO_L02N_7/VRP_7IO_L02P_7/VRN_7
IO_L03N_7IO_L03P_7/VREF_7
IO_L04N_7IO_L04P_7IO_L06N_7IO_L06P_7
*2*IO_L19N_7*2*IO_L19P_7*2*IO_L21N_7
*3*IO_L21P_7/VREF_7
*2*IO_L22N_7*2*IO_L22P_7*2*IO_L24N_7*2*IO_L24P_7
IO_L43N_7
R123.3k1%
NE7 SHUNT-LO-CL
Bank 6
*#* See Chart on Core Power Symbol.
U5G
U5V5
Y1Y2
V3V4
W1W2
U3U4
V1V2
U1U2
R5T5
T3T4
T1T2
R3R4
P5P6
P3P4
P1P2
N5N6
N3N4
N1N2
M5M6
M3M4
M1M2
T6 R6
P7
N7
M7
R2R1IO_L01N_6
IO_L01P_6
IO_L02N_6/VRP_6IO_L02P_6/VRN_6
IO_L03N_6/VREF_6IO_L03P_6
IO_L04N_6IO_L04P_6
IO_L06N_6IO_L06P_6
IO_L19N_6*2*IO_L19P_6*2*
IO_L21N_6/VREF_6*3*IO_L21P_6*2*
IO_L22N_6*2*IO_L22P_6*2*
IO_L24N_6*2*IO_L24P_6*2*
IO_L43N_6IO_L43P_6
IO_L45N_6/VREF_6IO_L45P_6
IO_L48N_6IO_L48P_6
*1*IO_L49N_6*1*IO_L49P_6
*4*IO_L51N_6/VREF_6*1*IO_L51P_6
*1*IO_L52N_6*1*IO_L52P_6
*1*IO_L54N_6*1*IO_L54P_6
IO_L91N_6IO_L91P_6
IO_L93N_6/VREF_6IO_L93P_6
IO_L94N_6IO_L94P_6
IO_L96N_6IO_L96P_6
VC
CO
_6V
CC
O_6
VC
CO
_6V
CC
O_6
VC
CO
_6
IO_L46P_6IO_L46N_6
NE4 SHUNT-LO-CL
R783.3k
NE5 SHUNT-LO-CL
JP16
1X2
12
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
JTAG
PROGRAM PUSHBUTTONXC18 PROM
JTAG PORT
FPGA POWER SELECT
DONE
PROGRAMMING DONE LED
CLOCKS
FPGA RESET CIRCUITSELECTMAP PORT
PROM JTAG BYPASS
TDI
TDO
JTAG CHAIN DIAGRAM
FPGAPROM
TDI.PORT.to.TDI.PROM
TDO.FPGA.to.TDO.PORT
TDO
TDI
PIV PORT
TDI.PROM
PROM NOT IN CHAIN
JP22
TDI.FPGA
PROM IN CHAIN
TDO.PROM
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
3 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
FPGA PERIPHERALS
Size Rev
Sheetof
Last Modified
Designer
TDI.PORT.to.TDI.PROM
TCKTMS
TDI.PROM
DONE
TDO.PROM
TCK
FPGA.BITSTREAM
PROGRAMn
TDO.PROM
CLK.CAN1
PROGRAMn
FPGA.CCLK
DONE
FPGA.BITSTREAM
CLK.CAN2
PUSH.RESETn
PUSH.RESETn
TDO.FPGA.to.TDO.PORTTDI.PORT.to.TDI.PROMTMS
FPGA.RESETn
INITn
SM.D1
SM.D3
SM.D7SM.D6
SM.D2
SM.D5SM.D4
SM.D2SM.D3
SM.D1
SM.D5SM.D6
SM.D4
SM.D7
INITn
SM.DOUT/BUSY
DONESM.CSn
FPGA.CCLK
PROGRAMn
SM.RDWRn
CLK.CAN3
TDI.PORT.to.TDI.PROM
TMSTCK
TDI.PROM
TDO.FPGA.to.TDO.PORT
TDI.FPGA
3.3V
3.3V
3.3V
3.3V
3.3V 3.3V
VBANK4
VBANK5
3.3V 2.5V
3.3V
3.3V
1.5V
3.3V
1.5V
VBANK.LVDS
1.5V
VBANK2
VBANK0
VBANK0
3.3V
3.3V
2.5V
2.5V2.5V
3.3V
3.3V
3.3V
NE16 SHUNT-LO-CL
JP20
1X31
2
3
SW2
Tl1105SP
A B
A' B'
J3
SelectMAP RA
1 23 45 67 89 10
11 1213 1415 16
CSn DIN/D0DONE D1CCLK D2INITn D3PROGRAMn D4NC D5RDWRn D6DOUT/BUSY D7
U11
TPS3125
32
51
4RESETGND
VDDRESET
MR
C124.01u
06036
C127.1u
C80.1u
Y4
100MHz
1
2 3
4EN
GND OUT
VCC
C12
.1u
SW3
Tl1105SP
A B
A' B'
JTAG SSerJP29
Parallel IV RA
1 23 45 67 89 10
11 1213 14
GND VREF VREFGND TMS PROGGND TCK CCLKGND TDO DONEGND TDI DINGND NC NCGND NC INIT
JP23
1X2
12
R1
R2
Q3BCR133
3
1
2
NE17 SHUNT-LO-CL
JP22 1X4 RA
12 3
4
JP18
1X31
2
3
J2
JTAG7 RA
12
4567
3
VCCGND
TCKTDO
TDITMS
NC
C11
.1u
R693.3k
NE8 SHUNT-LO-CL
C125.01u
06036
NE13 SHUNT-LO-CL
NE19 SHUNT-LO-CL
R4310k1%
NE18 SHUNT-LO-CL
R133.3k
R15
0 1%
C128.1u
DS5
LGT670-HK
Y3
24MHz
1
2 3
4EN
GND OUT
VCC
halffull
Y5
Clock Can
1 78
41114
EN
AB
LE
GN
DO
UT
GN
DO
UT
VC
C
NE14 SHUNT-LO-CL
JP19
1X31
2
3
R163.3k1%
JP26
1X31
2
3
C123.1u
R1
R2
Q2
BCR133
3
1
2
JP27
1X2 RA
12
R14330
NE15 SHUNT-LO-CL
JP21
1X31
2
3
R6010k1%
C126.01u
06036
JP24
1X2
12
JP28
1X31
2
3
144
1112 22
23
3433
U6
XC18V04VQ44C
40
42
43
357
913
1415
18
1921
25
27
2931
8
10
28 416
17 35 3816 26 36
D0/DATA
D2
CLK
TDITMSTCK
D4OE/RESET
D6CE
GN
D
D7CEO
D5
D3
D1TDO
VC
CO
CF
GN
DG
ND
GN
D
VC
CV
CC
VC
C
VC
CO
VC
CO
VC
CO
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
4 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
DDR MEMORY
Size Rev
Sheetof
Last Modified
Designer
MEM.LDM
MEM.A12
MEM.A0
MEM.UDQS
MEM.WEn
MEM.A7
MEM.A5
MEM.BS1
MEM.A3
MEM.LDQS
MEM.A4
MEM.UDM
MEM.CSn
MEM.A9
MEM.RASnMEM.CASn
MEM.BS0
MEM.A6
MEM.A1MEM.A2
MEM.A10/AP
MEM.A8
MEM.A11
MEM.D3
MEM.CKE
MEM.D1
MEM.D14
MEM.CLKn
MEM.D9
MEM.D5
MEM.D0
MEM.D6
MEM.D13
MEM.CLK
MEM.D8MEM.D7
MEM.D4
MEM.D10
MEM.D2
MEM.D11
MEM.D15
MEM.D12
2.5V 2.5V 1.25V
U8
TC59WM815BFT
51
14
20
46
4445
48341
47
16
245781011135456575960626365
29303132353637383940284142
5043251917
53
6 12 52 58 6466
18 33 3 9 15 55 61 49
212223
2627
24
UDQS
NC
LDM
CLK
CKECLK
GN
DG
ND
VD
D
UDM
LDQS
D0D1D2D3D4D5D6D7D8D9
D10D11D12D13D14D15
A0A1A2A3A4A5A6A7A8A9A10/APA11A12
NCNCNCNCNC
NC
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
DIO
GN
D
VD
DV
DD
VD
DIO
VD
DIO
VD
DIO
VD
DIO
VD
DIO
VR
EF
WECASRAS
BS0BS1
CS
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
LVDS TRANSMIT
LVDS RECEIVE
No transmit termination required forVirtex-II
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
5 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
LVDS
Size Rev
Sheetof
Last Modified
Designer
LVDSOUT4P
LVDSOUT1P
LVDSOUT3PLVDSOUT4N
LVDSOUT2PLVDSOUT3NLVDSOUT2NLVDSOUT1N
LVDSOUT7P LVDSOUT7N
LVDSOUT5NLVDSOUT5PLVDSOUT6P LVDSOUT6N
LVDSOUT8P LVDSOUT8N
LVDSOUT11P LVDSOUT11N
LVDSOUT9NLVDSOUT9PLVDSOUT10P LVDSOUT10N
LVDSOUT12P LVDSOUT12N
LVDSOUT15P LVDSOUT15N
LVDSOUT13NLVDSOUT13PLVDSOUT14P LVDSOUT14N
LVDSOUT16P LVDSOUT16N
LVDSINSTAT2P
LVDSINSTAT2N LVDSINSTAT2N
LVDSINSTAT2P
LVDSOUTCLKP LVDSOUTCLKN
LVDSOUTSTAT1P LVDSOUTSTAT1N
LVDSIN3N
LVDSIN4N
LVDSIN13N
LVDSIN11P
LVDSIN1N
LVDSIN5P
LVDSIN6N
LVDSIN8N
LVDSIN10N
LVDSIN9PLVDSIN1P
LVDSIN1N
LVDSIN16P
LVDSIN13P
LVDSIN2P
LVDSIN1P
LVDSIN9N
LVDSIN14N
LVDSIN9N
LVDSIN7P
LVDSIN2N
LVDSIN7P
LVDSIN14P
LVDSIN2P
LVDSIN5P
LVDSIN12P
LVDSIN5N
LVDSIN11P
LVDSIN16N
LVDSIN5N
LVDSIN10P
LVDSIN9P
LVDSIN16N
LVDSIN6P
LVDSIN8P
LVDSIN3N LVDSIN11N
LVDSIN6N
LVDSIN10N
LVDSIN15NLVDSIN7N
LVDSIN13P
LVDSIN8P
LVDSIN7N LVDSIN15N
LVDSIN12N
LVDSIN4P
LVDSIN14N
LVDSIN16P
LVDSIN13N
LVDSIN4N
LVDSIN15P
LVDSIN11N
LVDSIN4P
LVDSIN3P
LVDSIN10P
LVDSIN3P
LVDSIN15P
LVDSIN2N
LVDSIN12N
LVDSIN6P
LVDSIN8N
LVDSIN14P
LVDSIN12P
LVDSINCTRLN
LVDSINCTRLP
LVDSINCTRLN
LVDSINCTRLP
LVDSOUTSTATCLKP LVDSOUTSTATCLKN
LVDSOUTCTRLP LVDSOUTCTRLNLVDSOUTSTAT2P LVDSOUTSTAT2N
LVDSINSTAT1P
LVDSINSTAT1NLVDSINSTAT1N
LVDSINSTAT1P
LVDSINCLKP
LVDSINCLKNLVDSINCLKN
LVDSINCLKP LVDSINSTATCLKP
LVDSINSTATCLKNLVDSINSTATCLKN
LVDSINSTATCLKP
LVDSINSTATCLKN
LVDSINCLKP
LVDSINSTATCLKP
LVDSINCLKN
LVDSIN5P
LVDSIN4P
LVDSIN1P
LVDSIN6P
LVDSIN8P
LVDSIN13P
LVDSIN16P
LVDSIN10P
LVDSIN15P
LVDSIN12P
LVDSIN2P
LVDSIN9P
LVDSIN14P
LVDSIN7P
LVDSIN11P
LVDSIN3P
LVDSIN11N
LVDSIN2N
LVDSIN15N
LVDSIN5N
LVDSIN1N
LVDSIN14NLVDSIN13N
LVDSIN6N
LVDSIN8N
LVDSIN10N
LVDSIN12N
LVDSIN9N
LVDSIN7N
LVDSIN3NLVDSIN4N
LVDSIN16N
LVDSINCTRLPLVDSINSTAT2P LVDSINSTAT2N
LVDSINSTAT1NLVDSINSTAT1P
LVDSINCTRLN
R281001%
R241001%
J4
2X20
2345678910
11121314151617181920
1
2122232425262728293031323334353637383940
R201001%
R641001%
R291001%
R261001%
J7
2X7
1 23 45 67 89 10
11 1213 14
R181001%
R251001%
R681001%
J6
2X20
2345678910
11121314151617181920
1
2122232425262728293031323334353637383940
R321001%
R221001%
R301001%
R311001%
R191001%
R211001%
R331001%
R231001%
R661001%
R171001%
R271001%
R671001%
J8
2X7
1234567891011121314
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
P160 SOCKET
T2E 7S8
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
6 9
CSuite 540, 1212 31st Ave. NECalgary, AlbertaCanada
3
Jim Elliott
P160 SOCKET
Size Rev
Sheetof
Last Modified
Designer
RIO.A1RIO.A2RIO.A3RIO.A4
RIO.A7
RIO.A5RIO.A6
RIO.A8
RIO.A13
RIO.A11
RIO.A9RIO.A10
RIO.A12
RIO.A16
RIO.A14RIO.A15
RIO.A21
RIO.A19
RIO.A17RIO.A18
RIO.A20
RIO.A24
RIO.A22RIO.A23
RIO.A29
RIO.A27
RIO.A25RIO.A26
RIO.A28
RIO.A32
RIO.A30RIO.A31
RIO.A37
RIO.A35
RIO.A33RIO.A34
RIO.A36
RIO.A40
RIO.A38RIO.A39
RIO.B2
RIO.B4
RIO.B6
RIO.B8
RIO.B14
RIO.B12
RIO.B16
RIO.B10
RIO.B30
RIO.B28
RIO.B22
RIO.B26
RIO.B20
RIO.B24
RIO.B32
RIO.B18
RIO.B38
RIO.B36
RIO.B40
RIO.B34
LIO.B30
LIO.B27
LIO.A33
LIO.A31
LIO.B28
LIO.A25
LIO.A21
LIO.B15
LIO.B25
LIO.B17
LIO.B26
LIO.B36
LIO.A29
LIO.B37
LIO.A23
LIO.A19
LIO.B35
LIO.B20
LIO.B16
LIO.B31
LIO.B29
LIO.B19
LIO.A17
LIO.A37
LIO.B32
LIO.B21
LIO.B33
LIO.B40LIO.A39
LIO.B24LIO.B23LIO.B22
LIO.B38
LIO.A35
LIO.B18
LIO.B13LIO.B12
LIO.B39
LIO.B34
LIO.A27
LIO.B14
LIO.B11LIO.B10
LIO.B8LIO.B9
LIO.A15
LIO.A13
LIO.A11
LIO.A9
3.3V2.5V VINVIN 3.3V 2.5V
JX2 P160 Right Header MB
B1A1B2A2B3A3B4A4B5A5B6A6B7A7B8A8B9A9B10A10B11A11B12A12B13A13B14A14B15A15B16A16B17A17B18A18B19A19B20A20B21A21B22A22B23A23B24A24B25A25B26A26B27A27B28A28B29A29B30A30B31A31B32A32B33A33B34A34B35A35B36A36B37A37B38A38B39A39B40A40
GNDIOIOIO
VINIOIOIO
GNDIOIOIO
3.3VIOIOIO
GNDIOIOIO
2.5VIOIOIO
GNDIOIOIO
VINIOIOIO
GNDIOIOIO
3.3VIOIOIO
GNDIOIOIO
2.5VIOIOIO
GNDIOIOIO
VINIOIOIO
GNDIOIOIO
3.3VIOIOIO
GNDIOIOIO
2.5VIOIOIO
GNDIOIOIO
VINIOIOIO
JX1 P160 Left Header MB
B1A1B2A2B3A3B4A4B5A5B6A6B7A7B8A8B9A9B10A10B11A11B12A12B13A13B14A14B15A15B16A16B17A17B18A18B19A19B20A20B21A21B22A22B23A23B24A24B25A25B26B27A27B28A28B29A29B30A30B31A31B32A32B33A33B34B35A35B36A36B37A37B38A38B39A39B40A40
A34
A26
DINTCKDOUTGNDCCLKTMSDONEVININITnTDI
PROGRAMnGNDNCTDOIO3.3VIOIOIOGNDIOIOIO2.5VIOIOIOGNDIOIOIOVINIOIOIOGNDIOIOIO3.3VIOIOIOGNDIOIOIO2.5VIOIOIOIOIOIOVINIOIOIOGNDIOIOIO3.3VIOIOIOIOIOIO2.5VIOIOIOGNDIOIOIOVIN
GND
GND
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
SERIAL PORT
PUSHBUTTONS
DIP SWITCH
LEDs SEVEN SEGMENT DISPLAYS
Rupper = (3.3V - 2) / 5mA = 260 ohmsRlower = (2.5V - 2) / 5mA = 100 ohmsLet R = 130 ohms
Resistor Value Calculations
a
b
c
d
e
f
g
USE STANDARD STRAIGHT-THRUCABLE WHEN CONNECTING TO A PC
T2E 7S8
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
7 9
CSuite 540, 1212 31st Ave. NECalgary, AlbertaCanada
3
Jim Elliott
USER IO
Size Rev
Sheetof
Last Modified
Designer
PUSH.USER.1
PUSH.USER.2
TXDRXD
LED.USER
DISPLAY.1A
DISPLAY.1EDISPLAY.1F
DISPLAY.1C
DISPLAY.2C
DISPLAY.2A
DISPLAY.1D
DISPLAY.2F
DISPLAY.1G
DISPLAY.1B
DISPLAY.2G
DISPLAY.2E
DISPLAY.2B
DISPLAY.2D
DIP1
DIP5DIP6
DIP8DIP7
DIP4
DIP2DIP3
VBANK0
3.3V
3.3V
VBANK0
VBANK0
R561301%
C13.1u
R373.3k1%
R393.3k1%
R343.3k1%
SW6
Tl1105SP
A B
A' B'
R581301%
R481301%
R451301%
ABCDEFGDP
CC
DD1
RED CC
1
109854237
6
R591301%
JDR1
DB9 RA
5
9
4
8
3
7
2
6
1
GND
RI
DTR
CTS
TD
RTS
RD
DSR
DCD
R471301%
R521301%
C17.1u
U10
MAX3221
12345678
161514131211109
ENC1+V+C1-C2+C2-V-RIN
FORCEOFFVCCGND
DOUTFORCEON
DININVALID
ROUT
R533.3k1%
C14.1uR40
3.3k1%
R353.3k1%
R413.3k1%
R491301%
R501301%
C15.1u
SW4
SWDIP08
12345678 9
10111213141516
SW5
Tl1105SP
A B
A' B'
R541301%
R511301%
ABCDEFGDP
CC
DD2
RED CC
1
109854237
6
C16.1u
DS7
LGT670-HK
R461301%
R363.3k1%
R383.3k1%
R551301%
R441301%
R423.3k1%
R571301%
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
FPGA IO DecouplingFPGA Core Decoupling
FPGA AUX/Battery Decoupling
Memory Decoupling
FPGA Voltage Reference Decoupling
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
8 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
DECOUPLING
Size Rev
Sheetof
Last Modified
Designer
VBANK5
VBANK2
VBANK0VBANK0
2.5V
1.25V
VBANK4
VBANK5
VBANK4
1.5V
VBANK2
1.5V
1.25V
1.5V
2.5V
1.5V
2.5V
2.5V
2.5V
VBANK5
3.3V
2.5V
VBANK.LVDS
1.5V
3.3V
1.5V
2.5V
3.3V
VBANK5
VBANK0VBANK0
1.5V1.5V
2.5V
1.25V
2.5V
VBANK4
VBANK.LVDS
VBANK4
1.5V
2.5V
3.3V
1.25V
2.5V
VBANK.LVDS
VBANK0
1.5V
3.3V
VBANK.LVDS
2.5V
VBANK.LVDS
2.5V
VBANK.LVDS
3.3V
1.25V
2.5V
VBANK2
2.5V
1.5V1.5V
1.5V
1.25V
VBANK5
3.3V
2.5V
VBANK2
1.5V VBANK.LVDS
2.5V
3.3V
VBANK2
VBANK4
2.5V
VBANK.LVDSVBANK.LVDS
1.5V
VBANK.LVDS
1.5V
C3822n
+C101100u6.3
C3522n
C46.1u
C18
22nC8722n
C112
22n
C992.2u
120610
+ C86100u6.3
C59.22u
04026
C48.1u
C4122n
C6522n
C942.2u
120610
C84.22u
04026
C60
22n
C47.1u
C53.1u
C49.1u
C5722n
C2322n
C97.22u
04026
C29
22n
C54.1u
C106.22u
04026
+ C102100u6.3
C10422n
C5122n
+ C96100u6.3
C93.22u
04026
C5222n
C56.1u
C24.22u
04026
C2222n
C1172.2u
120610
+ C114100u6.3
C1102.2u
120610
C31
22n
C3422n
C882.2u
120610
C61
22n
C9122n
C5822n
C852.2u
120610
C4022n
C30
22n
C21
22n
C81.22u
04026
C42.22u
04026
C116.22u
04026
C1082.2u
120610
C55.1u
C32
22n
C92.22u
04026
C3922n
C5022n
C20
22n
C67.22u
04026
C892.2u
120610
C6622n
C1132.2u
120610
C952.2u
120610
C1072.2u
120610
C62
22n
C82.22u
04026
C105.22u
04026
C83.22u
04026
C115.22u
04026
C64.1u
+ C118100u6.3
+ C111100u6.3
C19
22n
C98.22u
04026
C10322n
C9022n
+ C109100u6.3
+ C100100u6.3
C3322n
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
H H
G G
F F
E E
D D
C C
B B
A A
REV2 REV3
CHANGED 1.5 DUAL REGULATORS TO SINGLE DEVICE
ADDED DECOUPLING CAPACITORS TO OSCILLATORS
INCREASED FPGA DECOUPLING
ADDED OSCILLATOR SOCKET
ADDED PARALLEL IV PORT
ADDED P160 CLOCK TERMINATION
CHANGED 3.3V REGULATORS PER TI GUIDE
<OrgAddr4>
2V1000 MICROBLAZE BOARD
MemecBoardFriday, October 11, 2002
9 9
C<OrgAddr1><OrgAddr2><OrgAddr3>
3
Jim Elliott
HISTORY
Size Rev
Sheetof
Last Modified
Designer