Verilog can be used to describe storage elements and sequential circuits as well.
So far continuous assignment statements are used in a behavioral description.
A continuous assignment in Verilog is a statement that executes every time the right hand side of the an assignment changes.
(executes here means executing in simulation; Hardware counterpart already simulates that behavior)
Continuous assignment The continuous assignment is used to assign a value onto
a wire in a module. It is the normal assignment outside of always or initial blocks.
Continuous assignment is done with an explicit assign statement or by assigning a value to a wire during its declaration.
Note that continuous assignment statements are concurrent and are continuously executed during simulation. The order of assign statements does not matter. Any change in any of the right-hand-side inputs will immediately change a left-hand-side output.
Process
A process can be viewed as a replacement for continuous assignment statement hat permits considerably greater descriptive power.
Multiple processes may execute concurrently and a process may execute concurrently with continuous assignment statements. i.e. we can have a continuous statement X
outside of the procedure Y executing concurrently with Y
Process
Within a process, procedural assignment statements, which are not continuous assignments, are used.
Because of this, the assigned values need to be retained over time. This can be achieved by using reg type (register type) rather than wire type.
Procedural Assignments
Procedural assignments are assignment statements used within Verilog procedures ( always and initial blocks). Only reg variables and integers (and their bit/part-selects and concatenations) can be placed left of the “=” in procedures.
The right hand side of the assignment is an expression which may use any of the operator types we have seen earlier.
Process
There are two basic types of processes initial process
Used only in simulations executes only once, beginning at time t = 0.
always process Used in simulations and synthesis Also executes at time t=0; but also executed
repeatedly afterwards.
Timing control is done by events of delay
Timing control # integer
Can be used to specify a delay Example: # 100 means wait 100 simulation
time units. @ event
Can be used to wait for an event, and then execute
@ expressionThe occurrence of event causes the process
to execute.
Process
beginprocedural assignment statements; ……
end
assignment statements can be blocking or non-blocking.
Assignment statements
Blocking assignment Uses = Next statement has to be executed after the current
statement completed (sequential execution of statements)
Non-Blocking assignment Uses <= Next statement executes at the same time with the
current statement. (parallel) execution of statements)
Assignment statements
beginB = A; C = B;
end
A = 1; B = 3; C = 7
Process Execution
A = 1; B = 1; C = 1
beginB <= A; C <= B;
end
A = 1; B = 3; C = 7
Process Execution
A = 1; B = 1; C = 3
Example Run Example Run
Example Process Example Process
Assignment statements
beginC = B; B = A;
end
A = 1; B = 3; C = 7
Process Execution
A = 1; B = 1; C = 3
BeginC <= B;B <= A;
end
A = 1; B = 3; C = 7
Process Execution
A = 1; B = 1; C = 3
Example Run Example Run
Example Process Example Process
Order matters! Order does not matter!
Process
With the @always keyword, you can make a process like a continuous statement
module test (z, x, y) output z; input x, y;
assign z = x + y;
endmodule
module test (z, x, y); output z; input x, y; reg z; always @ (x, y) begin
z = x + y; endendmodule;
Verilog Code be be written for:
Simulation Create the corresponding circuit (logic
diagram, etc.) Synthesis
Create a simulation program
Some features are not available for synthesis. For example: wait, initial, etc.
Sequential Design
In sequential design, that includes flip-flops, registers, etc., we will usually use non-blocking assignments.
Verilog code: D flip flop
module dff_v (CLK, RESET, D, Q)input CLK, RESET, D; output Q; reg Q;
always @ (posedge CLK or posedge RESET)begin
if (RESET)Q <= 0;
elseQ <= D;
end
process
event control statement
Verilog In the body of a process, additional Verilog conditional
statements can appear. For example: if-else
if (condition)begin
procedural statementsend
else if (condition)begin
procedural statementsend
else begin
procedural statementsend
Verilog for Sequence Recognizer
1/00/0
0/0
0/0
1/1
A B1/0
C1/0
D0/0
Present State
Next Statex = 0 x = 1
Output x = 0 x = 1
0 0 0 0 0 1 0 0
0 1 0 0 1 0 0 0
1 0 1 1 1 0 0 0
1 1 0 0 0 1 0 1
Verilog for Sequence Recognizer
Next State
Determination Logic
DFF
DFF
Circuit State
OutputLogicInput
(X)
Output(Z)
CLK
RESET
Verilog for Sequence Recognizer
module seq_rec_v (CLK, RESET, X, Z)input CLK, RESET, Xoutput Z; reg [1:0] state, next_state;parameter A = 2’b00, B = 2’b01, C = 2’b10, D = 2’b11; reg Z;
Verilog for Sequence Recognizer
always @ (posedge CLK or posedge RESET)begin
if (RESET == 1)state <= A;
else state <= next_state;
end
// implements state storage
Verilog for Sequence Recognizer
always @ (X or state)begin
case (state)A: if (X == 1)
next_sate <= B; else
next_state <= A; B: if (X) next_state <= C;
else next_state <= A; C: if (X) next_state <= C;
else next_state <= D; D: if (X) next_state <= B;
else next_state <= A; endcase
end
// next state functionality implementation
Verilog for Sequence Recognizer
always @ (X or state)begin
case (state)A: Z <= 0; B: Z <= 0; C: X <= 0; D: Z <= X ? 1 : 0;
endcaseend
// output functionality implementation
endmodule