Virtual Memory & Paging Algorithms
Chapter 4
Tuesday, March 26, 2007
Today’s Schedule Memory Management - Chapter 4
Managing Page Tables Multi-Level Page Tables Inverted Page Tables
Page Replacement Algorithms NRU FIFO Second Chance Clock
Objectives
You will be able to describe: Trade-offs in page table implementation for
speed and space TLB Multi-level page tables Inverted page tables
The difference between page replacement policies first-in first-out not-recently-used page clock and second chance
Paging Overview
Paging Hardware With TLB
A TLB to speed up paging
TLBs – Translation Lookaside Buffers
An Item is missing in the TLB entry? Why?
Page Table Entry
Typical page table entry
Address Translation Scheme Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which contains base address of each page in physical memory
Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit
For given logical address space 2m and page size 2n
page number page offset
p d
m - n n
How Big is a Page Table?
For 32-bit Address Space?? For 64-bit Address Space??
Multi-Level Page Tables
32 bit address with 2 page table fields Two-level page tables – save space!
Second-level page tables
Top-level page table
Inverted Page Table One entry for each real page of memory Entry consists of the virtual address of the page
stored in that real memory location, with information about the process that owns that page
Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs
Use hash table to limit the search to one — or at most a few — page-table entries
Inverted Page Tables
Comparison of a traditional page table with an inverted page table
Allocating Free Frames
Before allocation After allocation
Page Replacement Algorithms Page fault forces choice
which page must be removedmake room for incoming page
Modified page must first be savedunmodified just overwritten
Better not to choose an often used pagewill probably need to be brought back in
soon
Optimal Page Replacement Algorithm
Replace page needed at the farthest point in futureOptimal but unrealizable
Estimate by … logging page use on previous runs of processalthough this is impractical
Not Recently Used Page Replacement
Each page has Reference bit, Modified bit bits are set when page is referenced,
modified Pages are classified
Class 0 - not referenced, not modified Class 1 - not referenced, modified Class 2 - referenced, not modified Class 3 - referenced, modified
NRU removes page at random from lowest numbered non empty class
FIFO Page Replacement Algorithm Maintain a linked list of all pages
in order they came into memory
Page at beginning of list replaced
Disadvantagepage in memory the longest may be often used
Ex. FIFO Page Replacement
Working of a FIFO algorithm for a job with four pages (A, B, C, D) as it’s processed by a system with only two available page frames
Second Chance Page Replacement
Operation of a second chance pages sorted in FIFO order Page list if fault occurs at time 20, A has R bit set
(numbers above pages are loading times)
The Clock Page Replacement Algorithm
Summary Trade-offs in page table implementation for
speed and space TLB in H/W Multi-level page tables Inverted page tables
The difference between page replacement policies first-in first-out not-recently-used page clock & second chance
Thursday, March 29
Assignment #7 Due Monday, April 2 Continue reading,
Chapter 4 – Memory Management Sec 4.4.8 Working SetSec 4.4.10 Summary of Page
ReplacementSec 4.5.1 Modeling Page Repl.Sec 4.8 Segmentation (pg 249-253)