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Enabling aMicroelectronic
Wafer Level Package and TechnologyWafer Level Package and Technology
RND
BYJUNG
or
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Wafer Level Packaging
Fab-like WLP, Hybrid packaging: Fab and Assy
Most or all of processing related to packaging the die is done at
wafer level, using redistribution and bumping
WLP, bumping and WLCSP are closely related and sometimes,
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70% of WLP business is directly related to cell phone
application
2008 global cell phone production: 1.3B unit 3.5M cell phones manufactured per day; every day!!
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WaferLevel
Cost Dimensions
I/O Density
ElectricalPerformance
Batch Processing High Parallelism
Improved test concepts
Packaging cost
Test cost
Pitches ( )
Interconnect line
Package height ( )
Lateral dimensions ( ) Smallest packageheights Minimum lateralarea
Min line length Multilayer RDL Reduced no. ofinterconnects
Min pitches
Why Consider Wafer Level
Packages?
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Packages
Functionality(Integration)
ThermalPerformance
No standards
Small chips / highno. of I/Os
Integrated Passives (R, L, C)
System in Package
3D
Power consumption ( )
Package Density ( )
length ( )
Operatingfrequencies ( )
Package Speed ( )
Parasitics
Integrated passivesin RDL SiP / 3D capability
Improved chip toboard coupling
= Increase
= Decrease Courtesy: Infineon Technologies
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Wafer BumpingWafer Bumping- Solder bump- Cu Pillar bump
Next Generation:Next Generation:IPD, TSV, MEMS
WLCSPWLCSP
Wafer Level PKG Classification
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Fine Pitch Trend in Bump/WLP
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Whats Different in WLP?
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Multilevel Wiring/Inductor/Cu Bar
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WLCSP Defined
Wafer Level Chip Scale Package is defined by Amkor asfollows:
Die size package
Mounted directly onto final substrate (typically PCB) No underfill required
Assembled using standard SMT pitch & assembly equipment
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Whats Different about Wafer Level
Package?
Wafer
FabDice
Traditional Package Flow
Mark
Mark
Mark
Test
Test
Test
Assy
Assy
AssySHIPPACKTest
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Test
SortMark Dice SHIP
Pick
Wafer
FabBump
Wafer Level Package FlowFlip
Chip
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Whats driving adoption of WLP?
Footprint (die = package; more functions same space)
Performance (bumps < Inductance than wire-bond)
Legacy die converted to WLP through use of RDL (
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Future WLCSP Developments
Thinner Package Height (
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WLFO(Wafer Level Fan Out)
Increased I/O, Reduced pkg thickness, electrical/thermal
performance
Potential cost reduction compared to conventional packages(fcCSP, wbCSP, MLF)
Potential for very thin POP configuration as technology is
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extended beyond single die package
New infrastructure, higher cost
Yield and manufacturing cost will be a challenge
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Standard WLCSP vs. WLFO
Both use fab level processes to build redistribution layer
WLCSP created within device footprint
WLFO created within and beyond device footprint
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Standard Wafer AMKOR WLFO Molded Wafer
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WLCSP vs. WLFO X-Sections
Solder
ball
Fan Out (MoldedArea)
Device
Silicon
Area
Device Silicon Area
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Dielectric 1 Dielectric 2Dielectric 1 Dielectric 2
Standard WLCSP
(RDL on a Silicon Wafer)
WLFO
(RDL on Reconstituted Wafer)
Redistribution
Layer
Redistribution
Layer
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Effect of Die Shrink on WLCSP
As die shrinks with each successive Silicon node, cannot fitBall Grid Array on die without reduction in BGA pitch
End users do not like BGA pitch reduction due to increase
motherboard and SMT process cost => Need to Fan OutInterconnections
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Process Flow
Filmlamination
Dieplacement
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Compressionmolding
Debondingfrom carrier
RDL Process
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Amkor WLFO
Dielectric
RDL(Redistribution)Si chip
Fan out Area
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