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EE235Carbon Nanotube FET
Volker Sorger
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metal metali or p-
gatesource drain
SBFET
Schottky Barrier (SB) CNT FET Transistor
“Carbon nanotubes as Schottky barrier transistors” Heinze et al., PRL, 89, 106801, 2002 Appenzeller et al., PRL, 89, 126801, 2002
Tunneling limited current. Gate electrostatics will
control the tunneling barrier.
Gate 8nm HfO2
SiO2
p++ Si
PdPd CNT
Javey, et al., Nano Letters, 4, 1319, 2004
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n+ n+i or p-
gatesource drain
MOSFET
MOS CNT FET Transistor
Electrons do not see any tunneling barrier in the “on” state.
Gate electrostatics control the top-of-the-barrier.
Appenzeller et al., IEDM, 2004
Javey et al., Nano Letters, 5,2, 2005
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CNTs: Best Case Scenario Current
CNT array FET
Iper tube ~ VDD/ 6.5Kohms
~150uA (@VDD = 1V)
Take d = S = 1nm;
Iper gate width ~ 500 X 150uA/um
~ 75mA/um (+non-idealities)
Isilicon ~ 1mA/um
Capacitance
COXIDE
CSEMI
Physics: Low DOS makes band pinning difficult.
Intuitively: Not enough electrons to screen the gate E-field.
Circuits: COXIDE >~ CSEMI
Cper tube <~ 1-5 aF (@Length=50nm)
Cper gate width ~ 500 X 2aF/um ~ 1fF/um
Csilicon ~ 1fF/um
Cinterconnect ~ 0.3fF/um (does not scale)
C (per unit micron of width) = 1X
I (per unit micron of width) = 50X
TDELAY (for same transistor width) = 0.02X ON
DDD I
CVT
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Work function Engineering for SB-FETs
What device can we What device can we built with this finding now?!built with this finding now?!M. H. Yang, W. I. MilneM. H. Yang, W. I. Milne , APL, 2005 , APL, 2005
Work function: 5.12eVWork function: 5.12eV 4.33eV 4.33eV ~3.9eV ~3.9eV
EcEc
EvEvEfEf
ssEcEc
EvEvEfEf
ssEcEc
EvEvEfEf
ss
P-typeP-type intrinsicintrinsic N-typeN-type
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1-D Device Basics
What we want!
– High Ion speed
– Low Ioff less leakage
– Steep switching small Subthreshold swing, SS
– High mobility, How can we archive this?
– Ion: Ohmic contacts + big tube
– Ioff: high quality tox, small tube
– SS: good gate coupling = small tox
rhrox Ln
LC
202 tgtotal
D
DD VV
L
C
V
Ig
2
111 qmoxtotal CCC
=4pF/cm=4pF/cm
Hole mobility
Si 480
Ge 1900
GaAs 400
CNT ~3000
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Intrinsic Gate Delay CV/I for PMOS
R. Chau, IEEE Nanotechnology, 2005 R. Chau, IEEE Nanotechnology, 2005
ON
DDD I
CVT
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CV/I versus Ion/Ioff Ratio
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Conclusion
CNT have potential
Devices can keep up with state-of-the-art Si
Still 3 major challenges to overcome (Integration)
~~~ Thank you for you attention ~~~~~~ Thank you for you attention ~~~
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CNT-FET Benchmarking
Intrinsic Speed: CV/I vs. Lg
SS vs. Lg
Speed vs. Ion/Ioff Metrology
– I=Ion (@ Vg = Vt + 2/3 VDS)
– I=Ion (@ Vg = Vt – 1/3 VDS)
– V=Vcc=Vg=|VDS|
– Device width = 2R
– Vt from standard peak conductance
R. Chau, IEEE Nanotechnology, 2005 R. Chau, IEEE Nanotechnology, 2005