×
+ All Categories
Log in
English
Français
Español
Deutsch
The top documents tagged [balanced circuit gupta]
Home >
balanced circuit gupta
Partial Scan Design with Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems, Circuits and Systems Research Lab Murray Hill, NJ 07974, USA.
231 views
Oct. 5, 2001Agrawal, Kim and Saluja1 Partial Scan Design With Guaranteed Combinational ATPG Vishwani D. Agrawal Agere Systems Processor Architectures and.
225 views