×
+ All Categories
Log in
English
Français
Español
Deutsch
The top documents tagged [chip networks]
Home >
chip networks
IST_presentation - California Institute of Technology
194 views
1 Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need? George Nychis, Chris Fallin, Thomas Moscibroda, Onur Mutlu Carnegie Mellon.
214 views
Manycores in the Future Rob Schreiber hp labs. Dont Forget These views are mine, not necessarily HPs Never make forecasts, especially about the future.
212 views
Chapter 3 Embedded Computing in the Emerging Smart Grid Arindam Mukherjee, ValentinaCecchi, Rohith Tenneti, and Aravind Kailas Electrical and Computer.
213 views
EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
[email protected]
.
231 views
The Raw All Purpose Unit (APU) based on a Tiled-Processor Architecture A Logical Successor to the CPU, GPU and NPU? Anant Agarwal MIT .
215 views
ECE 1749H: Interconnection Networks for Parallel Computer Architectures: Flow Control Prof. Natalie Enright Jerger.
237 views
1 On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-Core Interconnects George Nychis ✝, Chris Fallin ✝, Thomas Moscibroda.
215 views
UIC Thesis Corbetta
435 views
FULLTEXT01_4
96 views
Dual-mode inter-router communication channel for deflectionrouted networks-on-chip
255 views
REAL-TIME COMMUNICATION ANALYSIS FOR NOCS WITH WORMHOLE SWITCHING Presented by Sina Gholamian,
[email protected]
1 09/11/2011.
217 views
Next >