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The top documents tagged [chip test architectures]
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chip test architectures
EE141 System-on-Chip Test Architectures Ch. 12 - FPGA Testing - P. 1 1 Chapter 12 Field Programmable Gate Array Testing.
229 views
Feng-Xiang Huang MCORE Architecture implements Real-Time Debug Port based on Nexus Consortium Specification David Ruimy Gonzales Senior Member of Technical.
217 views
EE141 System-on-Chip Test Architectures Ch. 2 – Digital Test Architectures - P. 1 Chapter 2 Digital Test Architectures.
225 views
Built-In Self-Test and Calibration of Mixed-signal Devices Wei Jiang Ph.D. Dissertation Proposal June 11, 2009 Advisor: Vishwani D. Agrawal Committee Members:
216 views
EE141 System-on-Chip Test Architectures Ch. 8 – Physical Failures - P. 1 1 Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues.
216 views
EE141 System-on-Chip Test Architectures Ch. 3 - Fault-Tolerant Design - P. 1 1 Chapter 3 Fault-Tolerant Design.
251 views
Built-in Adaptive Test and Calibration of DAC Wei Jiang and Vishwani D. Agrawal Electrical and Computer Engineering Auburn University, Auburn, AL 36849.
215 views
EE141 System-on-Chip Test Architectures Ch. 7 – Low-Power Testing - P. 1 1 Chapter 7 Low-Power Testing.
214 views
EE141 System-on-Chip Test Architectures Ch. 14 – High-Speed I/O Interface - P. 1 1 Chapter 14 High-Speed I/O Interface.
220 views
Chapter 14
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Built-In Self-Test and Calibration of Mixed-signal Devices
42 views
Built-in Adaptive Test and Calibration of DAC
50 views
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