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The top documents tagged [gate delay]
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gate delay
PDF Chap 10
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1 Chapter 2 Combinational Logic Circuits Binary Logic and Gates Boolean Algebra Based on Logic and Computer Design Fundamentals, 4 th ed., by Mano and.
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High-K Dielectrics: Extending Current Semiconductor Manufacturing Techniques by Alexander Glavtchev.
229 views
A Survey and Comparison of Existing Low Power Ripple-Carry Adders
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MITIGATION OF SOFT ERRORS ON 65NM COMBINATIONAL LOGIC GATES VIA BUFFER GATE
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EE 5900 Advanced Algorithms for Robust VLSI CAD, Spring 2009 Sequential Circuits.
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Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect. n Switch logic.
225 views
Simulated Evolution Algorithm for Multi- Objective VLSI Netlist Bi-Partitioning Sadiq M. Sait, Aiman El-Maleh, Raslan Al-Abaji King Fahd University of.
221 views
Virtual and Physical Cellular Architectures for Kilo-processor Chip Computers Tamás Roska Hungarian Academy of Sciences and Pázmány P. Catholic University,
216 views
Dezső Sima Evolution of Intel’s transistor technology 45 nm – 14 nm October 2014 Vers. 1.0.
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Circuit Retiming with Interconnect Delay CUHK CSE CAD Group Meeting One Evangeline Young Aug 19, 2003.
217 views
Spring 2007Lec #8 -- HW Synthesis1 Vending Machine Example from Last Class symbolic state table presentinputsnextoutput stateDNstateopen 0¢00 0¢0 01 5¢0.
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