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The top documents tagged [parasitic delay]
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parasitic delay
Logical Effort - Designing Fast CMOS Circuits Sutherland Sproull Harris
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S. Reda EN160 SP08 Design and Implementation of VLSI Systems (EN1600) Lecture11: Delay Estimation Prof. Sherief Reda Division of Engineering, Brown University.
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logical Effort
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Lecture19
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Lecture19
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S. Reda EN160 SP’08 Design and Implementation of VLSI Systems (EN01600) Lecture 19: Combinational Circuit Design (1/3) Prof. Sherief Reda Division of Engineering,
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CMOS VLSI For Computer Engineering Lecture 4 – Logical Effort Prof. Luke Theogarajan parts adapted form Harris – and Rabaey- .
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LECT_1
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