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The top documents tagged [static cmos]
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static cmos
EECS 270C / Spring 2014Prof. M. Green / U.C. Irvine1 OC-192 (10 Gb/s) transceiver 0.18 µm CMOS process OC-192 communications system block diagram.
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1 Logic Restructuring for Timing Optimization Outline: Definitions and problem statementDefinitions and problem statement Overview of techniques (motivated.
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Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering
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OC-192 communications system block diagram
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Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering
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Logic Restructuring for Timing Optimization
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1 EE/CPRE 465 Memory Array Subsystems. 2 Outline Memory Arrays SRAM Architecture –SRAM Cell –Decoders –Column Circuitry –Multiple Ports DRAM Architecture.
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