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The top documents tagged [timing slack]
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timing slack
How to Read PT Report
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1 Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion Presented By Cesare Ferri Takumi Okamoto, Jason Kong.
226 views
Physical Synthesis Buffer Insertion, Gate Sizing, Wire Sizing,
235 views
Fast Buffer Insertion Considering Process Variation Jinjun Xiong, Lei He EE Department University of California, Los Angeles Sponsors: NSF, UC MICRO, Actel,
217 views
High-Performance Gate Sizing with a Signoff Timer
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RTL Compiler Synthesis
85 views