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The top documents of inesc-id

Cost-Efficient SHA Hardware Accelerators
Cost-Efficient SHA Hardware Accelerators
Distributed Software Platform for Automation and Control of General Anaesthesia
Distributed Software Platform for Automation and Control of General Anaesthesia
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design
FEVES: Framework for Efficient Parallel Video Encoding on Heterogeneous Systems
FEVES: Framework for Efficient Parallel Video Encoding on Heterogeneous Systems
Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs
Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs
Neural code metrics: Analysis and application to the assessment of neural models
Neural code metrics: Analysis and application to the assessment of neural models
Optimization Algorithms for Multiple Constant Multiplications
Optimization Algorithms for Multiple Constant Multiplications