1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State...

transcript

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State University (Ames)

CPRE 583Reconfigurable Computing

Lecture 3: Wed 9/2/2009(Reconfigurable Computing Architectures,

VHDL Overview 3)

Instructor: Dr. Phillip Jones(phjones@iastate.edu)

Reconfigurable Computing LaboratoryIowa State University

Ames, Iowa, USA

http://class.ece.iastate.edu/cpre583/

• Reinforce some common questions

• Finish Chapter 1 Lecture

• Continue Chapter 2

• VHDL review

Overview

• How does an FPGA work?

• How does VHDL execute on an FPGA?

• How many LUT on the classes FPGA? 44,000

• State machines will be cover more next lecture

• Final Project group selection: choose your own groups

• Class machine resources– Coover 2048, 1212; Coover 2041 ML507 (will be 2)– Distance students xilinx.ece.iastate.edu (other servers on the way)

Common Questions

• Basic trade-offs associated with different aspects of a Reconfigurable Architecture. (Chapter 2)

• Practice with timing diagrams, start state machines

What you should learn

Reconfigurable Architectures

• Main Idea Chapter 2’s author wants to convey– Applications often have one or more small

computationally intense regions of code (kernels)

– Can these kernels be sped up using dedicated hardware?

– Different kernels have different needs. How does a kernels requirements guide design decisions when implementing a Reconfigurable Architecture?

Reconfigurable Architectures• Forces that drive a Reconfigurable Architecture

– Price• Mass production 100K to millions• Experimental 1 to 10’s

– Granularity of reconfiguration• Fine grain• Course Grain

– Degree of system integration/coupling• Tightly• Loosely

All are a function of the application that will run on the Architecture

Example Points in (Price,Granularity,Coupling) Space

$100’s

$1M’s

Granularity

Coarse

CouplingLoose Tight

Intel /AMD

Processor

Ethernet

Decode

What’s the point of a Reconfigurable Architecture

• Performance metrics– Computational

• Throughput• Latency

– Power• Total power dissipation• Thermal

– Reliability• Recovery from faults

Increase application performance!

Typical Approach for Increasing Performance

• Application/algorithm implemented in software– Often easier to write an application in software

• Profile application (e.g. gprof)– Determine where the application is spending its time

• Identify kernels of interest– e.g. application spends 90% of its time in function

matrix_multiply()• Design custom hardware/instruction to accelerate kernel(s)

– Analysis to kernel to determine how to extract fine/coarse grain parallelism (does any parallelism even exist?)

Amdahl’s Law!

Amdahl’s Law: Example• Application My_app

– Running time: 100 seconds– Spends 90 seconds in matrix_mul()

• What is the maximum possible speed up of My_app if I place matrix_mul() in hardware?

• What if the original My_app spends 99 seconds in matrx_mul()?

10 seconds = 10x faster

1 seconds = 100x faster

Good recent FPGA paper that illustrates increasing an algorithm’s performance with Hardware

“NOVEL FPGA BASED HAAR CLASSIFIER FACE DETECTION ALGORITHM ACCELERATION”, FPL 2008

http://class.ece.iastate.edu/cpre583/papers/Shih-Lien_Lu_FPL2008.pdf

Reconfigurable Architectures• RPF -> VIC (short slide)

Granularity

Granularity: Coarse Grain

• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects

ALU ALU ALU

Example

ALU ALU ALU

Example

ALU ALU ALU

Example

Granularity: Fine Grain

• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates

CLB CLB CLB CLB

Configurable Logic Block

CLB CLB CLB

CLB CLB CLB CLB

CLB CLB

CLB CLB CLB CLB

Granularity: Trade-offsTrade-offs associated with LUT size

Example: 2-LUT (4=2x2 bits) vs. 10-LUT (1024=32x32 bits)1024-bits

1024-bits

10-LUTMicroprocessor

1024-bits

10-LUT

Bit logic and constants

1024-bits

10-LUT

(A and “1100”) or (B or “1000”)

1024-bits

10-LUT

(A and “1100”) or (B or “1000”)

1024-bits

10-LUT

(A and “1100”) or (B or “1000”)

It’s much worse, each 10-LUT only has one output

Area that wasrequired using

2-LUTS

Granularity: Example Architectures

• Fine grain: GARP

• Course grain: PipeRench

Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

RFUcontrol

(1)Execution(16, 2-bit)

PE (Processing Element)

Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

RFUcontrol

PE (Processing Element)Example computations in one cycleA<<10 | (b&c)(A-2*b+c)

Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

Impact of configuration size• 1 GHz bus frequency•128-bit memory bus• 512Kbits of configuration size

On a RFU context switch how longto load a new full configuration?

4 microseconds

An estimate of amount of time for theCPU perform a context switch is ~5 microseconds

~2x increase context switch latency!!

Granularity: GARP

CPU RFU

Garp chip

Memory

I-cache D-cache

Configcache

RFUcontrol

PE (Processing Element)

“The Garp Architecture and C Compiler”http://www.cs.cmu.edu/~tcal/IEEE-Computer-Garp.pdf

Granularity: PipeRench • Coarse granularity

• Higher (higher) level programming

• Reference papers• PipeRench: A Coprocessor for Streaming Multimedia Acceleration

(ISCA 1999): http://www.cs.cmu.edu/~mihaib/research/isca99.pdf• PipeRench Implementation of the Instruction Path Coprocessor

(Micro 2000): http://class.ee.iastate.edu/cpre583/papers/piperench_Micro_2000.pdf

Granularity: PipeRench

Interconnect

8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE8-bit ALU

Reg file

Interconnect

8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE8-bit ALU

Reg file

8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE8-bit ALU

Reg file

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

PE PE PEPE

Pipelinestage

1 2 3 4 5 6

Pipelinestage

1 2 3 4 5 6

Degree of Integration/Coupling • Independent Reconfigurable Coprocessor

– Reconfigurable Fabric does not have direct communication with the CPU

• Processor + Reconfigurable Processing Fabric– Loosely coupled on the same chip– Tightly coupled on the same chip

Degree of Integration/Coupling M

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

USB PCI PCI-Express SATA

Hard DriveNIC

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

Hard DriveNIC

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

Hard DriveNIC

FPURPF

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

Hard DriveNIC

ConfigI/F

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

Hard DriveNIC

ConfigI/F

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

Hard DriveNIC

RPFI/O

ConfigI/F

Execute Me

L1 Cache

L2 Cache

MemoryController

DMAController

I/OController

Hard DriveNIC

FPURFU

PC Display.cEthernet(UDP/IP)

Power PC

User Defined Instruction

Monitor VGA

Power PC

Monitor VGA

Power PC

Monitor VGA

MP2 Notes• MUCH less VHDL coding than MP1

• But you will be writing most of the VHDL from scratch

• The focus will be more on learning to read a specification (Power PC coprocessor interface protocol), and designing hardware that follows that protocol.

• You will be dealing with some pointer intensive C-code. It’s a small amount of C code, but somewhat challenging to get the pointer math right.

Lecture 3 notes / slides in progress

• Scheduling virtual stage on to physical• Partial/Dynamically reconfig (each cycle)

Granularity: GARP

• Impact of configuration size on performance• Context switching

• Garp feature• Dynamic reconfigurable• Store multiple configurations in an on chip

cache (4)• One configuration at a time

• Example app mapping to GARP (loop)• Amdahl's Law

The Garp Architecture and C Compiler• http://www.cs.cmu.edu/~tcal/IEEE-Computer-Garp.pdf

Overview• Dimensions

– Price– Granularity– Coupling– To optimize App Performance (compute (throughput, latency),

Power, reliability)• RPF to efficiently implement VICs

– Main picture authors' wants to convey• What’s the point or having a Reconfigure arch

– Example (Increase App performance)• App -> SW/CPU• Profile• ID kernels of intense compute• Design custom hardware/instruction (Amdels law)

– Intel FPL paper, great example for reading by Friday

1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Archs, VHDL 3 Iowa State...

Documents