Post on 13-Dec-2015
transcript
80GHz Modulator Designs
Ian Harrison School of Electrical and Electronic Engineering
University of NottinghamUK
Work done at
Department of ECEUniversity of California, Santa Barbara
USA
Harrison@ece.ucsb.edu 805-893-8044, 805-893-3262 fax
Special thanksPK, Zak, Mattias for fabrication of circuits and devicesMiguel for advicePaidi and Navin for cricket discussionsMark Rodwell for useful discussion and use of infrastructure
Introduction
• Concentrate on more recent work
• Thermal Modelling
• Modulator work – design issues– Simulation results
Design Specifications
• Two types of optical modulator– LiNb03 Mach Zehnder -Interference
• Split beam into 2, induce 0 or 180 phase shift
• Large driving voltage eg 10GBits 5Vpp
– Electroabsorption• Quantum confined stark effect
• Smaller driving voltage eg 10GBits 3Vpp
• Design specificationsE=0 E≠0
E=0
E≠0
λA
ttn
EA modulator2V , 50 Ohm input
Output should be matched
I
VC
.
• Switching speed limited by output capacitance
How do we get speed improvement
Design Specifications set ΔV and RL sets I
Reduce C by decreasing AC
Increase in J since I fixed J limited by Kirk Effect Increase in J increase dissipated power density
Formula simplisticinsight
1.5
2
2.5
3
3.5
0.6 0.8 1 1.2 1.4 1.6 1.8
J MA
X (
mA
/m)
VCE
(V)
Kirk effect and switching time
• Above Jkirk massive increase in base charge
Base push out (Field Screening)
2
4)(
C
satKirk T
vVcbJ
sat
C
ceE
C
v
T
V
V
A
A
4
Vsat=3.5 105cms-1
Wide emitter, narrow base mesaRb limits the emitter width
VCE
Predictsstraight line
Why is thermal management important?
• As J increases so does the power density. This will lead to an increase in the temperature.
TC JKirk Le
Å mAμm-2 μm
3000 1.0 81
2000 2.3 34
1500 4.1 19
1000 9.8 8.6
For VCE=1V PD=10.6mWμm-3
V=2V
80mA
For VCE=1V PD=98mWμm-3!!
Thermal Modeling of HBT (1)
• 3D Finite Element using Ansys 5.7• K (Thermal conductivity) depends temperature
• K depends on doping • For GaAs heavily doped GaAs 65% less than undoped GaAs
• Unknown for InP or InGaAs use GaAs dependency
n
T Tkk
300300
J.C.Brice in “Properties of Indium phosphide” eds S Adachi and J.Brice pubs INSPEC London p20-21S Adachi in “Properties of Latticed –Matched and strained Indium Gallium Arsenide” ed P Bhattacharya pubs INSPEC London p34-39“CRC Materials science and engineering handbook”, 2nd edition ,eds J.F Shackelford,A.Alexander, and J.S Park, pubs CRC press, Boca Raton, p270
Material K300 n K300(exp) Refs
InP 0.68 1.42 0.68-0.877 1
InGaAs 0.048 1.375 0.048-0.061 2
Au 3.17 - 3
Large uncertainty
in values
Layout used for simulation validation
Layer structure
Emitter 0.04μm n+ InGaAs
0.12 μm n- InP
Base 0.03 μm p+ InGaAs
Collector
Setback
Grade
Drift
0.02 μm InGaAs
0.024 μm Grade
0.156 μm InP
Subcollector
Etchstop 0.050 μm n+ InGaAs
0.200 μm n+ InP
Substrate 500 μm Fe: InP
Need simplified model for simulation reduce simulation time and storage requirements
Ignore base pad collector interconnect•2 orthogonal symmetry lines•Simulate only ¼ device
4
2.5
0.5
0.1
0.7
2
14
3.5
7.2
1
4
1.5
4
0.25500
102.5
102.5
Polyimide forpassivation Very low K ignoreIn thermal analysis
After M. Dahlstrom
Actual device
Simulated ¼ Device
Validation of Model
0
5
10
15
20
25
30
35
40
-0.2 0 0.2 0.4 0.6 0.8 1 1.2
centerEdge
Tem
per
atu
re R
ise
(K)
Distance from substrate (m)
SC ES C B E E Metal
Caused by Low K
of InGaAs
Max T in Collector
Ave Tj (Base-Emitter) =26.20°CMeasured Tj=26°CGood agreement.
Advice Limit InGaAs Increase size of emitter arm
Effect of decreasing collector thickness
V=0.3V
6mA
Choose LeFor J=JKirk
We=0.5um50% dutycycle
AssumptionsDevices thermally isolated
Device structure identical tovalidation structure
Perfect switching waveform
ObservationsTemperature increases rapidly for thin collectors (ΔTmax =60°C for TC=1000Å)
Collector temperature always higher than Tj
(ΔTMax-ΔTj)>30°C )
Increase in ISC possible failure mechanism( Major failure problem in GaAs HBT’s)
Temperature of one device approximately double when circuit is not switching
Analysis of 40,80,160 Gbit/s devices
• To obtain speed inprovements require to scale other device
parameters.Speed (Gbit/s) 40 80 160
Collector Thickness (Å) 3000 2000 1000
Base Sheet resistance () 750 700 700
Base contact resistance (-m2) 150 20 10
Base Thickness (Å) 400 300 250
Base Mesa width ( m) 3 1.6 0.4
Current Density (mA/m2) 1 2.3 9.8
Emitter. Junction Width ( m) 1 0.8 0.2
Emitter Parasitic resistivity (-m2) 50 20 5
Emitter Length ( m) 6 3.3 3.2
Predicted MS-DFF (GHz) 62 125 237
Ft (GHz) 170 260 500
Fmax (GHz) 170 440 1000
Tj (K) 7.5 14 28
TMax (K) 10 20 49
TMax (No Etch Stop layer) (K) 7.5 13 21
Conservative 1.5x bit rate
Reduction of parasitic CBC
Device parameters after Rodwell et al
When not switching values will double
V=0.3V
6mA
Thermal Analysis using ADS
• For simulations need a model that can be solved by ADS so that thermal and circuit simulations can be coupled.
• Thermal generation current source
• Thermal resistance resistors
• Thermal capacity capacitors (If static not needed)
• Temperature variation of thermal conductivity not modelled because resistors do not depend on current (This restriction could be lifted)
R network easily solvedUsing ADS
Coupled Circuit-Thermal modelling
• How do the advance device models do it?
– Device at one temperature– Devices thermally isolated and
described by a single resistance– Thermal circuit hidden from user
• How do we want to do it– Access to thermal circuit– β only slightly temperature dependent
– Large change in VBE(ON)
TVBE
Temperate rise
Value used in model Ambient T
Power dissipated in the device
Thermal Resistance
•Β is the band gap shrinkage factorNot usually given but optical measurements on band gap ( Optical values must be used with caution )
0.0004 for both InP and InGaAs
My model
Can we measure Rth (Method of Lui et al )
0.50 0.520.48 0.54
0.002
0.004
0.006
0.008
0.000
0.010
VBE
IC.i
VBE
I_DCSRC2Idc=IB
L8E7B21X1
I_ProbeIC V_DC
SRC1Vdc=VCE
Ramp IB for different VCE
Measure VBE and IC
CCE
BET IV
VR
Depends on current density
2 3 4 5 6
x 10-3
1000
2000
3000
4000
5000
PAve
RT
Large uncertainty in values. Fitting regression curves helps to reduce error
VCE
I_DCSRC1Idc=IC
L8E7B21X1V_DC
SRC2Vdc=VB
I_ProbeI_B
An alternative method for finding RT
CE
BE
CT dV
dV
IR
1
0 0.01 0.02 0.031000
2000
3000
4000
5000
RT
PIn
RTo= 1945
0.74 0.76 0.78 0.8 0.820.5
1
1.5
2
2.5
IC fixed , sweep VB
From gradient RT
Obtain RT (Pave) Changes in VC larger more accurate RT measured at lower PaveThermal instability possibleNeed to be careful on the VB range
Ic= 6mA,6mAIc=12mA,12mA
Ic= 6mA,6mAIc=12mA,12mA
Comparison of the two methods
0 0.005 0.01 0.015 0.021000
2000
3000
4000
5000
PAve
RT
0 0.01 0.02 0.031000
2000
3000
4000
5000
RT
PIn
RTo= 1945
0 0.005 0.01 0.015 0.021000
2000
3000
4000
5000
PAve
RT
Classic Method
Linear interpolation.
Empirical Curve fit
“New method”
Classic method badly affected by the 4145 resolution. Better measurements at very high power. Often leads to device failuresProblems with every fourth measurement of 4145 in “new” methodNeed to compare the two methods using the4155
Emitter Mask 12 x 0.7 mesa width 1.7
Which model to estimate Rth
• Finite elements clearly shows diffusion of heat along the collector under the base contacts.
• Rth should depend on base mesa size
Model 1
Models flow of heat under base
Thermal circuit complex
Model 2
Thermal circuit simple
Over estimates RT
Both Models
Both will underestimate RT at high powers
Experimental results
RT(C/W) 1.7 2.1 2.7
4 5500 5100 6200
12 1800 1800
Mesa Width
Leng
th
Use Model 2
Model 1
Model 2
Thermal resistance calculations
• Thermal resistance of layers can be estimated from the thermal conductivity if no heat spreading is assumed.
• The emitter interconnect acts as a thermal link
• The thermal resistance of the substrate is estimate by solving the 3D heat flow problem using separable variables technique. This is the same method Lui et al used to calculate RT of single and multi-finger HBT power transistors.†
After M. Dahlstrom
RT(C/W) 1.7 2.1 2.7 Theory
4 5500 5100 6200 5700
12 1800 1800 2071
Mesa Width
Leng
th
Spreadsheet: ThermalCalc.xls
Stability of single BJT’s (Intro)
• Well known problem solved by ballasting with emitter or base resistance.
• Known to be a problem in power amplifiers.
• May argue, incorrectly, that in digital circuits this is not a problem because we are driving the circuits with a constant current source.
• Need to know how large we can make the emitters before “hot spots” form and current “hogging” becomes an issue.
0.50 0.520.48 0.54
0.002
0.004
0.006
0.008
0.000
0.010
VBE
IC.i
If the transistor base is being driven with a constant voltage.The collector current will increase until it gets to point X.Any further increase in base voltage will cause an infinite increase in the collector current resulting in physical damage to the device.
X
Single Emitter Stability
0 0.01 0.02 0.032.6
2.8
3
3.2
3.4
3.6
Maximum VC for different I
C.
Emitter Length (Mask) =10m
VCM
ax (
V)
Collector Current (A)
TheoryExperiment
0 5 10 15 202.4
2.6
2.8
3
3.2
Emitter Length (Mask) (m)
VCM
ax (
V)
Stability curves against emitter length for const J
JC= 2 mAm-2
JC= 3 mAm-2
Caused by the increase in RT when device size is reduced.
Caused by the reduction of Re with length
Uncertainty in Re
ρE=60Ω from DC measurements
)( kqRI
kTRqIV
TC
ECMaxC
J =1 5mAμm-2
Optimum operating point
Hot spot formation (not finished)
Device broken into sections
RR23R=1587 Ohm
VARVAR1
Wb=1.4Rbb=0.45/Wb/2
EqnVar
RR26R=2986/2
RR27R=2986/2
L1E7B21TX11
RR25R=Rbb
L1E7B21TX10
RR24R=Rbb
Subs1x10X9
2
4
6
8
10
1
3
5
7
9
RR20R=2986
RR22R=2986
RR21R=2986
RR7R=Rbb
RR6R=Rbb
RR5R=Rbb
PortemitterNum=3
PortcollectorNum=2
L1E7B21TX5
L1E7B21TX8
L1E7B21TX7
L1E7B21TX6
RR18R=2986
RR17R=2986
RR16R=2986
RR1R=Rbb
RR4R=Rbb
RR3R=Rbb
RR2R=Rbb
PortbaseNum=1 L1E7B21T
X1L1E7B21TX4
L1E7B21TX3
L1E7B21TX2
Thermal model of substrate
Base electrical resistance
Thermal resistance of the emitter
connection
Need to do1. Simulate DC measurements2. Compare with measurements
Modulator design (Matching)
Passive
Resistive Feedback Feedback
Passive simple high bias current
All active circuitsBias current lower need to prevent saturation
Resistive feedbackNo flexibility Zo=1/gm
FeedbackZo=1/(gmβ) but additional EF more ringing
RC Feedback β<1
Effect of current source design on output
Capacitive coupling toControl line reduces output resistance
0 5 10 15 20 25 30 35-5 40
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-1.5
2.5
Time (ps)
Vol
tage
RiseI1.556E11
FallI2.161E11
RiseO3.366E11
FallO8.172E11
CommonReference
0 5 10 15 20 25 30 35-5 40
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-1.5
2.5
Time (ps)
Vol
tage
RiseI1.476E11
FallI2.012E11
RiseO3.577E11
FallO6.014E11
DifferentReferenceVo
Vo
Vm
Vm
Vi
Vi
Current switch (only one half)
Use resistor:- inefficient power use, but simple
Output stage options
Miller effect increases output cap
Performance depends on the quality of the ground
Bias generated by diode
0 5 10 15 20 25 30 35-5 40
-1.0
-0.5
0.0
0.5
1.0
-1.5
1.5
time, psec
Out
put V
olta
ge
With diode baseIdeal Vsrc
Current designs
• 2 and 3 stage amplifiers• Cascode and simple output
0 2 4 6 8 10 12 14 16 18-2 20
-1.0
-0.5
0.0
0.5
1.0
-1.5
1.5
time, psec
Out
put V
olta
ge
3 stage cascode output
0 5 10 15 20 25 30 35-5 40
-1.0
-0.5
0.0
0.5
1.0
-1.5
1.5
time, psec
Out
put V
olta
ge
80GBit/s160GBit/s
Simulations show that 160GBit is just possible with 1500A collector.
What to do in the future
• Fabricate and test the current design
• Design amplifiers with output voltage
• Simulate with self heating
• Investigate the more advanced BJT models
Conclusion
• 160 Gbits Modulator has been designed
• Electro -thermal model has been developed which can be simulated using ADS
What would I change if I could rewind the clock
Gone in the clean room.