ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE...

transcript

ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

FPGA Design with XilinxFPGA Design with XilinxISEISE

Presenter: Shu-yen Lin

Advisor: Prof. An-Yeu Wu

2005/6/6

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU

OutlineOutline

Concepts of Xilinx FPGAXilinx FPGA ArchitectureIntroduction to ISECode GeneratorConstraints and ReportsConfigurationDemo and Lab

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Concepts of Xilinx FPGAConcepts of Xilinx FPGA

Electronic ComponentsElectronic Components

FPGA BenefitsFPGA BenefitsFull-Custom

ICsCell-Based

ICsGate Arrays FPGA

Speed ●● ● ● ●

Integration Density ●● ● ● ●

High-Volume Device Cost ●● ●● ● ●

Low-Volume device Cost ● ●●

Time to Market ● ●●

Risk Reduction ●●

Future Modification ●●

Development Tool ● ● ● ●●

Educational Purpose ●●

Full Xilinx Design SupportFull Xilinx Design Support

Xilinx Products CPLDs and FPGAs

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Xilinx FPGA ArchitectureXilinx FPGA Architecture

The Conceptual CPLD ArchitectureThe Conceptual CPLD Architecture

pp. 10

The Conceptual FPGA ArchitectureThe Conceptual FPGA Architecture

Field-programmable Re-programmable In-circuit design verification Rapid prototyping Fast time-to-market No IC-test & NRE cost H/W emulation instead of S/W

pp. 11

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)

pp. 12

Logic and Routing - the CLB tile

pp. 13

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)6)

Two slices in each CLB Each slice contains 2 LUT, 2 Register and 2 Carry Logic.

Logic and Routing – Simplified CLB Structure

pp. 14

Logic and Routing – Look-Up Tables (LUTs) Combinational logic is stored in Look-up Tables (LU

Ts) in a CLB. Capacity is limited by number of inputs, not complex

ity. Delay through CLB is constant.

pp. 15

System Interface – Select IOTM

Supports multiple voltage and signal standards simultaneously Eliminate costly bus transceivers

pp. 16

System Memory – Distributed RAM, Block RAM and External Memory

pp. 17

Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6)6)

System clock management - DLLs Clock Mirror Multiplication

1 DLL for 2x Combine 2 DLL for 4x

Division Selectable division values - 1.5, 2, 2.5,

3, 4, 5, 8, or 16

Phase Shift 0, 90, 180, 270

pp. 18

Spatran-3, VirtexII FPGA Architecture (1/7)Spatran-3, VirtexII FPGA Architecture (1/7)

pp. 19

Spatran-3, VirtexII FPGA Architecture (2/7)Spatran-3, VirtexII FPGA Architecture (2/7) Logic and Routing - the CLB tile

pp. 20

Spatran-3, VirtexII FPGA Architecture (3/7)Spatran-3, VirtexII FPGA Architecture (3/7)System Interface – Select IOTM 23 different

standards supported !

pp. 21

Spatran-3, VirtexII FPGA Architecture (4/7)Spatran-3, VirtexII FPGA Architecture (4/7) System Memory –External Memory supports DDR memory

pp. 22

Spatran-3, VirtexII FPGA Architecture (5/7)Spatran-3, VirtexII FPGA Architecture (5/7) System clock management – DCMs

pp. 23

Spatran-3, VirtexII FPGA Architecture (6/7)Spatran-3, VirtexII FPGA Architecture (6/7) System clock management – DCMs

pp. 24

Spatran-3, VirtexII FPGA Architecture (7/7)Spatran-3, VirtexII FPGA Architecture (7/7) Embedded multiplexer

pp. 25

VirtexII Pro FPGA ArchitectureVirtexII Pro FPGA Architecture

pp. 26

Programmable Logic EvolutionProgrammable Logic Evolution

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Introduction to ISEIntroduction to ISE

pp. 28

ISE PhilosophyISE Philosophy

ISE 6.1i Future Xilinx devices Proactive Timing Closure ECS & HDL Bencher & XST

Platform Unix: Solaris 2.7/2.8 PC: Win 2000/XP

Service Pack http://support.xilinx.com

ISE WebPage http://www.xilinx.com/ise

pp. 29

Design Flow in ISE (1/2)Design Flow in ISE (1/2)

Design

Synthesis

Implement

Download

A & B = C

LUT RegA

Specification

RTL model

Synthesis

Download

Testbench

Pre-Synthesis Simulation

Post-Synthesis Simulation&

Static Timing Analysis

Post-Layout Simulation&

Static Timing Analysis

pp. 30

Design Flow in ISE (2/2)Design Flow in ISE (2/2)

pp. 31

Introduction to Projection Navigator Introduction to Projection Navigator (1/4)(1/4)

pp. 32

Introduction to Projection Navigator (2/4)Introduction to Projection Navigator (2/4) Source Windows

pp. 33

Introduction to Projection Navigator (3/4)Introduction to Projection Navigator (3/4)Processes for current source

pp. 34

Introduction to Projection Navigator (4/4)Introduction to Projection Navigator (4/4) Processes for current source

pp. 35

Create New ProjectCreate New Project

pp. 36

Create New SourceCreate New Source

pp. 37

HDL Source FileHDL Source File

pp. 38

Text EntryText Entry

pp. 39

Language TemplatesLanguage Templates

pp. 40

Synthesis (1/4)Synthesis (1/4) XST

pp. 41

Synthesis (2/4)Synthesis (2/4) XST Flow

pp. 42

Synthesis (3/4)Synthesis (3/4) Synthesis Step

pp. 43

Synthesis (4/4)Synthesis (4/4) RTL view

pp. 44

Implementation (1/8)Implementation (1/8)

Translate - Merge multiple design files into a single netlistMap - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs)Place & Route - Place components onto the chip, connect them, and extract timing data into reports

pp. 45

pp. 46

NCFEDIF

EDIF2NGD

.NGO .NGO

NGDBUILD

Core Generator

.NGO Native Generic Database

Logical DRCCheck-point

TranslateImplementation (3/8)Implementation (3/8)

pp. 47

Optional Constraint File(File from UCF)

Optional Guide Files(Files from the last mapping)

NGD PCF

NCD PCF

MapImplementation (4/8)Implementation (4/8)

pp. 48

Map Property Trim Unconnected Signals

If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly.

Generate Detailed Map Report If more detailed report is needed, you can check it. (Recommending ch

eck it) Use Guide Design File (.ncd)

You can refer the last mapping solution so that you maybe get better solution.

Use RLOC Constraints Constraints of CLB (default check).

Pack I/O Registers/Latches into IOBs If the value chosen Default that pack the register nearby I/O into I/O blo

ck. You can also chose only for input or only for output or off.

pp. 49

Optional Guide File

NCDNCD PCF

NCDDIR

Multi-PAR runSingle-PAR

Place and Route

pp. 50

Place and Route Property (1/2) Place & Route Effort Level (Overall)

Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time.

Starting Placer Cost Table (0-100) Specify a placement initialization value with which to begin P&R attem

pts. Each subsequent attempt is assigned an incremental value based on the placement initialization value.

Place and Route Mode Quick means without timing constraints; Route Only and Re-entrant Ro

ute mean P&R must have been run at last once to use this option.

Guide File Include the .ncd file.

pp. 51

Place and Route Property (2/2) Use Timing Constraints

Include the .ucf file.

Use Bonded I/Os If it is checked, signals will be connected to I/O pads.

Generate Detailed PAR Report Check the value to generate a detailed PAR report.

Generate Post-Place & Route Static Timing Report Check the value to generate post-place & route static timing report.

Generate Post-Place & Route Simulation Model Check it for generating required simulation files for ModelSim (*.v and *.

pp. 52

Download (1/2)Download (1/2)

pp. 53

Download (2/2)Download (2/2)

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Code GeneratorCode Generator

pp. 55

What are Cores?What are Cores?

pp. 56

Benefits of Using CoresBenefits of Using Cores

pp. 57

Invoking the CORE Generator GUIInvoking the CORE Generator GUI

pp. 58

Xilinx Code Generator System GUIXilinx Code Generator System GUI

pp. 59

Core Customize WindowCore Customize Window

pp. 60

Core Data SheetCore Data Sheet

pp. 61

Core Generator Design Flow Core Generator Design Flow

pp. 62

Link with CodeGen IP (Verilog)Link with CodeGen IP (Verilog)

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Constraints and ReportsConstraints and Reports

pp. 64

TopicsTopics

Assign Package Pins (PACE)Assigning Pins

Create Timing ConstraintsThe PERIOD ConstraintsThe Pad-to-Pad ConstraintsThe OFFSET ConstraintsThe Constraints Editor

Read Report

pp. 65

Constraints GUI (1/2)Constraints GUI (1/2)

pp. 66

Constraints GUI (2/2)Constraints GUI (2/2)

pp. 67

Assign Package Pins (1/6)Assign Package Pins (1/6)Start PACE Editor

pp. 68

Assign Package Pins (2/6)Assign Package Pins (2/6)

PACE Editor GUI

pp. 69

Assign Package Pins (3/6)Assign Package Pins (3/6)Method #1 to assign package pins

pp. 70

pp. 71

pp. 72

Assign Package Pins (6/6)Assign Package Pins (6/6)

Method #4 to assign package pins

Use text editor to edit .ucf files

NET is port nameLOC assign pins to sp

ecific location

pp. 73

The PERIOD ConstraintThe PERIOD Constraint

pp. 74

The Pad-to-Pad ConstraintThe Pad-to-Pad Constraint

pp. 75

The OFFSET ConstraintThe OFFSET Constraint

pp. 76

The Constraint Editor (1/3)The Constraint Editor (1/3)

pp. 77

The Constraint Editor (2/3)The Constraint Editor (2/3) Enter PERIOD and Pad-to-Pad Constraint

pp. 78

The Constraint Editor (3/3)The Constraint Editor (3/3) Enter OFFSET Constraint

pp. 79

Read Report (1/12)Read Report (1/12) Create Report Files

pp. 80

Read Report (2/12)Read Report (2/12)

pp. 81

Read Report (3/12)Read Report (3/12) Example of MAP Report (1/2)

pp. 82

Read Report (4/12)Read Report (4/12) Example of MAP Report (2/2)

pp. 83

pp. 84

Read Report (6/12)Read Report (6/12) Example of PAR Report (1/2)

pp. 85

Read Report (7/12)Read Report (7/12) Example of PAR Report (2/2)

pp. 86

pp. 87

Read Report (9/12)Read Report (9/12) Example of Timing Report (1/4)

pp. 88

pp. 89

pp. 90

pp. 91

Post-layout SimulationPost-layout Simulation

Modelsim

Post layoutsimulation file

testbench

Result

glbl.v simprims.sdf file

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ConfigurationConfiguration

pp. 93

What is configuration?What is configuration?

Process for loading into the FPGA

pp. 94

Configuration Mode (1/4)Configuration Mode (1/4)

pp. 95

Configuration Mode (2/4)Configuration Mode (2/4) Serial Mode

pp. 96

Configuration Mode (3/4)Configuration Mode (3/4)SelectMAP Mode

pp. 97

Configuration Mode (4/4)Configuration Mode (4/4) JTAG or Boundary Scan

pp. 98

IMACT (1/3)IMACT (1/3)

Must double clock “Generate Programming File” before programming FPGA

pp. 99

pp. 100

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE...

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