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Universität Dortmund
ADC Interfaces
Universität Dortmund
CORTEXTM-M3CPU
24 MHz
AR
M®
Pe
rip
he
ral B
us
(max
24
MH
z)
2 x I2C
1 x SPI
2 x USART/LINSmartcard / IrDaModem Control
37/51/80 I/Os
Up to 16 Ext. ITs
JTAG/SW Debug
Power SupplyReg 1.8V
POR/PDR/PVD
DMA7 Channels
Nested vect IT Ctrl
1 x USART/LINSmartcard/IrDaModem Control
1 x SPI
Bridge
Bridge
1 x Systick Timer
AR
M®
Lite
Hi-
Spe
ed
Bu
sM
atri
x /
Arb
ite
r (m
ax 2
4M
Hz)
RTC / AWU
ARM® Peripheral Bus
(max 24MHz)
XTAL oscillators32KHz + 4~25MHz
Int. RC oscillators40KHz + 8MHz
PLL
8kB SRAM
Flas
h I
/F
64kB - 128kB Flash Memory
Clock Control
20B Backup Data
1 x 12-bit ADCup to16 channels
Temperature Sensor
2 x Watchdog(independent & window)
6 x 16-bit Timer 1 x CEC
2-channel 12-bit DAC
1 x 16-bit PWM Synchronized AC Timer
• Core and operating conditions
- ARM® Cortex™-M3
- 1.25 DMIPS/MHz up to 24 MHz
- 2.0 V to 3.6 V range
- -40 to +105 °C
• LQFP48, LQFP/BGA64, LQFP100
• Advanced analog- 12-bit1.2 µs conversion time ADC- Dual channel 12-bit DAC
• Enhanced control- 16-bit motor control timer- 6x 16-bit PWM timers
• Rich connectivity- 8 communications peripherals
STM32 Value line 64K-128KBytes System Diagram
Universität Dortmund
Sensors data acquisitionData acquisition system components:
Sensors:
Convert analogue measurements of physical quantities (e.g. temperature, pressure, humidity, velocity, flow-rate, linear motion, position) into electrical signals (voltage or current).
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Data acquisition system components
• Signal conditioning (filtering and amplification):• The operations required to convert the measured analogue signal to
the electrical signal range of the analogue-to-digital converter (ADC) may involve filtering, amplification, attenuation or impedance transformation.
• Analogue-to-Digital Converter (ADC):• Input: Signal to be measured;
• Output: A digital code compatible with the digital processing system;
• Requires:– Sample-and-hold: Used to take a snapshot of the continuously changing
input signal and maintain the value over the sample interval set by a clocksystem;
– A sampling frequency based on the Nyquist theorem.
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Signal Types
Analog Signals
• Any continuous signal that a time varying variable of the signal is a representation of some other time varying quantity– Measures one quantity in
terms of some other quantity
– Examples• Speedometer needle as
function of speed
• Radio volume as function of knob movement
t
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Signal Types
Digital Signals
• Consist of only two states
– Binary States
– On and off
• Computers can only perform processing on digitized signals
0
1
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Background Information
• What is ADC?
• Conversion Process
• Accuracy
• Examples of ADC architectures
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Analog-Digital Converter (ADC)
• An electronic integrated circuit which converts a signal from analog (continuous) to digital (discrete) form
• Provides a link between the analog world of transducers and the digital world of signal processing and data handling
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Analog-Digital Converter (ADC)
• An electronic integrated circuit which converts a signal from analog (continuous) to digital (discrete) form
• Provides a link between the analog world of transducers and the digital world of signal processing and data handling
t
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Analog-Digital Converter (ADC)
• An electronic integrated circuit which converts a signal from analog (continuous) to digital (discrete) form
• Provides a link between the analog world of transducers and the digital world of signal processing and data handling
t
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ADC Conversion Process
Two main steps of process
1. Sampling and Holding
2. Quantization and Encoding
ttInput: Analog Signal
Sampling and
Hold
Quantizing
and
Encoding
Analog-to-Digital Converter
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ADC Process
t
Continuous
Signal
Sampling & Hold
• Measuring analog signals at uniform time intervals– Ideally twice as fast as
what we are sampling
• Digital system works with discrete states– Taking samples from each
location
• Reflects sampled and hold signal – Digital approximation
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ADC Process
t
Sampling & Hold
• Measuring analog signals at uniform time intervals– Ideally twice as fast as
what we are sampling
• Digital system works with discrete states– Taking samples from each
location
• Reflects sampled and hold signal – Digital approximation
Universität Dortmund
ADC Process
t
Sampling & Hold
• Measuring analog signals at uniform time intervals– Ideally twice as fast as
what we are sampling
• Digital system works with discrete states– Taking a sample from each
location
• Reflects sampled and hold signal – Digital approximation
Universität Dortmund
ADC Process
t
Sampling & Hold
• Measuring analog signals at uniform time intervals– Ideally twice as fast as
what we are sampling
• Digital system works with discrete states– Taking samples from each
location
• Reflects sampled and hold signal – Digital approximation
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ADC Process
Quantizing
• Separating the input signal into a discrete states with K increments
• K=2N
– N is the number of bits of the ADC
• Analog quantization size
– Q=(Vmax-Vmin)/2N
– Q is the Resolution
Encoding
• Assigning a unique digital code to each state for input into the microprocessor
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ADC ProcessQuantization & Coding
• Use original analog signal
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ADC ProcessQuantization & Coding
• Use original analog signal
• Apply 2 bit coding
K=22 00
01
10
11
00
11
10
01
Universität Dortmund
ADC ProcessQuantization & Coding
• Use original analog signal
• Apply 2 bit coding
K=22 00
01
10
11
00
11
10
01
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ADC ProcessQuantization & Coding
• Use original analog signal
• Apply 3 bit coding
K=23 000
001
010
011
100
101
110
111
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ADC ProcessQuantization & Coding
• Use original analog signal
• Apply 3 bit coding
• Better representation of input information with additional bits K=23 000
001
010
011
100
101
110
111
K=16 0000 K=…
.
.
.
1111
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ADC Process-Accuracy
Sampling Rate, Ts• Based on number of steps
required in the conversion process
• Increases the maximum frequency that can be measured
Resolution, Q• Improves accuracy in
measuring amplitude of analog signal
• Limited by the signal-to-noise ratio (~6dB)
t t
The accuracy of an ADC can be improved by increasing:
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ADC Process-Accuracy
Sampling Rate, Ts• Based on number of steps
required in the conversion process
• Increases the maximum frequency that can be measured
Resolution (bit depth), Q• Improves accuracy in
measuring amplitude of analog signal
t t
The accuracy of an ADC can be improved by
increasing:
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ADC-Error Possibilities
• Aliasing (sampling)– Occurs when the input signal is changing much faster
than the sample rate
– Should follow the Nyquist Rule when sampling• Answers question of what sample rate is required
• Use a sampling frequency at least twice as high as the maximum frequency in the signal to avoid aliasing
• fsample>2*fsignal
• Quantization Error (resolution)– Optimize resolution
– Dependent on ADC converter of microcontoller
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Types of ADC
• Successive Approximation A/D Converter
• Flash A/D Converter
• Dual Slope A/D Converter
• Delta-Sigma A/D Converter
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Successive Approximation ADC
Elements• SAR = Successive Approximation Register
• EOC = End of Conversion
• DAC = Digital to Analog Converter
• S/H = Sample and Hold Circuit
• Vin = Input Voltage
• Comparator
• Vref = Reference Voltage
• Clock (synchronous)VDAC
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Successive Approximation ADC
Algorithm• Uses an n-bit DAC and original analog results
• Performs a binary comparison of VDAC and Vin
• MSB is initialized at 1 for DAC
• If Vin < VDAC (VREF / 2^n=1) then MSB is reset to 0
• If Vin > VDAC (VREF / 2^n) Successive Bits set to 1 otherwise 0
• Algorithm is repeated up to LSB
• At end DAC in = ADC out
• N-bit conversion requires N comparison cycles
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Successive Approximation ADC - Example
5-bit ADC, Vin=0.6V, Vref=1V
Cycle 1 => MSB=1SAR = 1 0 0 0 0
VDAC = Vref/2^1 = .5 Vin > VDAC SAR unchanged = 1 0 0 0 0
Cycle 2SAR = 1 1 0 0 0
VDAC = .5 +.25 = .75 Vin < VDAC SAR bit3 reset to 0 = 1 0 0 0 0
Cycle 3SAR = 1 0 1 0 0
VDAC = .5 + .125 = .625 Vin < VDAC SAR bit2 reset to 0 = 1 0 0 0 0
Cycle 4SAR = 1 0 0 1 0
VDAC = .5+.0625=.5625 Vin > VDAC SAR unchanged = 1 0 0 1 0
Cycle 5SAR = 1 0 0 1 1
VDAC = .5+.0625+.03125= .59375
Vin > VDAC SAR unchanged = 1 0 0 1 1
Bit 4 3 2 1 0
Voltage .5 .25 .125 .0625 .03125
DAC bit/voltage
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Successive Approximation ADC - Example
000t
VR(t),VIN
VIN
100VR(t)
VFS
2
VFS
0
4
V3 FS
4
VFS
110
101
100
Final code
T 2T 3T 4T
001
010
011
100
101
110
111
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Flash ADC
Also known as parallel ADC
Elements
• Encoder – Converts output of comparators to binary
• Comparators
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Flash ADC
Algorithm– Vin value lies between two comparators
– Resolution ∆𝑉 =𝑉𝑟𝑒𝑓
2𝑁;
– N= Encoder Output bits
– Comparators => 2N-1
– Example: Vref 8V, Encoder 3-bit
• Resolution ∆𝑉 =8
23= 1.0V
• Comparators 23-1=7
– 1 additional encoder bit -> 2 x # Comparators
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Flash ADC Example
Vin = 5.5V, Vref= 8V
Vin lies in between Vcomp5 & Vcomp6
Vcomp5 = Vref*5/8 = 5V
Vcomp6 = Vref*6/8 = 6V
Comparator 1 - 5 => output 1
Comparator 6 - 7 => output 0
Encoder Octal Input = sum(0011111) = 5
Encoder Binary Output = 1 0 15.5V 1
1
1
1
1
0
0
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Flash ADC – pro & cons
• High speed– Limited only by delays of comparator and logics– Conversion rate ≈ 10-100Msample/s (or tconv order of
ms)
• Expensive (2n-1 comparators and 2n high precision R) preferrable for low num of bit ADC
• Low differential linearity– Difficult to have 2n identical R
– Comparators have offsets affecting the divider network threshold
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Dual Slope A/D Converter• Also known as an Integrating ADC
Clock Counter
Control
Logic
+_
Start Stop
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Dual-Slope ADC – How It Works
u
drefin
t
tVV
• An unknown input voltage is applied to the input of the integrator and allowed to ramp for a fixed time period (tu)
• Then, a known reference voltage of opposite polarity is applied to the integrator and is allowed to ramp until the integrator output returns to zero (td)
• The input voltage is computed as a function of the reference voltage, the constant run-up time period, and the measured run-down time period
• The run-down time measurement is usually made in units of the converter's clock, so longer integration times allow for higher resolutions
• The speed of the converter can be improved by sacrificing resolution
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Dual Slope Converter Pros & Cons
Advantages
• Input signal is averaged
• Greater noise immunity than other ADC types
• High accuracy
Disadvantages
• Slow
• High precision external components required to achieve accuracy
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Delta-Sigma A/D Converter
Delta-Sigma
ModulatorAnalog
InputDigital
Output
Low-Pass
Filter
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Delta-Sigma ADC – How It Works • Input over sampled, goes to integrator
• Integration compared with ground
• Iteration drives integration of error to zero
• Output is a stream of serial bits
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Delta-Sigma (ΔΣ) ADC
• Functionally, this results in a serial stream of bits output by the flip-flop. If the analog input is zero volts, the integrator will have no tendency to ramp either positive or negative, except in response to the feedback voltage. In this scenario, the flip-flop output will continually oscillate between “high” and “low,” as the feedback system “hunts” back and forth, trying to maintain the integrator output at zero volts:
• If, however, we apply an analog input voltage, the integrator will have a tendency to ramp its output in a positive direction. Feedback can only add to the integrator’s ramping by a fixed voltage over a fixed time, and so the bit stream output by the flip-flop will not be quite the same:
ΔΣ converter operation with
small analog input
ΔΣ converter operation with
0V analog input
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Delta-Sigma (ΔΣ) ADC
• By applying a larger analog input signal to the integrator, we force its output to ramp more steeply in the positive direction. Thus, the feedback system has to output more 1’s than before to bring the integrator output back to zero volts:
• As the analog input signal increases in magnitude, so does the occurrence of 1’s in the digital output of the flip-flop:
• A parallel binary number output is obtained from this circuit by averaging the serial stream of bits together. For example, a counter circuit could be designed to collect the total number of 1’s output by the flip-flop in a given number of clock pulses. This count would then be indicative of the analog input voltage.
ΔΣ converter operation with
medium analog input
ΔΣ converter operation with
large analog input
Analog input applied:
- Rise slopes faster
- Fall slope slower
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Delta-Sigma (ΔΣ) ADC
PRO
• High Resolution
• No need for precision components
CONS
• Slow due to over sampling
• Only good for low bandwidth
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Comparison of ADC’s
TypeSpeed
(relative)Cost
(relative)Resolution
(bits)
Dual Slope Slow Med 12-16
Flash Very Fast High 4-12
Successive Approx
Medium –Fast
Low 8-16
Sigma – Delta Slow Low 12-24