Arm Processor

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1TMT H E A R C H I T E C T U R E F O R T H E D I G I T A L W O R L D

The ARM Processor

2TM 239v10 The ARM Architecture

Submitted by –

Pradipta RoySidhartha RajakSantanu Mondal

ARM – Acorn RISC Machine/Advanced RISC Machine

Family – RISC (Reduced Instruction Set Computing)

Designer – ARM Holdings.

History

Invention Year – 1980 First Processor – BBC Micro Series Personal Use for Acorm Computer -> Business Market Acrom Computers -> ARM Ltd.

RISC - Reduced Instruction Set Computing.

A reduced instruction set computer is a computer which only use simple instructions that can be divide into multiple instructions which perform low-level operation within single clock cycle, as its name suggest “REDUCED INSTRUCTION SET”

RISC - Reduced Instruction Set Computing.

Let we take an example of multiplying two numbers A = A * B; <<<======this is C statement

LOAD R1, A <<<======this is assembly statementLOAD R2,B <<<======this is assembly statementPROD A, B <<<======this is assembly statementSTORE R3, A <<<======this is assembly statement

RISC – Advantages.

• Each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle “MULT” command.

• These RISC “reduced instructions” require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock)

• Pipelining is possible.

• Less Transistor = Reduced cost,low Heat & Power consumption.

ARM Powered Products

ARM Partnership Model

Licence

Perpetual (Implementation) License. Term License . Per Use License.

Data Sizes and Instruction Sets

The ARM is a 32-bit architecture.

When used in relation to the ARM: Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes)

Most ARM’s implement two instruction sets 32-bit ARM Instruction Set 16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode

Processor Modes The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised

IRQ : entered when a low priority (normal) interrupt is raised

Supervisor : entered on reset and when a Software Interrupt instruction is executed

Abort : used to handle memory access violations

Undef : used to handle undefined instructions

System : privileged mode using the same registers as user mode

The Registers

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers

Data processing Instructions

Consist of : Arithmetic: ADD ADC SUB SBC RSB

RSC Logical: AND ORR EOR BIC Comparisons: CMP CMN TST TEQ Data movement: MOV MVN

These instructions only work on registers, NOT memory.

Marketing

2005 – 90% Mobile Phone Processor Was ARM. 2010 – 95% Smart Phone, 35% Digital Television & Set-top Boxes. 2011 – Most Widely Used Arc. (32bit) in all Mobile phone & ES. 2013 – 10 Billion(1000 Crore) ARM Based Devices Produced. 2015 – 47 Billion (4700 Crore) ARM Based Chip Produced.

64-bit ARM

2012 – ARM Cortex A53 & A57. 2013 – Apple Developed First 64-bit Smartphone iPhone 5S(ARM v8) . 2014 – Google Nexus 9 (NVDIA TEGRA KI Processor). 2015 – Lenovo P90 (Intel 64-bit Atom).

OS Support

First 32-bit ARM Based Processor – Arthur OS

Embedded OS

Android & iOS

XL & Lumia OS

BlackBerry OS

Ubuntu Touch OS

Symbeian OS

Desktop OS Debian

Desktop OS - FreeBSD

Desktop OS - Fedora

Desktop OS - Open Suse

Arm Processor

Technology