Ch2 P1 CMOS Design - cours.polymtl.ca 1: Main CMOS circuits design rules Mohamad Sawan et al. ......

transcript

2013-01-23

GBM8320 Dispositifs Médicaux Intelligents

Microelectronics Part 1: Main CMOS circuits design rules

Mohamad Sawan et al.

Laboratoire de neurotechnologies Polystim !http://www.cours.polymtl.ca/gbm8320/!

med-amine.miled@polymtl.ca!mohamad.sawan@polymtl.ca!

23 January 2013

GBM5320 - Dispositifs Médicaux Intelligents 2

Outline Main CMOS circuits design rules •  Introduction •  The CMOS process

−  CMOS technology processing

•  The MOS Transistor −  Basic device physics −  Small Signal Model

Basic analog CMOS circuits •  Inverter •  Voltage follower •  Current mirrors •  Amplifiers and Op-Amps.

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CMOS technology for medical implants integration

•  Low power consumption is crucial for medical implant devices!

•  A single-chip must allow very-low-power operation while containing amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control!

•  Recent CMOS processes are suitable for pure analog integration with high operating speed!

•  CMOS is suitable to VLSI of both high-density digital circuits (e.g. DSP, memory, etc.) and analog circuits (amplifiers, ADC, DAC, etc.)!

•  CMOS digital circuits feature 0 static power consumption. !

•  High performance MOS switches à CMOS technology suitable for high accuracy sample-data circuits.!

Mixed signal design overview •  Newer CMOS technologies with smaller feature sizes (such as 180nm

and 130nm) can operate at increasingly high speed (5GHz), comparable to some bipolar technologies. !

•  CMOS technologies become mainstream technologies for mixed-signal integration due to the advantages of low cost and high integration density. Digital circuitries cost decreases by 29% each year in CMOS technology thanks to device downscaling; !

•  To benefit from this, analog ICs have to be integrated on the same chip with the digital circuits in mixed-signal integration;!

•  We are in SoC (System on a Chip) era, which favors CMOS technology;!

•  System on Chip: mixed-signal integrated circuits that contains analog, memory, logic, and embedded processor.!

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Mixed signal design overview

•  MOSFET ft frequency is continuously increasing over time.!

•  The minimum channel length of MOS transistors dropped from 25 mm in 1960s to 60 nm in the year 2005.!

•  Benefit of much higher complexity, smaller volume, less power consumption and higher frequency performance.!

Outline

•  Introduction •  The CMOS process

•  Basic blocks in CMOS Analog Circuits −  Inverter −  Voltage follower −  Current mirrors −  Amplifiers

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CMOS technology processing •  CMOS technologies

have penetrated application areas, which used to be the exclusive domain of bipolar or BiCMOS technology.!

•  Out of seven integrated RF transceivers introduced in 2003, four are realized in a CMOS process technology.!

CMOS technology processing

GateSource Drain

Bulk Si

Polysilicon

n+ S D

•  Four terminals: gate, source, drain, body!

•  Gate – oxide – body stack looks like a capacitor!–  Gate and body are

conductors!–  SiO2 (oxide) is a

very good insulator.!–  Called Metal-oxide-semiconductor (MOS) !–  Even though gate is no longer made of metal.!

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•  Typically use p-type substrate for nMOS transistors!

•  Requires n-well for body of pMOS transistors.!

p substrate

n well

OutVss VDD

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

VDDVSS

•  Lithography process similar to printing press!•  On each step, different materials are deposited or etched.!

•  Substrate are tied to VSS and n-well to VDD!

•  Metal to lightly-doped semiconductor forms poor connection. !

•  Use heavily doped well and substrate contacts / taps.!

p substrate

n well

OutVSS VDD

substrate tap well tap

VDDVSS

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VSS VDD

substrate tap well tapnMOS transistor pMOS transistor

•  Transistors and wires are defined by masks.!

•  Cross-section taken along dashed line.!

VDDVSS

p substrate

n well

OutVSS VDD

substrate tap well tap

•  Six masks!–  n-well!–  Polysilicon!–  n+ diffusion!–  p+ diffusion!–  Contact!–  Metal!

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

VSS VDD

substrate tap well tapnMOS transistor pMOS transistor

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p substrate

n well

n+p+ n+ p+

0.35_m

1.25_m200nm

Cross section of 0.35um CMOS technology!

Outline

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MOSFET Structure

•  The NMOS transistor is on p- substrate (bulk or body). !•  Two n+ regions form S (source) and D (drain) terminals. !•  MOS transistor is symmetric. S has lower potential than D for NMOS.!•  p- substrate is connected to the most negative voltage. !•  Ldrawn is the channel length drawn in the layout!•  L is the effective channel length.!•  tox is the gate oxide thickness (40Å in 0.18 µm and 22Å in 0.13 µm) !

MOSFET Structure

p- substrateDepletion region

Channel

VG >>0

+ + + + + + + + + + + + + +

- - - - - - - - - - - - - - - - -n+n+

•  If VGS > 0, the electrical field will repel holes and attracts electrons.!

•  When VGS reaches a value called the threshold voltage (Vth), channel under the gate becomes inverted. !!It changes from p-type to n-type semiconductor.!

•  n-type channel exists between the source and drain that allows carriers to flow.!

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VG S>VthVS = 0

VDS> 0

y y+dy

V(y)- +

MOS Characteristics

•  If VGS> Vth the channel is inverted. Conductivity is controlled by VGS- Vth .!

•  When VDS > 0 current ID flows from drain to source.!

•  The drain current :!

dQ is the channel charge in dy at a distance y from the source, and dt is the time required for this charge to cross the length dy.!

I-V characteristics!

MOS Characteristics

QI is the induced electron charge in unit area of the channel.!

The gate-to-channel voltage at a distance y from the source is VGS-V(y). ! Assume this voltage exceeds Vth we can write:!

vd(y) is the electron velocity at y.!

E(y) is horizontal electrical field and µn is the average electron mobility.!

dQ = QIWdy

QI = Cox VGS −V ( y)−Vth

"# $% Cox =

=Koxε0

dt = dy

vd ( y)

ID =WCox VGS −V ( y)−Vth

"# $%µn

ID =dQdt

( y ) = ∝ n E ( y ) , E ( y ) =

I-V characteristics (Cont’d)!

VG S>VthVS = 0

VDS> 0

y y+dy

V(y)- +

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MOS Characteristics

If VDS << 2(VGS- Vth), ID is proportional to VDS.!

ID dy0

L∫ = WCox VGS −V ( y)−Vth

#$ %&µndV0VDS∫

ID = µnCox

2 VGS −Vth( )VDS −VDS2"# $%

ID = µnCox

VGS −Vth( )VDS

VG S>VthVS = 0

VDS> 0

y y+dy

V(y)- +

MOS Characteristics

VG S>>Vth

VS = 0 VD > 0

( )D n ox GS th DS

WI C V V V

Lµ< −

( )D n ox GS th DS

WI C V V V

Lµ= −

•  As VDS increases, ID increases until the drain end of the channel becomes pinch off.!

•  Pinch off occurs when VGD <= Vth the channel is not inverted near the drain (QI=0).!

! VGD ≤Vth ⇒VDS ≥VGS −Vth

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MOS Characteristics

VG S>>Vth

VS = 0 VGD<Vth, VDS >VGS-Vth

Pinch -off

•  For VDS> VGS-Vth ID stays constant by ignoring the second order effects.!

Active region

Triode region

VDS =Vdsat

( )22D n ox GS th

WI C V VL

µ= −

( )D n ox GS th DS

WI C V V V

Lµ= −

ID = µnCox

2 VGS −Vth( )VDS −VDS2"# $%

VDS =VGS −Vth=VDsat

= µnCox

VGS −Vth( )2

Outline

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MOS Characteristics

•  ID increases slightly with increasing VDS due to the increasing of the depletion region width Xd with VDS!

VG S>>Vth

VS = 0 VDS >VGS-Vth

XdVB = 0Leff

ID = µnCox

W2Leff

VGS −Vth( )2, Leff = L − Xd

= −µnCox

W2Leff

2 VGS −Vth( )2 dLeff

= λ ID

Channel length modulation!

MOS Characteristics

VGSIncreases

Active or pinch -off regionTriode region

VDS = VGS -Vth

VGS <=Vth

Actual

•  Therefore, a good approximation to the influence of VDS on ID is!

ID ≈ ID λ = 0( ) + dID

ID = µnCox

VGS −Vth( )21+ λVDS( )

ID = µnCox

VGS −Vth( )VDS

ID = µnCox

VGS −Vth( )21+ λVDS( )Channel length modulation (cont’d)!

= ID λ = 0( ) 1+ λVDS( )

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MOS Characteristics

VS > 0 VDS

VB = 0

γ is the body effect constant!

•  If VSB increases, the effective threshold voltage increases.!

•  VSB increases, the depletion region between the channel and the substrate becomes wider à QB k.!

QB ≅ −qN Axd = 2qεSi N A 2ΦF → 2qεSi N A (2ΦF +VSB )

Vth =Vth0 + ΔVth , Vth0 =Vth (VSB = 0)

Vth =Vth0 + γ VSB + 2ΦF − 2ΦF( ), γ =2qN A KSiε0

Body effect!

PMOS equations

Increases

VSD = VSG -|Vthp|

VSG <=|Vthp|

Actual

ID =µ pCox

2 VSG − Vthp( )VSD −VSD2"

#$%, VSG > Vthp andVDG > Vthp

µ pCox

VSG − Vthp( )21+ λVSD( ), VSG > Vthp andVDG < Vthp

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MOS symbols

•  The B symbol is used for substrate to avoid confusion with source.!•  Drain in NMOS is positioned on top while the source is positioned on top for

PMOS.!•  Symbol with B connection is used when the source and the substrate have

different voltages!•  Symbols w/o arrow are used for digital circuit.!

NMOS PMOS

Device model summary

Linear / triode region

VDS < VGS - Vth

Saturation regionVDS >= VGS - Vth

Weak inversionVGS < Vth

Strong inversionVGS > Vth

V VGS DSnV VT T

VGSnVT

S DS T

WI I e eL

WI e V V

−" #= −$ %$ %

≈ >>

026 300T

kTV mV at T K

q= ≈ =

DSD ox GS th DS

ox GS th DS DS dsat

W VI C V V V

WC V V V V V

) *= − −+ ,

≈ ) − * <<- .

( ) ( )211

2D ox GS th DS

WI C V V V

Lµ λ= − +

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Small-Signal Models of MOS Transistors: NMOS ID

VGSIncreases

VDS = VGS -Vth

VGS <=Vth

Actual

ID =µnCox

VGS −Vthn( )VDS , VGS >Vthn andVGD >Vthn (VDS <VGS −Vthn )

µnCox

VGS −Vthn( )21+ λVDS( ), VGS >Vthn and VGD <Vthn (VDS >VGS −Vthn )

Vthn =Vthn0 + γ VSB + 2ΦF − 2ΦF( ), γ =

2qN D KSiε0

Cox λ =

Leff dVDS

VDDVSS

Small-Signal Models of MOS Transistors: PMOS ID

Increases

VSD = VSG -|Vthp|

VSG <=|Vthp|

Actual

ID =µ pCox

VSG − Vthp( )VSD , VSG > Vthp andVDG > Vthp (VSD <VSG − Vthp )

µ pCox

VSG − Vthp( )21+ λVSD( ), VSG > Vthp andVDG < Vthp (VSD >VSG − Vthp )

Vthp =Vthp0 + γ VBS + 2ΦF − 2ΦF( ), γ =

2qN A KSiε0

Cox λ =

Leff dVSD

VDDVSS

Ch2 P1 CMOS Design - cours.polymtl.ca 1: Main CMOS circuits design rules Mohamad Sawan et al. ......

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