2013-01-23 1 GBM8320 Dispositifs Médicaux Intelligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim http://www.cours.polymtl.ca/gbm8320/ m [email protected][email protected]M5031 23 January 2013 GBM5320 - Dispositifs Médicaux Intelligents 2 Outline Main CMOS circuits design rules • Introduction • The CMOS process − CMOS technology processing • The MOS Transistor − Basic device physics − Small Signal Model Basic analog CMOS circuits • Inverter • Voltage follower • Current mirrors • Amplifiers and Op-Amps.
Transcript
2013-01-23
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GBM8320 Dispositifs Médicaux Intelligents
Microelectronics Part 1: Main CMOS circuits design rules
Mohamad Sawan et al.
Laboratoire de neurotechnologies Polystim !http://www.cours.polymtl.ca/gbm8320/!
Outline Main CMOS circuits design rules • Introduction • The CMOS process
− CMOS technology processing
• The MOS Transistor − Basic device physics − Small Signal Model
Basic analog CMOS circuits • Inverter • Voltage follower • Current mirrors • Amplifiers and Op-Amps.
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CMOS technology for medical implants integration
• Low power consumption is crucial for medical implant devices!
• A single-chip must allow very-low-power operation while containing amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control!
• Recent CMOS processes are suitable for pure analog integration with high operating speed!
• CMOS is suitable to VLSI of both high-density digital circuits (e.g. DSP, memory, etc.) and analog circuits (amplifiers, ADC, DAC, etc.)!
• CMOS digital circuits feature 0 static power consumption. !
• High performance MOS switches à CMOS technology suitable for high accuracy sample-data circuits.!
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Mixed signal design overview • Newer CMOS technologies with smaller feature sizes (such as 180nm
and 130nm) can operate at increasingly high speed (5GHz), comparable to some bipolar technologies. !
• CMOS technologies become mainstream technologies for mixed-signal integration due to the advantages of low cost and high integration density. Digital circuitries cost decreases by 29% each year in CMOS technology thanks to device downscaling; !
• To benefit from this, analog ICs have to be integrated on the same chip with the digital circuits in mixed-signal integration;!
• We are in SoC (System on a Chip) era, which favors CMOS technology;!
• System on Chip: mixed-signal integrated circuits that contains analog, memory, logic, and embedded processor.!
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Mixed signal design overview
• MOSFET ft frequency is continuously increasing over time.!
• The minimum channel length of MOS transistors dropped from 25 mm in 1960s to 60 nm in the year 2005.!
• Benefit of much higher complexity, smaller volume, less power consumption and higher frequency performance.!
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Outline
• Introduction • The CMOS process
− CMOS technology processing
• The MOS Transistor − Basic device physics − Small Signal Model
• Basic blocks in CMOS Analog Circuits − Inverter − Voltage follower − Current mirrors − Amplifiers
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CMOS technology processing • CMOS technologies
have penetrated application areas, which used to be the exclusive domain of bipolar or BiCMOS technology.!
• Out of seven integrated RF transceivers introduced in 2003, four are realized in a CMOS process technology.!
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CMOS technology processing
n+
p
GateSource Drain
Bulk Si
SiO2
Polysilicon
n+ S D
B
G
• Four terminals: gate, source, drain, body!
• Gate – oxide – body stack looks like a capacitor!– Gate and body are
conductors!– SiO2 (oxide) is a
very good insulator.!– Called Metal-oxide-semiconductor (MOS) !– Even though gate is no longer made of metal.!
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CMOS technology processing
• Typically use p-type substrate for nMOS transistors!
• Requires n-well for body of pMOS transistors.!
n+
p substrate
p+
n well
In
OutVss VDD
n+ p+
SiO2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
VDDVSS
In
Out
• Lithography process similar to printing press!• On each step, different materials are deposited or etched.!
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CMOS technology processing
• Substrate are tied to VSS and n-well to VDD!
• Metal to lightly-doped semiconductor forms poor connection. !
• Use heavily doped well and substrate contacts / taps.!
n+
p substrate
p+
n well
In
OutVSS VDD
n+p+
substrate tap well tap
n+ p+
VDDVSS
In
Out
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CMOS technology processing
VSS VDD
Out
A
substrate tap well tapnMOS transistor pMOS transistor
substrate tap well tapnMOS transistor pMOS transistor
In
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n+
p substrate
p+
n well
n+p+ n+ p+
600_m
0.35_m
6.5nm
1.25_m200nm
Cross section of 0.35um CMOS technology!
CMOS technology processing
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Outline
• Introduction • The CMOS process
− CMOS technology processing
• The MOS Transistor − Basic device physics − Small Signal Model
• Basic blocks in CMOS Analog Circuits − Inverter − Voltage follower − Current mirrors − Amplifiers
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MOSFET Structure
• The NMOS transistor is on p- substrate (bulk or body). !• Two n+ regions form S (source) and D (drain) terminals. !• MOS transistor is symmetric. S has lower potential than D for NMOS.!• p- substrate is connected to the most negative voltage. !• Ldrawn is the channel length drawn in the layout!• L is the effective channel length.!• tox is the gate oxide thickness (40Å in 0.18 µm and 22Å in 0.13 µm) !
W
L
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MOSFET Structure
p- substrateDepletion region
Channel
VG >>0
+ + + + + + + + + + + + + +
DS
- - - - - - - - - - - - - - - - -n+n+
B
• If VGS > 0, the electrical field will repel holes and attracts electrons.!
• When VGS reaches a value called the threshold voltage (Vth), channel under the gate becomes inverted. !!It changes from p-type to n-type semiconductor.!
• n-type channel exists between the source and drain that allows carriers to flow.!
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VG S>VthVS = 0
n+n+
VDS> 0
ID
y
y y+dy
V(y)- +
B
MOS Characteristics
• If VGS> Vth the channel is inverted. Conductivity is controlled by VGS- Vth .!
• When VDS > 0 current ID flows from drain to source.!
• The drain current :!
dQ is the channel charge in dy at a distance y from the source, and dt is the time required for this charge to cross the length dy.!
ID =
dQdt
I-V characteristics!
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MOS Characteristics
QI is the induced electron charge in unit area of the channel.!
The gate-to-channel voltage at a distance y from the source is VGS-V(y). ! Assume this voltage exceeds Vth we can write:!
vd(y) is the electron velocity at y.!
E(y) is horizontal electrical field and µn is the average electron mobility.!
dQ = QIWdy
QI = Cox VGS −V ( y)−Vth
"# $% Cox =
εox
tox
=Koxε0
tox
dt = dy
vd ( y)
ID =WCox VGS −V ( y)−Vth
"# $%µn
dVdy
ID =dQdt
v d
( y ) = ∝ n E ( y ) , E ( y ) =
d V
d y -
I-V characteristics (Cont’d)!
VG S>VthVS = 0
n+n+
VDS> 0
ID
y
y y+dy
V(y)- +
B
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MOS Characteristics
If VDS << 2(VGS- Vth), ID is proportional to VDS.!
ID dy0
L∫ = WCox VGS −V ( y)−Vth
#$ %&µndV0VDS∫
ID = µnCox
W2L
2 VGS −Vth( )VDS −VDS2"# $%
ID = µnCox
WL
VGS −Vth( )VDS
I-V characteristics (Cont’d)!
VG S>VthVS = 0
n+n+
VDS> 0
ID
y
y y+dy
V(y)- +
B
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MOS Characteristics
n+
VG S>>Vth
VS = 0 VD > 0
ID
n+
B
ID
VDS
( )D n ox GS th DS
WI C V V V
Lµ< −
( )D n ox GS th DS
WI C V V V
Lµ= −
• As VDS increases, ID increases until the drain end of the channel becomes pinch off.!
• Pinch off occurs when VGD <= Vth the channel is not inverted near the drain (QI=0).!
! VGD ≤Vth ⇒VDS ≥VGS −Vth
I-V characteristics (Cont’d)!
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MOS Characteristics
n+
VG S>>Vth
VS = 0 VGD<Vth, VDS >VGS-Vth
ID
n+
Pinch -off
• For VDS> VGS-Vth ID stays constant by ignoring the second order effects.!
ID
VDS
Active region
Triode region
VDS =Vdsat
( )22D n ox GS th
WI C V VL
µ= −
( )D n ox GS th DS
WI C V V V
Lµ= −
ID = µnCox
W2L
2 VGS −Vth( )VDS −VDS2"# $%
VDS =VGS −Vth=VDsat
= µnCox
W2L
VGS −Vth( )2
I-V characteristics (Cont’d)!
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Outline
• Introduction • The CMOS process
− CMOS technology processing
• The MOS Transistor − Basic device physics − Small Signal Model
• Basic blocks in CMOS Analog Circuits − Inverter − Voltage follower − Current mirrors − Amplifiers
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MOS Characteristics
• ID increases slightly with increasing VDS due to the increasing of the depletion region width Xd with VDS!
!
n+
VG S>>Vth
VS = 0 VDS >VGS-Vth
ID
n+
XdVB = 0Leff
ID = µnCox
W2Leff
VGS −Vth( )2, Leff = L − Xd
dID
dVDS
= −µnCox
W2Leff
2 VGS −Vth( )2 dLeff
dVDS
=ID
Leff
dXd
dVDS
= λ ID
Channel length modulation!
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MOS Characteristics
ID
VDS
VGSIncreases
Active or pinch -off regionTriode region
VDS = VGS -Vth
VGS <=Vth
Actual
Ideal
• Therefore, a good approximation to the influence of VDS on ID is!
