Digital Integrated Circuits Lecture 20: Package, Power, Clock, and...

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DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 1

Digital Integrated CircuitsLecture 20: Package, Power, Clock, and I/O

Chih-Wei Liu

VLSI Signal Processing LAB

National Chiao Tung University

cwliu@twins.ee.nctu.edu.tw

Outline

Packaging

Power Distribution

Clock Distribution

Packages

Package functionsElectrical connection of signals and power from chip to boardLittle delay or distortionMechanical connection of chip to boardRemoves heat produced on chipProtects chip from mechanical damageCompatible with thermal expansionInexpensive to manufacture and test

Package Types

Through-hole vs. surface mount

Multichip Modules

Pentium Pro MCMFast connection of CPU to cacheExpensive, requires known good dice

Chip-to-Package Bonding

Traditionally, chip is surrounded by pad frameMetal pads on 100 – 200 μm pitchGold bond wires attach pads to packageLead frame distributes signals in packageMetal heat spreader helps with cooling

Advanced Packages

Bond wires contribute parasitic inductanceFancy packages have many signal, power layers

Like tiny printed circuit boardsFlip-chip places connections across surface of die rather than around periphery

Top level metal pads covered with solder ballsChip flips upside downCarefully aligned to package (done blind!)Heated to melt ballsAlso called C4 (Controlled Collapse Chip Connection)

Package Parasitics

Signal P

PackageCapacitor

Signal P

ChipVDD

ChipGND

BoardVDD

BoardGND

Bond Wire Lead Frame

Package

Use many VDD, GND in parallelInductance, IDD

Heat Dissipation

60 W light bulb has surface area of 120 cm2

Itanium 2 die dissipates 130 W over 4 cm2

Chips have enormous power densities

Cooling is a serious challenge

Package spreads heat to larger surface areaHeat sinks may increase surface area further

Fans increase airflow rate over surface area

Liquid cooling used in extreme cases ($$$)

Thermal Resistance

ΔT = θjaPΔT: temperature rise on chip

θja: thermal resistance of chip junction to ambientP: power dissipation on chip

Thermal resistances combine like resistorsSeries and parallel

θja = θjp + θpa

Series combination

Example

Your chip has a heat sink with a thermal resistance to the package of 4.0° C/W. The resistance from chip to package is 1° C/W.The system box ambient temperature may reach 55° C.The chip temperature must not exceed 100° C.What is the maximum chip power dissipation?

(100-55 C) / (4 + 1 C/W) = 9 W

Power Distribution

Power Distribution Network functionsCarry current from pads to transistors on chip

Maintain stable voltage with low noise

Provide average and peak power demands

Provide current return paths for signals

Avoid electromigration & self-heating wearout

Consume little chip area and wire

Easy to lay out

Power Requirements

VDD = VDDnominal – Vdroop

Want Vdroop < +/- 10% of VDD

Sources of Vdroop

IR dropsL di/dt noise

IDD changes on many time scalesclock gating

Average

Power System Model

Power comes from regulator on system boardBoard and package add parasitic R and LBypass capacitors help stabilize supply voltageBut capacitors also have parasitic R and L

Simulate system for time and frequency responses

VoltageRegulator

Printed CircuitBoard Planes

Packageand Pins

SolderBumps

BulkCapacitor

CeramicCapacitor

PackageCapacitor

On-ChipCapacitor

On-ChipCurrent DemandVDD

PackageBoard

Bypass Capacitors

Need low supply impedance at all frequenciesIdeal capacitors have impedance decreasing with ωReal capacitors have parasitic R and L

Leads to resonant frequency of capacitor

frequency (Hz)

impedance

0.03 Ω

0.25 nH

Frequency Response

Use multiple capacitors in parallelLarge capacitor near regulator has low impedance at low frequenciesBut also has a low self-resonant frequencySmall capacitors near chip and on chip have low impedance at high frequencies

Choose caps to get low impedance at all frequencies

frequency (Hz)

impedance

Clock Distribution

On a small chip, the clock distribution network is just a wire

And possibly an inverter for clkbOn practical chips, the RC delay of the wire resistance and gate load is very long

Variations in this delay cause clock to get to different elements at different timesThis is called clock skew

Most chips use repeaters to buffer the clock and equalize the delay

Reduces but doesn’t eliminate skew

Example

Skew comes from differences in gate and wire delayWith right buffer sizing, clk1 and clk2 could ideally arrive at the same time.But power supply noise changes buffer delaysclk2 and clk3 will always see RC skew

1.3 pF

3.1 mmgclk

0.5 mm

clk2clk3

0.4 pF 0.4 pF

Review: Skew Impact

clk clk

Combinational Logic

tsetup

( )setup skew

sequencing overhead

hold skew

pd c pcq

cd ccq

t T t t t

t t t t

≤ − + +

≥ − +

144424443

Ideally full cycle isavailable for workSkew adds sequencingoverheadIncreases hold time too

Cycle Time Trends

Much of CPU performance comes from higher ff is improving faster than simple process shrinksSequencing overhead is bigger part of cycle

8038680486PentiumPentium II / III

1985 1988 1991 1994 1997 2000

1.2 0.8 0.6 0.35 2.0

Process

500VDD = 5 VDD = 3.3

VDD = 2.5

50Fano

f-4 (F

rter D

8038680486PentiumPentium II / III

1988 1991 1994 1997 20001985

1985 1988 1991 1994 1997

8038680486PentiumPentium II / IIIFO

Solutions

Reduce clock skewCareful clock distribution network design

Plenty of metal wiring resources

Analyze clock skewOnly budget actual, not worst case skews

Local vs. global skew budgets

Tolerate clock skewChoose circuit structures insensitive to skew

Clock Dist. Networks

Ad hoc

H-tree

Hybrid

Clock Grids

Use grid on two or more levels to carry clockMake wires wide to reduce RC delayEnsures low skew between nearby pointsBut possibly large skew across die

Alpha Clock Grids

gclk grid

Alpha 21064 Alpha 21164 Alpha 21264

gclk grid

Alpha 21064 Alpha 21164 Alpha 21264

H-Trees

Fractal structureGets clock arbitrarily close to any pointMatched delay along all paths

Delay variations cause skewA and B might see big skew A B

Itanium 2 H-Tree

Four levels of buffering:Primary driverRepeaterSecond-level clock bufferGater

Route aroundobstructions

Primary Buffer

Repeaters

Typical SLCBLocations

Hybrid Networks

Use H-tree to distribute clock to many pointsTie these points together with a grid

Ex: IBM Power4, PowerPCH-tree drives 16-64 sector buffersBuffers drive total of 1024 pointsAll points shorted together with grid

Input / Output

Input/Output System functionsCommunicate between chip and external world

Drive large capacitance off chip

Operate at compatible voltage levels

Provide adequate bandwidth

Limit slew rates to control di/dt noise

Protect chip against electrostatic discharge

Use small number of pins (low cost)

I/O Pad Design

Pad typesVDD / GNDOutputInputBidirectionalAnalog

Output Pads

Drive large off-chip loads (2 – 50 pF)With suitable rise/fall timesRequires chain of successively larger buffers

Guard rings to protect against latchupNoise below GND injects charge into substrateLarge nMOS output transistorp+ inner guard ringn+ outer guard ring

In n-well

Input Pads

Level conversionHigher or lower off-chip VMay need thick oxide gates

Noise filteringSchmitt triggerHysteresis changes VIH, VIL

Protection against electrostatic discharge

VDDLA Y

ESD Protection

Static electricity builds up on your bodyShock delivered to a chip can fry thin gatesMust dissipate this energy in protection circuits before it reaches the gates

ESD protection circuitsCurrent limiting resistorDiode clamps

ESD testingHuman body modelViews human as charged capacitor

Diodeclamps

Thingate

oxides

Currentlimitingresistor

DeviceUnderTest

1500 Ω

100 pF

Bidirectional Pads

Combine input and output padNeed tristate driver on output

Use enable signal to set directionOptimized tristate avoids huge series transistors

Analog Pads

Pass analog voltages directly in or out of chipNo bufferingProtection circuits must not distort voltages

MOSIS I/O Pad

1.6 μm two-metal processProtection resistorsProtection diodesGuard ringsField oxide clamps

264 Ω 185 Ω

In_bIn_unbuffered

Digital Integrated Circuits Lecture 20: Package, Power, Clock, and...

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