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ECE 5/410 Digital IC Design

Course Introduction

Vishal Saxena (vishalsaxena@boisetstate.edu)

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Course Outline

• Instructor : Dr. Vishal Saxena

• Time : Mon/Wed 6:00-7:15 PM

• Course dates : Aug 24 – Dec 9, 2015

• Location : MEC 307

• Office Hours : Mon/Wed 4:00-5:00 PM

• Holidays : Nov 23&25, Thanksgiving break.

• Final Exam time: Monday, Dec 14, 2015, 5:00-7:00 p.m.

• Website : http://lumerink.com/courses/ece5410/f15/ECE5410.htm

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Course Topics

• An introduction to CMOS IC design, layout, and simulation

• MOSFET operation and parasitics

• Digital design fundamentals

– Digital logic design and analysis

– logic sequencing

• Custom circuits: Charge pumps

• Extensive amount of circuit design, layout and simulation in Cadence design environment

• Pre-requisite

– Brush-up concepts from ECE 310 (Microelectronics)

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Textbook and References

• CMOS Circuit Design, Layout and Simulation – R. J. Baker, 3rd Ed., Wiley-IEEE, 2010. – Circuit design and simulation examples

– Cadence examples available on the server

• CMOS VLSI Design: A Circuits and Systems Perspective, N. Weste and D. Harris, 4th Ed., Addison-Wesley, 2010.

• For detailed references and handouts see this page.

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Course Pedagogy, Grading and Policies

• Combination of lecture notes, slides and simulation – Lecture notes/slides will be posted at the end of the week

• Workload (Grading)

– 15% Midterm Exam 1 – 15% Midterm Exam 2 – 15% Homeworks – 15% Quizzes – 20% Project – 20% Final Exam

• Policies – No late work accepted. All assigned work is due at the beginning of class. – Neither the final exam nor final project will be returned at the end of the semester. – Please be discreet with internet devices such as laptop, smartphones and tablets in

class. – Plagiarism is not acceptable. Look at the BSU student code of conduct.

http://www.boisestate.edu/policy/policy_docs/2020_studentcodeofconduct.pdf

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Digital Circuits in Action

XC3028 TV Tuner Chip Single-chip analog and digital TV tuner showing the

fully integrated RF-to-baseband functional blocks.

Intel Quad-core Processor

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IC Design Courses at Boise State

ECE 510

– Digital IC Design

ECE 511

– CMOS Analog IC Design

ECE 518

–PLL and Memory IC Design

ECE 614

– Advanced Analog IC Design

ECE 615

– Mixed-Signal IC Design

ECE 613 (tentative)

– Wireless IC Design

Other Courses: ECE 530

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IC Design Flow

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Standard Wafer Sizes

1 inch.

2 inch (50.8 mm). Thickness 275 µm.

3 inch (76.2 mm). Thickness 375 µm.

4 inch (100 mm). Thickness 525 µm.

5 inch (127 mm) or 125 mm (4.9 inch). Thickness 625 µm.

150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.

200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.

300 mm (11.8 inch, usually referred to as "12 inch" or "Pizza size" wafer). Thickness 775 µm.

450 mm ("18 inch"). Thickness 925 µm (expected)

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Packages and Die

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DIP Packaging

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Recent Packages

Refer to: http://en.wikipedia.org/wiki/Chip_package

QFN BGA

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Layout and Cross-sectional Views

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Back to the basics of IC Design.