INTERCONNECT MODELING

M.Arvind2nd M.E Microelectronics

OVERVIEW

Introduction to On-Chip interconnects

Modeling the parasitics

Elmore Delay Model

Repeater insertion

Min delay condition

Power Model

Optimizing Power

Introduction to On-chip interconnects

Wires linking the transistors together

Three types of interconnects :

Local

Semi-global and

Global interconnect

Introduction to On-chip interconnects

Can be modeled as R, RC, LC, RLC or RLGC network.

Power lines R,RL

Signal lines C, RC

Clock lines & buses RLC

Modeling a piece of wire

Capacitance Modeling

Capacitance

• cw = 2 * (cg + cf * cc )

• cf is the coupling factor

Capacitance Modeling (cont)

cg has 2 components: cg1, cg2

1

2

( , , )

( , , , )

(s, , )

g

g

c

c f ILDT w

c f ILDT s h

c f h

Simplified Capacitance Model

For a circuit designer ILDT, h and ε are fixed. Therefore,

1

2

( )

( )

( )

g

g

c

c f w

c f s

c f s

Fringing Effects

1fC 2fC

1fC

0fC

1fC

Modeling Wire Resistance

Resistance

w

lr

Al

h w h sq

Pros and Cons of Cu

Pros Better electro-migration resistance

Cons Cu atoms diffuses into SiO2

Cladding layers of TiN, Si3N4 used to prevent this

Increases the resistance

Elmore Delay Model

Delay of a RC network is given by

1 1 1 2 2 1 2 3 3

1 2

( ) ( ) ...

( ... )n n

D RC R R C R R R C

R R R C

Delay of a long wire

Delay grows quadratic Hence need repeaters

Repeater Insertion

Repeaters are placed to reduce delay

Repeater Insertion (cont)

Delay grows linear

Modeling the repeater

Repeater is a large inverter (5-25μm) placed in-between interconnect lines.

Cgate, Cp α size of the repeater

RT = VDD/2*Iavg, where Iavg = ∫Iddt in the interval Td

Modeling the repeater (cont)

2

(1 ( )

at

{( ) }2

d dlin ds gs th

dsat ds dsat ds gs th

dsat d ds dsat gs th

dsdlin eff ox gs th ds

I I V V V

I V V V V V

I I V V V V

VWI C V V V

L

Delay equations

Delay of an interconnect segment is

Total delay is

TD= R *( ) *( )2w

w gate p w gate

CC C C R C

tot TD = {R *( ) *( )}*2w

w gate p w gate

CC C C R C N

Optimal Repeater Size and Spacing

The minimum delay condition

[ {( ) } { }]*2

0; 0;

2 ( )

w w wTgate p gate

t w

w gate

w w

t gate p

c l r l c lrD c c size c s N

size N N ND D

size N

rcSize

r c

r cN

r c c

Power modeling

Total power dissipated in the interconnect network is given by• Ptotal= Pdy + Psc + Pleak

• Pdy = Ctotal V²

ddf

• Psc = Isc per μm Vdd Wtotalftt

• Pleak = Ileak per μm WtotalVdd

Where is the switching factor, tt is the time taken

for the input to transit from Vthn to Vdd – Vthp

Power modeling (cont)

0

min

( )*2

(1 )

at , 0.12

* *

gs th ds

t t

wtotal gate p

V V V

nV Vleak

ddsc d gs ds dd

total

CC C C N

I I e e

VI I V V V

W W size N

Optimizing power

Min delay does not imply min power

Techniques to Reduce Power

Can be reduced by decreasing Supply voltage

Size of repeaters

Number of repeaters

Optimal Power Delay Tradeoff

References

William J.Dally John W.Poulton., ”Digital Systems Engineering” Cambridge University Press,1998

Kaustav Banerjee et al., ”A power-optimal insertion methodology for global interconnects in nanometer designs” IEEE TRANSACTION ON ELECTRON DEVICES, VOL. 49, NO. 11, NOVEMBER 2002

Kaustav Banerjee et al., ”A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation” IEEE TRANSACTION ON ELECTRON DEVICES. VOL. 51, NO.2, FEBRUARY 2004.

Thank You