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Adaptive Circuitsfor
the 0.5-V Nanoscale CMOS Era
Kiyoo Itoh
Hitachi Ltd., Tokyo, Japan
ISSCC2009 Keynote
2009 IEEE International Solid-State Circuits Conference 2009 IEEE
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K. Itoh
OUTLINE
1. IntroductionThe 1-V wall
2. Adaptive Circuits for Memory-Rich LSIsTrends in VminBreakthrough technologiesScenario to the 0.5-V nanoscale era
3. Adaptive Circuits for Mixed Signal LSIs
Digital assisted analog design4. Conclusion
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K. Itoh
The 1-V Wall
Device feature size, F(nm)800 350 90 45 22 11
VDD
Target
180
Vmin(RDF)
543
2
1
0.4
VDD,Vmin(V)
0.2
0.60.8
MPUs(ISSCC), Vmin: Min. op. VDD
Power crisis
RDF: Random Dopant Fluctuation
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What should we do to lower VDD?
1. Reduce min. operating VDD(Vmin) by reducingLowest necessary Vt(Vt0),
Intrinsic Vt-variation ( Vt).New devices, circuits, repair etc.
2. Reduce power-supply noise (Vps)Compact subsystems (small core/chip,3-D chip stack) etc.
Reducing Vmin is the key. (VminVps)
2009 IEEE International Solid-State Circuits Conference 2009 IEEE
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OUTLINE
1. IntroductionThe 1-V wall
2. Adaptive Circuits for Memory-Rich LSIsTrends in VminBreakthrough technologiesScenario to the 0.5-V nanoscale era
3. Adaptive Circuits for Mixed Signal LSIs
Digital assisted analog design4. Conclusion
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Circuits Giving Low-VDDLimitations
* Most sensitive to Vt
Vt large largest small
LW 8F2(av.) 1.5-3F2 15F2
Count large largest medium
Inverter SRAM Cell* DRAM SA
Vt 1/ LW, F: device feature size
Chip
Logic block
RAM block
Peri. Array
DL
cell
WL
DL
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Definition ofVmin
(Vt) VDD/(VDDVt)1.2
= (Vt0+ Vtmax)/ (Vt0)={(VDDVt0)/(VDDVt0 Vtmax)}1.2
Vt0: Lowest necessary av.Vt
VTmax: Max. variation in Vt
Vmin=VDDfor a fixed=Vt0+ (1 + ) Vtmax
= 1/( 1/1.21)
: Tolerable speed
variation23 for =1.4 1.6
Inverter SRAM Cell DRAM SAVDD
DLDL0
SP
VDD-vS
DL
SN
DL
VDD
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High and Unscalable Vt0
Sub
thresholdleakage
(A)
10-8
10-710
-6
10-510-410-3
10-210-1100
101102
-0.2 0 0.2 0.4 0.6 1
Tj= 75 C, 130 nm
Vt0(ext, 25 C)
Vt0(ext) =Vt0(nA/ m) + 0.3 V
1-Mgate Logic
1-Mb SRAM
64-KDRAM SAs*
0.8
HP LP
HP
LP
* contributing to leakage in active standby mode
HP: high performance, LP: low power
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Vtmax
K. Itoh et al., p. 68, ESSCIRC2007 K. Takeuchi et al., p. 467, IEDM 2007
Vtmax= mm circuit count
=Avt/ LW
{tox(Vt0+ 0.1 V)}0.5
Nsub0.25
For lower Vtmax, use1. Repair
ECC + Redundancy (m->1/2)
2. Small technologies
Circuits toleratingThe largest MOSFET possibleThe lowest Vt0possible
Small-AvtMOSFETs
Avt(mV
m),tOX(nm
)
Device feature size, F(nm)
10
54
3
2
1
0.5
0.4
0.3
Avt
2.5
1.5
FD-SOI, EOT = 0.5 nm
tOX
250 130 90 65 45 32180
4.2
Conv. (tOX )High-k MG (tOX )FD-SOI (Nsub )
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ECC + Redundancy
RedundantWords
ECC word with one defectcell corrected by ECC.
ECC word with two or
more defect replacedby a redundant word.
parity
bits
data
bits
N
WECC Words
defective cell replace
K. Itoh, ESSCIRC2007 Dig., pp. 68-75
r: repairable %Max r= 0.1%(SRAMs), 0.4%(DRAMs).
32M 64M 128M 256MSRAM(b)128M 256M 512M 1GDRAM(b)
m
3.3
2.9
2
4
6
0.1 (SRAM)
0.01
0.001%
r= 0%
SRAM DRAM
5.5
6.0
0.4 (DRAM)
1
5
3
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Trends in Vmin=Avt/ LW
LW= 8F2(L), 1.5F2(SRAM), 15F2(DRAM)
Avt= 1.5 mV m (Hi-k MG, SOI)Avt= 4.2 mV m (Conv.)
F(nm)Logic (g)
0.2V
0.4V
0.2
VVt0
=0.4
V
Vmin(V)
0.2
2
1
0.5
0.4
3
SRAM (b)DRAM (b) 8G
130 65250180 90 45 32 22 15 11
32M
1.3M 5M 20M 80M 320M8M 32M 128M 512M 2G
128M 512M 2G
Repair for RAMs
DRAM
LogicSRAM
8G
320M
Repair for RAMs
Vt0=0.
4V
0.2V
0.4V
0.2V
DRAM
LogicSRAM
130 65250180 90 45 32 22 15 11
32M
1.3M 5M 20M 80M8M 32M 128M 512M 2G
128M 512M 2G
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K. Itoh
Dynamic S-control 8-T cell
State-of-the-Art SRAM Cells
WDL
VDDWWLRWL
RDLWDL
M1
M2
VDLor float (W)
VDD( VDL)
0
VDL
VDD
STB ACT
0
00
Increased cell-power supply Dynamic S-control
K. Itoh, p. 132, VLSI Circuits96; H. Akamatsu, p. 14, VLSI Circuits96; F. Hamzaoglu, ISSCC08, p. 376; L. Chang, p. 252, VLSI Circuits9
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Reduction in Vminof SRAMs
6-T cell 6-T cell vs 8-T cell
8-T, LW F2
156-185F2
LW F2
120F2
6-T
LW FW fixedat 90 nm
11
Cellsiz
e(ratio)
1
0.5
0.4
0.3
0.2
0.1130 90 65 45 32 22 15Device feature size, F(nm)
LW FW fixedat 90 nm
Vt0=0
.4V
0.2V
LW F2
SRAM(b)65
32130 15250 64M 256M16M 1G
= 1.6, repairAvt= 2.5 mV m
F(nm)
3
0.2
2
1
0.5
0.4
0.3
V
min(V)
4M
LW FW fixedat 90 nm
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Breakthrough Technologies
1. Adaptive devices/circuits(Vmin ) -scalable FinFET
Dual-VDDdual-Vt0circuit2. Adaptive tech. (Vps )
with small chip/compact
subsystem 2-D selection FinFET cell Many-core and chip stack
The best way to predict the future is to invent it.for reducing Vminand Vps
0.4
(a.u.)
0.2
0.6
0.8
1.2
1.0
0.60 0.1 0.2 0.3 0.4 0.5Vt0(V)
(Vt0+ 0.1 V)0.5
Vmin= Vt0+ (1+ ) m
Future Perspectives, ISLPED02, August 2002.
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Assumptions forAvt and Vt0=Avt/ LW, > 1 ( : device scaling factor)
tOX Avt 1/Vt0= 0.4 V
250 130 90 65 45 32 15Device feature size, F(nm)
Poly-Si bulk
Avt
HP
10
54
3
2
1
0.5
Avt(mVm
),
tOX(nm
)
0.4
0.3
High-k MG, FD-SOI
2.5
1.5
FD-SOI, EOT = 0.5 nm
22 11
LP
180
Avt 1/
Vt0= 0.2 V
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L/
W/ D G S
Planar FinFET
AvtL
W
LW
1/1/
1/
1/ 2
1/
1/1/
1
1
1/1/
1/
1/ 2
1/
1/1/
1
HP LP HP LP
L/W
GS
D
> 1, =Avt/ LW
-Scalable FinFET
by scaling up the height of fin
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and Vminfor HP Designs
Planar Fin
SRAM
Logic
DRAM
5040
3020
10
54
32
(mV)
Device feature size, F(nm)45 32 22 15 11
Repair for RAMs
Logic
DRAM
Logic
SRAM
SRAM
0.49
0.27
1
0.5
0.4
0.3
0.2
Vmin
(V)
F(nm)
SRAM (b)
45 32
128M 256M 512M
22 15 11
1G 2GLogic (g) 20M 40M 80M 160M 320M
DRAM (b) 4G 8G2G1G512M
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and Vminfor LP Designs
100
45 32 22 15 11Device feature size, F(nm)
5040
30
20
10
(mV)
54
SRAM
Logic
DRAM
Repair for RAMs
F(nm)
SRAM (b)
45 32
128M 256M 512M
22 15 11
1G 2GLogic (g) 20M 40M 80M 160M 320M
DRAM (b) 4G 8G2G1G512M
2
1
0.5
0.4
0.3
Vmin(V)
DRAM
Logic
SRAM
1.41.3Logic
SRAM
0.65
Planar Fin
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Dual-VDDDual-Vt0Dynamic Circuit
45 32 22 15 11Device feature size, F(nm)
0.65Vt0=0.4V
Vt0=0V
FinFETs
Vminfor dual-VDDdual-Vt0circuit
0.50.40.3
0.2
0.1
2
1
Vmin
(V)
0.11
Logic block
Logic block
VDD, VtH VDL, VtL
Bigger area ofVDLsub-block
Lower Vmin
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Gate-Source Offset Driving
K. Itoh et al., p. 68, ESSCIRC2007
0.6
0.4
0.2
Vt(V)-0.4 -0.2 0 0.2 0.4
VDL(V)
0
VDD= 0.6 VVteff=Vt0= 0.3 VVG= 0.3 V
D E
Vteff=
V+Vt Vt0
VG=VDL Vt
Stdby Active
V 0
VDDVDL
VDLlow Vt
VDL
CK1
VDD
M1
M2
N
CK2
M4
OUT
M3
IN
low Vt
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0.1-V Swing E/D Dynamic Inverter
Others: E-MOS (Vt= 0.3 V).W(nm)=140(M1,M3),
420(M2), 280(M4),L=50 nmCL= 4fF+4MOSs.K. Itoh et al., p. 68, ESSCIRC2007
CK1
VDLVDD
M1
M2
N
CK2
M4
OUT
M3
IN
Widely applicable to low-powerbuffers and others.
Vol
tage(V)
OUT
(IN:L)
0 0.5 1.0 1.5 2.0 2.50
0.1
0.2
0.3
0.4
0.5
0.6
3.0
CK2
CK1
N(IN:L)N(IN:H)
OUT
(IN:H)
Time (ns)
VDL= 0.1 V, VDD= 0.6 VD-MOS (Vt= 0.2 V)
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K. Itoh
Breakthrough Technologies
1. Adaptive devices/circuits(Vmin ) -scalable FinFET
Dual-VDDdual-Vt0circuit2. Adaptive tech. (Vps )
with small chip/compact
subsystem 2-D selection FinFET cell Many-core and chip stack
The best way to predict the future is to invent it.for reducing Vminand Vps
Future Perspectives, ISLPED02, August 2002.
0.4
(a.u.)
0.2
0.6
0.8
1.2
1.0
0.60 0.1 0.2 0.3 0.4 0.5Vt0(V)
(Vt0+ 0.1 V)0.5
Vmin= Vt0+ (1+ ) m
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2-D Selection DRAM Cell
Conventional 2-D selection
512 cells
SA
DLMC
WL
CD= 512Cd(1)
WL
1-T 1-C
vS CS/CDDL
CSVDD/0
CS 1/20 for same vS
CD = 16Cd+ 32Ci/024Cd(0.05)ifCd= 4Ci/0
2-T 1-C
vS CS/CDDL
WL
YS
CS
DL
YSWL
32
16
i/0
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PL
WL
p-subSTI
SiO2
n+
YS
2-T FinFET DRAM Cell
A FinFET and FinFET capacitor at the side wall Another FinFET with the gate controlled by buried YS line One DL shared by two cells
5F2/cell (cf. 6-8F2 for DRAMs, >160F2 for SRAMs)
DL0 YS0 DL1 YS1 DL2
cont.
WL
PL
i
5F
2F
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K. Itoh
M L
C0,0
C1,0
C127,0
C0,1
C1,1
C127,1
C0,127
C1, 127
C127,127
power switch
Many-Core LSI
16k cores in the 11-nm generation
Chip: 10 x 10 mm2
320 Mg, 8-Gb DRAM
Small Core: 56 x 56 m2
20-Kg + others (0.67)512-Kb DRAM (0.33)
5F2
cellChallenges:DevelopRedundant circuits/cores
LN HS power switch etc.
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Differentially-Driven Low-Vt0Power Switches
ProposedConventional
Large VPS(VDDswing of ND)Int. logic state destroyedSlow recovery of ND
core
P. Sw.
VDD
SP
VDD
VDD
0
0
ND
highVt0
Ifioffp= ioffn, ND & NS VDD/2.VPScanceled.
(differentially-driven ND & NS)
Int. logic state held
Fast recovery
SPioffp
ioffn Sn
VDD
VDD
0
0
0VDD
VDD/2
VDD
ND
NS
lowVt0
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Simulation Results
20-kgate coreVDD= 0.5 V, Vt0= 0.2 V, 85 C
WP= 320 360 nmWn= 240 190 nmL= 50 nm
VDD
SPVt0= 0,WP
ND
55WP
100Wn 100Wn
NS
Vt0= 0,Wn Sn
55WP
Leakage power of 16k cores:1.4 W (standby)
9.3 W (active, all cores activated)
0.2
0.6
0 100n 200n 300n
0.3
0.1
1.0
ND
NS
1.16 mA
0.5
0.18 mA
0.2 VVN(V)
mA
15 ns
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Chip Stack
Interface chip
9 stacked DRAM chips
(each 50 m thick)
TSVBumpTSV: Through
Silicon Via
by courtesy of ELPIDA
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Scenario to the 0.5-V Era
RDF: Random Dopant Fluctuation
Breakthrough
Device feature size, F(nm)
800 350 90 45 22
VDD
180
Vmin(RDF)
54
3
2
1
0.4
0.2
0.6
0.8
Power crises
HP
MPU(ISSCC), Vmin: Min. op. VDD
11
Repair-scalable MOS
(FinFET)
Dual-VDDdual-Vt0circuitsTiny DRAM cellMany-core LSIs
LN HS powergating
VDD
,Vmin(V
)
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Memory-Rich LSI vs. Mixed Signal LSI
Mixed signal LSI
DAC/ADC
Analog
+
L/M
+ ++
comp.
op-amp
Vtmax* 0.5 mV 2.3 mV
20 200
*Avt= 1.25 mV m, Vt0= 0, 11-nm FinFET, repair for RAMs
Inv.SRAMcell
DRAMSA
LW 8F2 1.5F2 15F2
Vtmax* 27 mV 34 mV 10 mV
3000F2 300F2
Cascodeamp
Diff.amp
Count*
LW
Count* 640M 2G 128M
Memory-rich LSILogic block (L)
RAM block (M)
Peri. Array
DL
cell
DL
WL
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Digital Assisted Analog Design-Pipeline ADC
Lower-Vt0MOSBetter signalintegrity
FinFETSmall VTmax/voffNo body effectSmall sub. noiseHigh-density C
(large LW)
High-Q inductor
VDD/VDHVDD/VDH VDD/VDH
Vin
( VDD) ( VDD) ( VDD) VDD( 0.5 V)
ADC
STG1
D1
1.9
D2 Dn
STG2 STGn Digital
Cal.
+ +
DAC
Vmin Vdyn( 0.5 V)
Vmin 3Vod+Vdyn0.9-0.7 V
VDH( VDD) VDD( Vmin)
0
vi
0
VDD
VDD
vi vi
vo
op-amp
Vmin 3Vod 0.4 V
VDD( Vmin)
0
vi vi
0
VodVod(.13 V)VDD
0
Vod
comp.
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Conclusion
The 1-V wall breached with adaptive circuits.
The 0.5-V nanoscale era will open the doorto lower power dissipation, if relevant devicesand fabrication processes are developed.
Disruptive inventions and technologies, whichsome of you may come up with, will makesuch an era an even closer reality.
2009 IEEE International Solid-State Circuits Conference 2009 IEEE
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