LAYOUTS

NAND2 layout

NOR2 layout

4 input NAND gate:( Not A preferrable layout)

8 input AND gate

2 I/P MUX AND ITS LAYOUT

F’ = (A.S+B.S’)

STICK DIAGRAMS

CONCEPT

• Popular Way Of symbolic design.

• Free hand layout

• Colored lines for various process layers.

• Poly crossing diffusion gives transistors.

• Metal touching diffusion gives contacts.

Concept• Notation gives only relative position of

various design components.

• A compactor is used to convert it into absolute design.

• The compactor translates design rules into constraints on the component positions.

• It also gives optimized design layout with efforts for minimization of area and cost function.

Pros and cons

• Designer does not have to worry about design rules.

• Compactor takes care of that.

• Outcome of the compactor may be unpredictable and may not match manual approach.

Typical Stick Diagram

Layers in the stick diagrams

The Procedur

e For Drawing

Stick Diagrams

:

Draw stick diagrams for the above circuits.

Back end optimization of a circuit

using

Euler's Graph approach

Constructing a minimum area Constructing a minimum area layout layout

Stick diagram layout of the complex CMOS logic gate with arbitrary ordering of poly gate columns.

Ordering of polysilicon gate columns in Euler graph sequence results in uninterrupted p-type and n-type diffusion areas.

Adv: Compact area, simple routing of signals and less parasitic capacitance.

Euler Graph Approach:(Good Density, Min Area, Abutting of S-D Connections, Single Diffusion Strip In Both Wells, , Easy Automation)

Construction Of Logic Graph:

1. Vertices : Nodes of the N/W.

2. Edge: I/P.

3. Dual Graphs for PUN & PDN.

Identification Of Euler Paths:

1. Path through all nodes such that an edge is visited only once.

2. Uninterrupted diffusion strip in the layout is possible iff Euler path exists.

3. Many solutions exist.

4. Common Euler path in PUN & PDN

5. Sequence of edges in the Euler path = Order of I/Ps in the layout.

E - D - A - B - C

Ex: 1.

Ex: 2.

Ex: 3.

Effect Of Restructuring

Ex: 3.

Effect Of Restructuring

Ex: 3.

Effect Of Restructuring

Sketch a stick diagram for a combinational circuit evaluating following Boolean expression.