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ECE C03 Lecture 1 1
Lecture 1Introduction to Digital Logic Design
Hai Zhou
ECE 303
Advanced Digital Design
Spring 2002
ECE C03 Lecture 1 2
Outline
• Class administration• Digital design methodology• Representations of Digital Design• Introduction to Mentor Graphics tools• READING: Katz 1.3, 1.4, Dewey 1.2, 1.3, 1.4
ECE C03 Lecture 1 3
Class Administration
• Lectures twice a week, Tuesday-Thursday 4:00-5:20PM• Instructor:
– Hai Zhou– Office: L461 Tech– EMAIL: haizhou@ece.nwu.edu– PHONE: 491-4155
• Teaching Assistant– Shizhong Mei– Office: M316 Tech– EMAIL: meisz@ece.nwu.edu
• Web Page: www.ece.nwu.edu/~haizhou/ece303.html
ECE C03 Lecture 1 4
Class Prerequisites
• ECE 203: Introduction to Computer Engineering– Need to have basic understanding of digital systems, logic
gates, combinational and sequential logic
• Need to have been exposed to UNIX since we will use the Mentor Graphics tools on HP/SUN workstations
• Class will form a background for other classes in Computer Engineering– ECE 357: Introduction to VLSI CAD– ECE C91: Introduction to VLSI Design– ECE C92: VLSI Design Projects
ECE C03 Lecture 1 5
Class Administration
• Required Textbooks:– R. Katz, “Contemporary Logic Design”, Benjamin
Cummings Press, 1994 (same text as ECE B01)
– Allen Dewey, “Analysis and Design of Digital Systems with VHDL”, PWS Publishing Company, 1997.
• Classnotes– Copies of lecture transparencies to be made available
ECE C03 Lecture 1 6
Class Grades• 5 Homeworks
– 25% of grade
• 5 Labs– 25% of grade
• Midterm exam– 20% of grade
• Final exam– 30% of grade
• Homeworks and labs will be due at the beginning of class on the due date– A penalty of 10% per working day will be assigned to late assignments or
labs
ECE C03 Lecture 1 7
Lab Work
• You will be introduced to the use of a commercial computer aided design tool from Mentor Graphics
• Will use the HP and Sun workstations in the Wilkinson Lab (3rd floor M wing of Tech)
• Lab Hours: Open• There will be 5 labs
– Lab 1: Tutorial on Mentor Graphics (simple logic)– Lab 2: Design of combinational logic (8-bit adder)– Lab 3: Design of ALU and shifter– Lab 4: Design of a simple 8-state finites state machine– Lab 5: Use of VHDL for combinational and sequential design
ECE C03 Lecture 1 8
The Process of Design
DesignInitial concept: what is the function performed by the object?Constraints: How fast? How much area? How much cost?Refine abstract functional blocks into more concrete realizations
Implementation
Assemble primitives into more complex building blocksComposition via wiringChoose among alternatives to improve the design
DebugFaulty systems: design flaws, composition flaws, component flawsDesign to make debugging easierHypothesis formation and troubleshooting skills
Implementation
Design
Debug
ECE C03 Lecture 1 9
Digital SystemsDigital vs. Analog Waveforms
Analog: values vary over a broad range continuously
Digital: only assumes discrete values
+5
V
–5
T ime
+5
V
–5
1 0 1
T ime
ECE C03 Lecture 1 10
Digital Hardware Systems
Algebra: variables, values, operations
In Boolean algebra, the values are the symbols 0 and 1 If a logic statement is false, it has value 0 If a logic statement is true, it has value 1
Operations: AND, OR, NOT
Boolean Algebra and Logical Operators
0 0 1 1
X Y X AND Y
0 1 0 1
0 0 0 1
X Y X OR Y
0 0 1 1
0 1 0 1
0 1 1 1
X NOT X
0 1
1 0
ECE C03 Lecture 1 11
Digital Hardware Systems
Combinational logic no feedback among inputs and outputs outputs are a pure function of the inputs e.g., full adder circuit: (A, B, Carry In) mapped into (Sum, Carry Out)
Network implemented from switching elements or logicgates. The presence of feedback distinguishes between sequentialand combinational networks.
Combinational vs. Sequential Logic
- - -
X 1 X 2 X n
Switching Network
Z 1 Z 2 Z m
- - -
A B Cin
Full Adder
Sum Cout
ECE C03 Lecture 1 12
Digital Hardware SystemsSequential logic
inputs and outputs overlap outputs depend on inputs and the entire history of execution!
network typically has only a limited number of unique configurations these are called states e.g., traffic light controller sequences infinitely through four states
new component in sequential logic networks: storage elements to remember the current state
output and new state is a function of the inputs and the old state i.e., the fed back inputs are the state!
Synchronous systemsperiod reference signal, the clock, causes the storage elements to accept new values and to change state
Asynchronous systemsno single indication of when to change state
ECE C03 Lecture 1
L1
L6
L2
L3
L7
L4
L5
Case Study of a Simple Logic Design: Seven Segment Display
• Chip to drive digital display
ECE C03 Lecture 1
B3 B2 B1 B0 Val L1 L2 L3 L4 L5 L6 L7
0 0 0 0 0 1 0 1 1 1 1 1
0 0 0 1 1 0 0 0 0 0 1 1
0 0 1 0 2 1 1 1 0 1 1 0
0 0 1 1 3 1 1 1 0 0 1 1
0 1 0 0 4 0 1 0 1 0 1 1
0 1 0 1 5 1 1 1 1 0 0 1
0 1 1 0 6 1 1 1 1 1 0 1
0 1 1 1 7 1 0 0 0 0 1 1
1 0 0 0 8 1 1 1 1 1 1 1
1 0 0 1 9 1 1 1 1 0 1 1
L1
L6
L2
L3
L7
L4
L5
Case Study (cont.)
ECE C03 Lecture 1
Case Study (cont.)
• Implement L4:
Some gate level implementationof the Boolean function for L4
ECE C03 Lecture 1 16
Representations of Digital Design: Switches
A switch connects two points under control signal.
when the control signal is 0 (false), the switch is open
when it is 1 (true), the switch is closed
when control is 1 (true), switch is open
when control is 0 (false), switch is closed
Normally Closed
Normally Open
Open Switch
Control
Normally Open Switch
Closed Switch
T rue
False
Open Switch
Control
Normally Closed Switch
Closed Switch
T rue
False
ECE C03 Lecture 1 17
Switch RepresentationsExamples: routing inputs to outputs through a maze
Floating nodes: what happens if the car is not running? outputs are floating rather than forced to be false
Under all possible control signal settings (1) all outputs must be connected to some input through a path (2) no output is connected to more than one input through any path
EXAMPLE: IF car in driveway OR (car in garage AND NOT garage door closed) AND car running THEN can back out car
Car in garage Car
running
True
True
Car can back out
Garage door closed
Car in driveway
EXAMPLE: IF car in garage AND garage door open AND car running THEN back out car
T rue Car can back out
Garage door open
Car running
Car in garage
ECE C03 Lecture 1 18
Switch Representations
Implementation of AND and OR Functions with Switches
A
False
T rue
output
B A
False
T rue
output
B
AND functionSeries connection to TRUE
OR functionParallel connection to TRUE
ECE C03 Lecture 1 19
Representations of a Digital Design
Truth Tables
tabulate all possible input combinations and their associated output values
Example: half adder adds two binary digits to form Sum and Carry
Example: full adder adds two binary digits and Carry in to form Sum and Carry Out
NOTE: 1 plus 1 is 0 with a carry of 1 in binary
A B
0 0 1 1
0 1 0 1
Sum Carry
0 1 1 0
0 0 0 1
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C in 0 1 0 1 0 1 0 1
S um 0 1 1 0 1 0 0 1
C out 0 0 0 1 0 1 1 1
ECE C03 Lecture 1 20
Representations of Digital Design: Boolean Algebra
NOT X is written as XX AND Y is written as X & Y, or sometimes X YX OR Y is written as X + Y
values: 0, 1variables: A, B, C, . . ., X, Y, Zoperations: NOT, AND, OR, . . .
A
0011
B
0101
Sum
0110
Carry
0001
Sum = A B + A B
Carry = A B
OR'd together product terms for each truth table
row where the function is 1
if input variable is 0, it appears in complemented form;
if 1, it appears uncomplemented
Deriving Boolean equations from truth tables:
ECE C03 Lecture 1 21
Representations of a Digital Design: Boolean Algebra
A
00001111
B
00110011
Cin
01010101
Sum
01101001
Cout
00010111
Another example:
Sum = A B Cin + A B Cin + A B Cin + A B Cin
Cout = A B Cin + A B Cin + A B Cin + A B Cin
ECE C03 Lecture 1 22
Gate Representations of a Digital Designmost widely used primitive building block in digital system design
StandardLogic Gate
RepresentationHalf Adder Schematic
Netlist: tabulation of gate inputs & outputs and the nets they are connected to
Net: electrically connected collection of wires
Inverter
AND
OR
Net 1
Net 2
A
B
CARR Y
SUM
ECE C03 Lecture 1 23
Representations of a Digital Design: Gates
Full Adder Schematic
Fan-in: number of inputs to a gateFan-out: number of gate inputs an output is connected to
Technology "Rules of Composition" place limits on fan-in/fan-out
Cin B A \Cin \ B \ A
A
B
Cin SUM
Cout
A B
B C in
A C in
C out
ECE C03 Lecture 1 24
Waveform Representationdynamic behavior of a circuitreal circuits have non-zero delays
Timing Diagram of the Half Adder
sumpropagation
delay
circuit hazard: 1 plus 0 is 1, not 0!
sumpropagation
delay
Output changes are delayed from input changes
The propagation delay is sensitive to paths in the circuit
Outputs may temporarily change from the correct value to the wrong value back again to the correct value: this is called a glitch or hazard
100 200
A B SUM CARR Y
ECE C03 Lecture 1 25
Block Representation of a Digital Designstructural organization of the design
black boxes with input and output connections
corresponds to well defined functions
concentrates on how the components are composed by wiring
Full Adder realized in terms ofcomposition of half adder blocks
Block diagram representationof the Full Adder
Sum
Cout
A
B
Cin
A
B
Sum
Carry HA
A
B
Sum
Carry HA
Sum
Cout
A
B
Cin
A
Cin
Sum
Cout
F A B
ECE C03 Lecture 1 26
Introduction to Mentor Graphics Tools
• The Mentor Graphics CAD system has many components
• You will use a small portion of the tools for this course– Falcon Design Framework– Design Architect for entering logic designs– Quicksim for simulating the designs– QuickHDL for entering and simulating the VHDL designs
• Read through and execute Lab 1: Mentor Graphics tutorial
ECE C03 Lecture 1 27
Introduction to Mentor Graphics
• Typing “source ~meisz/ECE303/mgc.env” on HP/Sun workstation will set up env for 303 labs
• Typing “dmgr” for Design Manager will create a window for running several tools
• Mentor Graphics is not a single tool tool but a series of design tools that uses object oriented data representation to simplify the design process
• Data created in one tool (e.g. design architect) can be shipped to another tool (e.g. quicksim) for simulation
• A schematic is merely a pictorial representation of a circuit
ECE C03 Lecture 1 28
Viewpoints in Electronic Design Objects• Data created by DESIGN ARCHITECT is
saved in– Component
– Viewpoint
• A component is a collection of models used to describe the functional, graphical aspects– Component data is made of a schematic and a
symbol
– A symbol is a graphical model of the input and output pins
– A schematic is a functional model of how outputs are related to input values
• A viewpoint can be thought of as a filter that other applications use to process component data
Component Viewpoint
Electronic Design Object
Symbol forXOR
ECE C03 Lecture 1 29
Moving Design Data
• Students familiar with UNIX, please refrain from using UNIX commands to move directories or files
• You MUST move these objects using the Design Manager
• Failure to use Design Manager will result in data corruption– Design Architect will store the absolute pathname to a
design
– Quicksim will try to use the symbol to look for the design from that pathname
ECE C03 Lecture 1 30
Summary
• Class administration• Digital design methodology• Representations of Digital Design• Introduction to Mentor Graphics tools• NEXT LECTURE: Two level Minimization • READING: Katz 2.1, 2.2, 2.3, Dewey 4.2, 4.3, 4.4